RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Code Issues Projects Releases Wiki Activity

[AMDGPU] Add new EmitDstSel field to VOPPofile. NFC.

Browse Source 
Differential Revision: https://reviews.llvm.org/D100589
This commit is contained in:
Stanislav Mekhanoshin 2021-04-15 11:45:45 -07:00
parent 3e03953b19
commit 5b15ced47a
3 changed files with 7 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
lib/Target/AMDGPU/SIInstrInfo.td
View File

@ -2100,6 +2100,7 @@ class VOPProfile <list<ValueType> _ArgVT, bit _EnableF32SrcMods = 0,
field bit HasDst = !ne(DstVT.Value, untyped.Value); field bit HasDst = !ne(DstVT.Value, untyped.Value);
field bit HasDst32 = HasDst; field bit HasDst32 = HasDst;
field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case field bit EmitDst = HasDst; // force dst encoding, see v_movreld_b32 special case
field bit EmitDstSel = EmitDst;
field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret; field int NumSrcArgs = getNumSrcArgs<Src0VT, Src1VT, Src2VT>.ret;
field bit HasSrc0 = !ne(Src0VT.Value, untyped.Value); field bit HasSrc0 = !ne(Src0VT.Value, untyped.Value);
field bit HasSrc1 = !ne(Src1VT.Value, untyped.Value); field bit HasSrc1 = !ne(Src1VT.Value, untyped.Value);

6
lib/Target/AMDGPU/VOPCInstructions.td
View File

@ -27,10 +27,6 @@ class VOPC_SDWAe <bits<8> op, VOPProfile P> : VOP_SDWAe <P> {
let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0); let Inst{16-9} = !if(P.HasSrc1, src1{7-0}, 0);
let Inst{24-17} = op; let Inst{24-17} = op;
let Inst{31-25} = 0x3e; // encoding let Inst{31-25} = 0x3e; // encoding
// VOPC disallows dst_sel and dst_unused as they have no effect on destination
let Inst{42-40} = 0;
let Inst{44-43} = 0;
} }
class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> { class VOPC_SDWA9e <bits<8> op, VOPProfile P> : VOP_SDWA9Be <P> {
@ -56,6 +52,8 @@ class VOPC_Profile<list<SchedReadWrite> sched, ValueType vt0, ValueType vt1 = vt
let Asm32 = "$src0, $src1"; let Asm32 = "$src0, $src1";
// The destination for 32-bit encoding is implicit. // The destination for 32-bit encoding is implicit.
let HasDst32 = 0; let HasDst32 = 0;
// VOPC disallows dst_sel and dst_unused as they have no effect on destination
let EmitDstSel = 0;
let Outs64 = (outs VOPDstS64orS32:$sdst); let Outs64 = (outs VOPDstS64orS32:$sdst);
list<SchedReadWrite> Schedule = sched; list<SchedReadWrite> Schedule = sched;
} }

8
lib/Target/AMDGPU/VOPInstructions.td
View File

@ -417,8 +417,8 @@ class VOP_SDWAe<VOPProfile P> : Enc64 {
bits<1> clamp; bits<1> clamp;
let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0); let Inst{39-32} = !if(P.HasSrc0, src0{7-0}, 0);
let Inst{42-40} = !if(P.EmitDst, dst_sel{2-0}, 0); let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, 0);
let Inst{44-43} = !if(P.EmitDst, dst_unused{1-0}, 0); let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, 0);
let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0);
let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0); let Inst{50-48} = !if(P.HasSrc0, src0_sel{2-0}, 0);
let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0); let Inst{51} = !if(P.HasSrc0IntMods, src0_modifiers{0}, 0);
@ -468,8 +468,8 @@ class VOP_SDWA9Ae<VOPProfile P> : VOP_SDWA9e<P> {
bits<1> clamp; bits<1> clamp;
bits<2> omod; bits<2> omod;
let Inst{42-40} = !if(P.EmitDst, dst_sel{2-0}, 0); let Inst{42-40} = !if(P.EmitDstSel, dst_sel{2-0}, 0);
let Inst{44-43} = !if(P.EmitDst, dst_unused{1-0}, 0); let Inst{44-43} = !if(P.EmitDstSel, dst_unused{1-0}, 0);
let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0); let Inst{45} = !if(P.HasSDWAClamp, clamp{0}, 0);
let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0); let Inst{47-46} = !if(P.HasSDWAOMod, omod{1-0}, 0);
} }