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[WebAssembly] Prototype i64x2.widen_{low,high}_i32x4_{s,u}

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As proposed in https://github.com/WebAssembly/simd/pull/290. As usual, these
instructions are available only via builtin functions and intrinsics while they
are in the prototyping stage.

Differential Revision: https://reviews.llvm.org/D90504
This commit is contained in:
Thomas Lively 2020-10-30 15:44:04 -07:00
parent 7964568963
commit 5b1fe216f7
4 changed files with 74 additions and 0 deletions
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13
include/llvm/IR/IntrinsicsWebAssembly.td
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@ -151,6 +151,7 @@ def int_wasm_dot :
Intrinsic<[llvm_v4i32_ty],
[llvm_v8i16_ty, llvm_v8i16_ty],
[IntrNoMem, IntrSpeculatable]>;
def int_wasm_narrow_signed :
Intrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, LLVMMatchType<1>],
@ -159,6 +160,18 @@ def int_wasm_narrow_unsigned :
Intrinsic<[llvm_anyvector_ty],
[llvm_anyvector_ty, LLVMMatchType<1>],
[IntrNoMem, IntrSpeculatable]>;
// TODO: Replace these intrinsics with normal ISel patterns once i32x4 to i64x2
// widening is merged to the proposal.
def int_wasm_widen_low_signed :
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
def int_wasm_widen_high_signed :
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
def int_wasm_widen_low_unsigned :
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
def int_wasm_widen_high_unsigned :
Intrinsic<[llvm_v2i64_ty], [llvm_v4i32_ty], [IntrNoMem, IntrSpeculatable]>;
def int_wasm_q15mulr_saturate_signed :
Intrinsic<[llvm_v8i16_ty],
[llvm_v8i16_ty, llvm_v8i16_ty],

9
lib/Target/WebAssembly/WebAssemblyInstrSIMD.td
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@ -1116,6 +1116,15 @@ multiclass SIMDWiden<ValueType vec_t, string vec, ValueType arg_t, string arg,
defm "" : SIMDWiden<v8i16, "i16x8", v16i8, "i8x16", 135>;
defm "" : SIMDWiden<v4i32, "i32x4", v8i16, "i16x8", 167>;
defm "" : SIMDConvert<v2i64, v4i32, int_wasm_widen_low_signed,
"i64x2.widen_low_i32x4_s", 199>;
defm "" : SIMDConvert<v2i64, v4i32, int_wasm_widen_high_signed,
"i64x2.widen_high_i32x4_s", 200>;
defm "" : SIMDConvert<v2i64, v4i32, int_wasm_widen_low_unsigned,
"i64x2.widen_low_i32x4_u", 201>;
defm "" : SIMDConvert<v2i64, v4i32, int_wasm_widen_high_unsigned,
"i64x2.widen_high_i32x4_u", 202>;
// Narrowing operations
multiclass SIMDNarrow<ValueType vec_t, string vec, ValueType arg_t, string arg,
bits<32> baseInst> {

40
test/CodeGen/WebAssembly/simd-intrinsics.ll
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@ -528,6 +528,46 @@ define <4 x i32> @trunc_sat_u_v4i32(<4 x float> %x) {
; ==============================================================================
; 2 x i64
; ==============================================================================
; CHECK-LABEL: widen_low_s_v2i64:
; SIMD128-NEXT: .functype widen_low_s_v2i64 (v128) -> (v128){{$}}
; SIMD128-NEXT: i64x2.widen_low_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32>)
define <2 x i64> @widen_low_s_v2i64(<4 x i32> %x) {
%a = call <2 x i64> @llvm.wasm.widen.low.signed(<4 x i32> %x)
ret <2 x i64> %a
}
; CHECK-LABEL: widen_high_s_v2i64:
; SIMD128-NEXT: .functype widen_high_s_v2i64 (v128) -> (v128){{$}}
; SIMD128-NEXT: i64x2.widen_high_i32x4_s $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32>)
define <2 x i64> @widen_high_s_v2i64(<4 x i32> %x) {
%a = call <2 x i64> @llvm.wasm.widen.high.signed(<4 x i32> %x)
ret <2 x i64> %a
}
; CHECK-LABEL: widen_low_u_v2i64:
; SIMD128-NEXT: .functype widen_low_u_v2i64 (v128) -> (v128){{$}}
; SIMD128-NEXT: i64x2.widen_low_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32>)
define <2 x i64> @widen_low_u_v2i64(<4 x i32> %x) {
%a = call <2 x i64> @llvm.wasm.widen.low.unsigned(<4 x i32> %x)
ret <2 x i64> %a
}
; CHECK-LABEL: widen_high_u_v2i64:
; SIMD128-NEXT: .functype widen_high_u_v2i64 (v128) -> (v128){{$}}
; SIMD128-NEXT: i64x2.widen_high_i32x4_u $push[[R:[0-9]+]]=, $0{{$}}
; SIMD128-NEXT: return $pop[[R]]{{$}}
declare <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32>)
define <2 x i64> @widen_high_u_v2i64(<4 x i32> %x) {
%a = call <2 x i64> @llvm.wasm.widen.high.unsigned(<4 x i32> %x)
ret <2 x i64> %a
}
; CHECK-LABEL: extmul_low_s_v2i64:
; SIMD128-NEXT: .functype extmul_low_s_v2i64 (v128, v128) -> (v128){{$}}
; SIMD128-NEXT: i64x2.extmul_low_i32x4_s $push[[R:[0-9]+]]=, $0, $1{{$}}

12
test/MC/WebAssembly/simd-encodings.s
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@ -520,6 +520,18 @@ main:
# CHECK: i64x2.all_true # encoding: [0xfd,0xc3,0x01]
i64x2.all_true
# CHECK: i64x2.widen_low_i32x4_s # encoding: [0xfd,0xc7,0x01]
i64x2.widen_low_i32x4_s
# CHECK: i64x2.widen_high_i32x4_s # encoding: [0xfd,0xc8,0x01]
i64x2.widen_high_i32x4_s
# CHECK: i64x2.widen_low_i32x4_u # encoding: [0xfd,0xc9,0x01]
i64x2.widen_low_i32x4_u
# CHECK: i64x2.widen_high_i32x4_u # encoding: [0xfd,0xca,0x01]
i64x2.widen_high_i32x4_u
# CHECK: i64x2.shl # encoding: [0xfd,0xcb,0x01]
i64x2.shl