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[mips] Tidy up cnMIPS tablegen definitions. NFC.
Summary:
In particular, make the cnMIPS predicates much more obvious and prefer
def ... : ... {
let Foo = bar;
}
over:
let Foo = bar in
def ... : ...;
Reviewers: vkalintiris
Subscribers: dsanders, llvm-commits
Differential Revision: http://reviews.llvm.org/D18354
llvm-svn: 264258
This commit is contained in:
Daniel Sanders
parent
f64e5bc3d4
commit
5b6379a5b2
@ -307,8 +307,8 @@ def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
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// Cavium Octeon cnMIPS instructions
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let DecoderNamespace = "CnMips",
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EncodingPredicates = []<Predicate>, // FIXME: The lack of HasStdEnc is probably a bug
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AdditionalPredicates = [HasCnMips] in {
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// FIXME: The lack of HasStdEnc is probably a bug
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EncodingPredicates = []<Predicate> in {
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class Count1s<string opstr, RegisterOperand RO>:
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InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"),
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@ -359,73 +359,80 @@ class MFC2OP<string asmstr, RegisterOperand RO> :
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!strconcat(asmstr, "\t$rt, $imm16"), [], NoItinerary, FrmFR>;
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// Unsigned Byte Add
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let Pattern = [(set GPR64Opnd:$rd,
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(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))] in
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def BADDu : ArithLogicR<"baddu", GPR64Opnd, 1, II_BADDU>,
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ADD_FM<0x1c, 0x28>;
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ADD_FM<0x1c, 0x28>, ASE_CNMIPS {
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let Pattern = [(set GPR64Opnd:$rd,
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(and (add GPR64Opnd:$rs, GPR64Opnd:$rt), 255))];
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}
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// Branch on Bit Clear /+32
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def BBIT0 : CBranchBitNum<"bbit0", brtarget, seteq, GPR64Opnd,
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uimm5_64_report_uimm6>, BBIT_FM<0x32>;
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uimm5_64_report_uimm6>, BBIT_FM<0x32>, ASE_CNMIPS;
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def BBIT032: CBranchBitNum<"bbit032", brtarget, seteq, GPR64Opnd, uimm5_64,
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0x100000000>,
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BBIT_FM<0x36>;
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0x100000000>, BBIT_FM<0x36>, ASE_CNMIPS;
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// Branch on Bit Set /+32
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def BBIT1 : CBranchBitNum<"bbit1", brtarget, setne, GPR64Opnd,
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uimm5_64_report_uimm6>, BBIT_FM<0x3a>;
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uimm5_64_report_uimm6>, BBIT_FM<0x3a>, ASE_CNMIPS;
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def BBIT132: CBranchBitNum<"bbit132", brtarget, setne, GPR64Opnd, uimm5_64,
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0x100000000>, BBIT_FM<0x3e>;
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0x100000000>, BBIT_FM<0x3e>, ASE_CNMIPS;
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// Multiply Doubleword to GPR
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let Defs = [HI0, LO0, P0, P1, P2] in
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def DMUL : ArithLogicR<"dmul", GPR64Opnd, 1, II_DMUL, mul>,
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ADD_FM<0x1c, 0x03>;
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ADD_FM<0x1c, 0x03>, ASE_CNMIPS {
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let Defs = [HI0, LO0, P0, P1, P2];
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}
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// Extract a signed bit field /+32
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def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>;
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def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>;
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def EXTS : ExtsCins<"exts">, EXTS_FM<0x3a>, ASE_CNMIPS;
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def EXTS32: ExtsCins<"exts32">, EXTS_FM<0x3b>, ASE_CNMIPS;
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// Clear and insert a bit field /+32
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def CINS : ExtsCins<"cins">, EXTS_FM<0x32>;
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def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>;
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def CINS : ExtsCins<"cins">, EXTS_FM<0x32>, ASE_CNMIPS;
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def CINS32: ExtsCins<"cins32">, EXTS_FM<0x33>, ASE_CNMIPS;
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// Move to multiplier/product register
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def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>;
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def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>;
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def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>;
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def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>;
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def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>;
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def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>;
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def MTM0 : MoveToLOHI<"mtm0", GPR64Opnd, [MPL0, P0, P1, P2]>, MTMR_FM<0x08>,
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ASE_CNMIPS;
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def MTM1 : MoveToLOHI<"mtm1", GPR64Opnd, [MPL1, P0, P1, P2]>, MTMR_FM<0x0c>,
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ASE_CNMIPS;
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def MTM2 : MoveToLOHI<"mtm2", GPR64Opnd, [MPL2, P0, P1, P2]>, MTMR_FM<0x0d>,
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ASE_CNMIPS;
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def MTP0 : MoveToLOHI<"mtp0", GPR64Opnd, [P0]>, MTMR_FM<0x09>, ASE_CNMIPS;
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def MTP1 : MoveToLOHI<"mtp1", GPR64Opnd, [P1]>, MTMR_FM<0x0a>, ASE_CNMIPS;
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def MTP2 : MoveToLOHI<"mtp2", GPR64Opnd, [P2]>, MTMR_FM<0x0b>, ASE_CNMIPS;
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// Count Ones in a Word/Doubleword
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def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>;
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def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>;
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def POP : Count1s<"pop", GPR32Opnd>, POP_FM<0x2c>, ASE_CNMIPS;
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def DPOP : Count1s<"dpop", GPR64Opnd>, POP_FM<0x2d>, ASE_CNMIPS;
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// Set on equal/not equal
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def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>;
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def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>;
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def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>;
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def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>;
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def SEQ : SetCC64_R<"seq", seteq>, SEQ_FM<0x2a>, ASE_CNMIPS;
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def SEQi : SetCC64_I<"seqi", seteq>, SEQI_FM<0x2e>, ASE_CNMIPS;
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def SNE : SetCC64_R<"sne", setne>, SEQ_FM<0x2b>, ASE_CNMIPS;
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def SNEi : SetCC64_I<"snei", setne>, SEQI_FM<0x2f>, ASE_CNMIPS;
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// 192-bit x 64-bit Unsigned Multiply and Add
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let Defs = [P0, P1, P2] in
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def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>,
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ADD_FM<0x1c, 0x11>;
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def V3MULU: ArithLogicR<"v3mulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x11>,
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ASE_CNMIPS {
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let Defs = [P0, P1, P2];
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}
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// 64-bit Unsigned Multiply and Add Move
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let Defs = [MPL0, P0, P1, P2] in
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def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>,
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ADD_FM<0x1c, 0x10>;
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def VMM0 : ArithLogicR<"vmm0", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x10>,
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ASE_CNMIPS {
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let Defs = [MPL0, P0, P1, P2];
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}
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// 64-bit Unsigned Multiply and Add
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let Defs = [MPL1, MPL2, P0, P1, P2] in
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def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>,
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ADD_FM<0x1c, 0x0f>;
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def VMULU : ArithLogicR<"vmulu", GPR64Opnd, 0, II_DMUL>, ADD_FM<0x1c, 0x0f>,
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ASE_CNMIPS {
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let Defs = [MPL1, MPL2, P0, P1, P2];
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}
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// Move between CPU and coprocessor registers
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def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>;
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def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>;
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def DMFC2_OCTEON : MFC2OP<"dmfc2", GPR64Opnd>, MFC2OP_FM<0x12, 1>, ASE_CNMIPS;
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def DMTC2_OCTEON : MFC2OP<"dmtc2", GPR64Opnd>, MFC2OP_FM<0x12, 5>, ASE_CNMIPS;
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}
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}
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@ -539,16 +546,14 @@ let AdditionalPredicates = [NotDSP] in {
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}
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// Octeon bbit0/bbit1 MipsPattern
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let Predicates = [HasMips64, HasCnMips] in {
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def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
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(BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
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(BBIT0 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
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def : MipsPat<(brcond (i32 (seteq (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
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(BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
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(BBIT032 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
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def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2LO:$mask), 0)), bb:$dst),
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(BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>;
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(BBIT1 i64:$lhs, (Log2LO PowerOf2LO:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
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def : MipsPat<(brcond (i32 (setne (and i64:$lhs, PowerOf2HI:$mask), 0)), bb:$dst),
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(BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>;
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}
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(BBIT132 i64:$lhs, (Log2HI PowerOf2HI:$mask), bb:$dst)>, ASE_MIPS64_CNMIPS;
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// Atomic load patterns.
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def : MipsPat<(atomic_load_8 addr:$a), (LB64 addr:$a)>;
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@ -634,12 +639,10 @@ let AdditionalPredicates = [NotInMicroMips] in {
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def : MipsInstAlias<"dmfc2 $rt, $rd", (DMFC2 GPR64Opnd:$rt, COP2Opnd:$rd, 0), 0>;
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def : MipsInstAlias<"dmtc2 $rt, $rd", (DMTC2 COP2Opnd:$rd, GPR64Opnd:$rt, 0), 0>;
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let Predicates = [HasMips64, HasCnMips] in {
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def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>;
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def : MipsInstAlias<"syncs", (SYNC 0x6), 0>;
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def : MipsInstAlias<"syncw", (SYNC 0x4), 0>;
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def : MipsInstAlias<"syncws", (SYNC 0x5), 0>;
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}
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def : MipsInstAlias<"synciobdma", (SYNC 0x2), 0>, ASE_MIPS64_CNMIPS;
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def : MipsInstAlias<"syncs", (SYNC 0x6), 0>, ASE_MIPS64_CNMIPS;
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def : MipsInstAlias<"syncw", (SYNC 0x4), 0>, ASE_MIPS64_CNMIPS;
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def : MipsInstAlias<"syncws", (SYNC 0x5), 0>, ASE_MIPS64_CNMIPS;
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// cnMIPS Aliases.
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@ -315,6 +315,10 @@ class ASE_CNMIPS {
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list<Predicate> InsnPredicates = [HasCnMips];
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}
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class ASE_MIPS64_CNMIPS {
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list<Predicate> InsnPredicates = [HasMips64, HasCnMips];
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}
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class ASE_MSA {
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list<Predicate> InsnPredicates = [HasMSA];
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}
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