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[SelectionDAG] ComputeKnownBits - Add DemandedElts support to getValidShiftAmountConstant/getValidMinimumShiftAmountConstant()

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This commit is contained in:
Simon Pilgrim 2020-01-13 13:35:12 +00:00
parent cddab58467
commit 5bd29598ab
3 changed files with 17 additions and 17 deletions
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22
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
View File

@ -2411,9 +2411,10 @@ SDValue SelectionDAG::getSplatValue(SDValue V) {
/// If a SHL/SRA/SRL node has a constant or splat constant shift amount that
/// is less than the element bit-width of the shift node, return it.
static const APInt *getValidShiftAmountConstant(SDValue V) {
static const APInt *getValidShiftAmountConstant(SDValue V,
const APInt &DemandedElts) {
unsigned BitWidth = V.getScalarValueSizeInBits();
if (ConstantSDNode *SA = isConstOrConstSplat(V.getOperand(1))) {
if (ConstantSDNode *SA = isConstOrConstSplat(V.getOperand(1), DemandedElts)) {
// Shifting more than the bitwidth is not valid.
const APInt &ShAmt = SA->getAPIntValue();
if (ShAmt.ult(BitWidth))
@ -2424,13 +2425,16 @@ static const APInt *getValidShiftAmountConstant(SDValue V) {
/// If a SHL/SRA/SRL node has constant vector shift amounts that are all less
/// than the element bit-width of the shift node, return the minimum value.
static const APInt *getValidMinimumShiftAmountConstant(SDValue V) {
static const APInt *
getValidMinimumShiftAmountConstant(SDValue V, const APInt &DemandedElts) {
unsigned BitWidth = V.getScalarValueSizeInBits();
auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
if (!BV)
return nullptr;
const APInt *MinShAmt = nullptr;
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
if (!DemandedElts[i])
continue;
auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
if (!SA)
return nullptr;
@ -2827,14 +2831,15 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
break;
}
case ISD::SHL:
if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
if (const APInt *ShAmt = getValidShiftAmountConstant(Op, DemandedElts)) {
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
unsigned Shift = ShAmt->getZExtValue();
Known.Zero <<= Shift;
Known.One <<= Shift;
// Low bits are known zero.
Known.Zero.setLowBits(Shift);
} else if (const APInt *ShMinAmt = getValidMinimumShiftAmountConstant(Op)) {
} else if (const APInt *ShMinAmt =
getValidMinimumShiftAmountConstant(Op, DemandedElts)) {
// Minimum shift low bits are known zero.
Known.Zero.setLowBits(ShMinAmt->getZExtValue());
} else {
@ -2846,14 +2851,15 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
}
break;
case ISD::SRL:
if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
if (const APInt *ShAmt = getValidShiftAmountConstant(Op, DemandedElts)) {
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
unsigned Shift = ShAmt->getZExtValue();
Known.Zero.lshrInPlace(Shift);
Known.One.lshrInPlace(Shift);
// High bits are known zero.
Known.Zero.setHighBits(Shift);
} else if (const APInt *ShMinAmt = getValidMinimumShiftAmountConstant(Op)) {
} else if (const APInt *ShMinAmt =
getValidMinimumShiftAmountConstant(Op, DemandedElts)) {
// Minimum shift high bits are known zero.
Known.Zero.setHighBits(ShMinAmt->getZExtValue());
} else {
@ -2864,7 +2870,7 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
}
break;
case ISD::SRA:
if (const APInt *ShAmt = getValidShiftAmountConstant(Op)) {
if (const APInt *ShAmt = getValidShiftAmountConstant(Op, DemandedElts)) {
Known = computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
unsigned Shift = ShAmt->getZExtValue();
// Sign extend known zero/one bit (else is unknown).

2
test/CodeGen/X86/combine-shl.ll
View File

@ -891,7 +891,7 @@ define <4 x i32> @combine_vec_add_shuffle_shl(<4 x i32> %a0) {
; AVX-NEXT: vpsllvd {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[0,1,1,0]
; AVX-NEXT: vpbroadcastd {{.*#+}} xmm1 = [3,3,3,3]
; AVX-NEXT: vpaddd %xmm1, %xmm0, %xmm0
; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0
; AVX-NEXT: retq
%1 = shl <4 x i32> %a0, <i32 2, i32 3, i32 0, i32 1>
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <4 x i32> <i32 0, i32 1, i32 1, i32 0>

10
test/CodeGen/X86/known-bits-vector.ll
View File

@ -671,10 +671,7 @@ define <2 x double> @knownbits_lshr_subvector_uitofp(<4 x i32> %x) {
; X32-NEXT: vpsrld $2, %xmm0, %xmm1
; X32-NEXT: vpsrld $1, %xmm0, %xmm0
; X32-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
; X32-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; X32-NEXT: vmovdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; X32-NEXT: vpor %xmm1, %xmm0, %xmm0
; X32-NEXT: vsubpd %xmm1, %xmm0, %xmm0
; X32-NEXT: vcvtdq2pd %xmm0, %xmm0
; X32-NEXT: retl
;
; X64-LABEL: knownbits_lshr_subvector_uitofp:
@ -682,10 +679,7 @@ define <2 x double> @knownbits_lshr_subvector_uitofp(<4 x i32> %x) {
; X64-NEXT: vpsrld $2, %xmm0, %xmm1
; X64-NEXT: vpsrld $1, %xmm0, %xmm0
; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
; X64-NEXT: vpmovzxdq {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero
; X64-NEXT: vmovdqa {{.*#+}} xmm1 = [4.503599627370496E+15,4.503599627370496E+15]
; X64-NEXT: vpor %xmm1, %xmm0, %xmm0
; X64-NEXT: vsubpd %xmm1, %xmm0, %xmm0
; X64-NEXT: vcvtdq2pd %xmm0, %xmm0
; X64-NEXT: retq
%1 = lshr <4 x i32> %x, <i32 1, i32 2, i32 0, i32 0>
%2 = shufflevector <4 x i32> %1, <4 x i32> undef, <2 x i32> <i32 0, i32 1>