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[SystemZ] [z/OS] Add XPLINK64 Calling Convention to SystemZ
This patch adds the XPLINK64 calling convention to the SystemZ backend. It specifies and implements the argument passing and return value conventions. Reviewed By: uweigand Differential Revision: https://reviews.llvm.org/D101010
This commit is contained in:
Neumann Hon
Kai Nacke
parent
7a1762f190
commit
5bf2202796
@ -18,3 +18,13 @@ const MCPhysReg SystemZ::ELFArgGPRs[SystemZ::ELFNumArgGPRs] = {
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const MCPhysReg SystemZ::ELFArgFPRs[SystemZ::ELFNumArgFPRs] = {
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SystemZ::F0D, SystemZ::F2D, SystemZ::F4D, SystemZ::F6D
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};
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// The XPLINK64 ABI-defined param passing general purpose registers
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const MCPhysReg SystemZ::XPLINK64ArgGPRs[SystemZ::XPLINK64NumArgGPRs] = {
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SystemZ::R1D, SystemZ::R2D, SystemZ::R3D
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};
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// The XPLINK64 ABI-defined param passing floating point registers
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const MCPhysReg SystemZ::XPLINK64ArgFPRs[SystemZ::XPLINK64NumArgFPRs] = {
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SystemZ::F0D, SystemZ::F2D, SystemZ::F4D, SystemZ::F6D
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};
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@ -9,6 +9,7 @@
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#ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZCALLINGCONV_H
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#define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZCALLINGCONV_H
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#include "SystemZSubtarget.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/MC/MCRegisterInfo.h"
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@ -20,6 +21,12 @@ namespace SystemZ {
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const unsigned ELFNumArgFPRs = 4;
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extern const MCPhysReg ELFArgFPRs[ELFNumArgFPRs];
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const unsigned XPLINK64NumArgGPRs = 3;
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extern const MCPhysReg XPLINK64ArgGPRs[XPLINK64NumArgGPRs];
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const unsigned XPLINK64NumArgFPRs = 4;
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extern const MCPhysReg XPLINK64ArgFPRs[XPLINK64NumArgFPRs];
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} // end namespace SystemZ
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class SystemZCCState : public CCState {
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@ -107,7 +114,16 @@ inline bool CC_SystemZ_I128Indirect(unsigned &ValNo, MVT &ValVT,
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// OK, we've collected all parts in the pending list. Allocate
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// the location (register or stack slot) for the indirect pointer.
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// (This duplicates the usual i64 calling convention rules.)
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unsigned Reg = State.AllocateReg(SystemZ::ELFArgGPRs);
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unsigned Reg;
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const SystemZSubtarget &Subtarget =
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State.getMachineFunction().getSubtarget<SystemZSubtarget>();
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if (Subtarget.isTargetELF())
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Reg = State.AllocateReg(SystemZ::ELFArgGPRs);
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else if (Subtarget.isTargetXPLINK64())
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Reg = State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
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else
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llvm_unreachable("Unknown Calling Convention!");
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unsigned Offset = Reg ? 0 : State.AllocateStack(8, Align(8));
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// Use that same location for all the pending parts.
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@ -124,6 +140,80 @@ inline bool CC_SystemZ_I128Indirect(unsigned &ValNo, MVT &ValVT,
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return true;
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}
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inline bool CC_XPLINK64_Shadow_Reg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags, CCState &State) {
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if (LocVT == MVT::f32 || LocVT == MVT::f64) {
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State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
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}
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if (LocVT == MVT::f128 || LocVT.is128BitVector()) {
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// Shadow next two GPRs, if available.
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State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
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State.AllocateReg(SystemZ::XPLINK64ArgGPRs);
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// Quad precision floating point needs to
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// go inside pre-defined FPR pair.
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if (LocVT == MVT::f128) {
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for (unsigned I = 0; I < SystemZ::XPLINK64NumArgFPRs; I += 2)
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if (State.isAllocated(SystemZ::XPLINK64ArgFPRs[I]))
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State.AllocateReg(SystemZ::XPLINK64ArgFPRs[I + 1]);
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}
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}
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return false;
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}
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inline bool CC_XPLINK64_Allocate128BitVararg(unsigned &ValNo, MVT &ValVT,
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MVT &LocVT,
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CCValAssign::LocInfo &LocInfo,
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ISD::ArgFlagsTy &ArgFlags,
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CCState &State) {
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if (LocVT.getSizeInBits() < 128)
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return false;
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if (static_cast<SystemZCCState *>(&State)->IsFixed(ValNo))
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return false;
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// For any C or C++ program, this should always be
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// false, since it is illegal to have a function
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// where the first argument is variadic. Therefore
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// the first fixed argument should already have
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// allocated GPR1 either through shadowing it or
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// using it for parameter passing.
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State.AllocateReg(SystemZ::R1D);
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bool AllocGPR2 = State.AllocateReg(SystemZ::R2D);
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bool AllocGPR3 = State.AllocateReg(SystemZ::R3D);
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// If GPR2 and GPR3 are available, then we may pass vararg in R2Q.
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if (AllocGPR2 && AllocGPR3) {
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State.addLoc(
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CCValAssign::getReg(ValNo, ValVT, SystemZ::R2Q, LocVT, LocInfo));
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return true;
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}
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// If only GPR3 is available, we allocate on stack but need to
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// set custom handling to copy hi bits into GPR3.
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if (!AllocGPR2 && AllocGPR3) {
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auto Offset = State.AllocateStack(16, Align(8));
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State.addLoc(
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CCValAssign::getCustomMem(ValNo, ValVT, Offset, LocVT, LocInfo));
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return true;
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}
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return false;
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}
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inline bool RetCC_SystemZ_Error(unsigned &, MVT &, MVT &,
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CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
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CCState &) {
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llvm_unreachable("Return value calling convention currently unsupported.");
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}
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inline bool CC_SystemZ_Error(unsigned &, MVT &, MVT &, CCValAssign::LocInfo &,
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ISD::ArgFlagsTy &, CCState &) {
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llvm_unreachable("Argument calling convention currently unsupported.");
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}
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inline bool CC_SystemZ_GHC_Error(unsigned &, MVT &, MVT &,
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CCValAssign::LocInfo &, ISD::ArgFlagsTy &,
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CCState &) {
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@ -20,6 +20,10 @@ class CCIfSubtarget<string F, CCAction A>
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class CCIfFixed<CCAction A>
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: CCIf<"static_cast<SystemZCCState *>(&State)->IsFixed(ValNo)", A>;
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// Match if this specific argument is not a fixed (i.e. vararg) argument.
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class CCIfNotFixed<CCAction A>
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: CCIf<"!(static_cast<SystemZCCState *>(&State)->IsFixed(ValNo))", A>;
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// Match if this specific argument was widened from a short vector type.
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class CCIfShortVector<CCAction A>
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: CCIf<"static_cast<SystemZCCState *>(&State)->IsShortVector(ValNo)", A>;
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@ -161,11 +165,133 @@ def CSR_SystemZ_NoRegs : CalleeSavedRegs<(add)>;
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def CSR_SystemZ_XPLINK64 : CalleeSavedRegs<(add (sequence "R%dD", 8, 15),
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(sequence "F%dD", 8, 15))>;
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def CSR_SystemZ_XPLINK64_Vector : CalleeSavedRegs<(add (sequence "R%dD", 8, 15),
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(sequence "F%dD", 15, 8),
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(sequence "V%d", 23, 16))>;
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//===----------------------------------------------------------------------===//
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// z/OS XPLINK64 return value calling convention
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//===----------------------------------------------------------------------===//
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def RetCC_SystemZ_XPLINK64 : CallingConv<[
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// XPLINK64 ABI compliant code widens integral types smaller than i64
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// to i64.
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CCIfType<[i32], CCPromoteToType<i64>>,
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// Structs of size 1-24 bytes are returned in R1D, R2D, and R3D.
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CCIfType<[i64], CCIfInReg<CCAssignToReg<[R1D, R2D, R3D]>>>,
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// An i64 is returned in R3D. R2D and R1D provided for ABI non-compliant
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// code.
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CCIfType<[i64], CCAssignToReg<[R3D, R2D, R1D]>>,
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// ABI compliant code returns floating point values in FPR0, FPR2, FPR4
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// and FPR6, using as many registers as required.
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// All floating point return-value registers are call-clobbered.
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CCIfType<[f32], CCAssignToReg<[F0S, F2S, F4S, F6S]>>,
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CCIfType<[f64], CCAssignToReg<[F0D, F2D, F4D, F6D]>>,
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// ABI compliant code returns f128 in F0D and F2D, hence F0Q.
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// F4D and F6D, hence F4Q are used for complex long double types.
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CCIfType<[f128], CCAssignToReg<[F0Q,F4Q]>>,
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// ABI compliant code returns vectors in VR24 but other registers
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// are provided for code that does not care about the ABI.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToReg<[V24, V25, V26, V27, V28, V29, V30, V31]>>>
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]>;
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//===----------------------------------------------------------------------===//
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// z/OS XPLINK64 argument calling conventions
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//===----------------------------------------------------------------------===//
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// XPLink uses a logical argument list consisting of contiguous register-size
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// words (8 bytes in 64-Bit mode) where some arguments are passed in registers
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// and some in storage.
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// Even though 3 GPRs, 4 FPRs, and 8 VRs may be used,
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// space must be reserved for all the args on stack.
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// The first three register-sized words of the parameter area are passed in
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// GPRs 1-3. FP values and vector-type arguments are instead passed in FPRs
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// and VRs respectively, but if a FP value or vector argument occupies one of
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// the first three register-sized words of the parameter area, the corresponding
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// GPR's value is not used to pass arguments.
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//
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// The XPLINK64 Calling Convention is fully specified in Chapter 22 of the z/OS
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// Language Environment Vendor Interfaces. Appendix B of the same document contains
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// examples.
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def CC_SystemZ_XPLINK64 : CallingConv<[
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// XPLINK64 ABI compliant code widens integral types smaller than i64
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// to i64 before placing the parameters either on the stack or in registers.
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CCIfType<[i32], CCIfExtend<CCPromoteToType<i64>>>,
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// A SwiftSelf is passed in callee-saved R10.
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CCIfSwiftSelf<CCIfType<[i64], CCAssignToReg<[R10D]>>>,
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// A SwiftError is passed in R0.
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CCIfSwiftError<CCIfType<[i64], CCAssignToReg<[R0D]>>>,
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// First i128 values. These are already split into two i64 here,
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// so we have to use a custom handler and assign into registers, if possible
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// We need to deal with this first
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CCIfType<[i64], CCCustom<"CC_SystemZ_I128Indirect">>,
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// The first 3 integer arguments are passed in registers R1D-R3D.
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// The rest will be passed in the user area. The address offset of the user
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// area can be found in register R4D.
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CCIfType<[i32], CCAssignToReg<[R1L, R2L, R3L]>>,
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CCIfType<[i64], CCAssignToReg<[R1D, R2D, R3D]>>,
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// The first 8 named vector arguments are passed in V24-V31. Sub-128 vectors
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// are passed in the same way, but they're widened to one of these types
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// during type legalization.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Reg">>>>,
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfFixed<CCAssignToReg<[V24, V25, V26, V27,
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V28, V29, V30, V31]>>>>,
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// The first 4 named float and double arguments are passed in registers FPR0-FPR6.
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// The rest will be passed in the user area.
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CCIfType<[f32, f64], CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Reg">>>,
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CCIfType<[f32], CCIfFixed<CCAssignToReg<[F0S, F2S, F4S, F6S]>>>,
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CCIfType<[f64], CCIfFixed<CCAssignToReg<[F0D, F2D, F4D, F6D]>>>,
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// The first 2 long double arguments are passed in register FPR0/FPR2
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// and FPR4/FPR6. The rest will be passed in the user area.
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CCIfType<[f128], CCIfFixed<CCCustom<"CC_XPLINK64_Shadow_Reg">>>,
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CCIfType<[f128], CCIfFixed<CCAssignToReg<[F0Q, F4Q]>>>,
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// Non fixed floats are passed in GPRs
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// Promote f32 to f64, if it needs to be passed in GPRs.
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CCIfType<[f32], CCIfNotFixed<CCPromoteToType<f64>>>,
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// Assign f64 varargs to their proper GPRs.
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CCIfType<[f64], CCIfNotFixed<CCAssignToReg<[R1D, R2D, R3D]>>>,
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// long double, can only be passed in GPR2 and GPR3, if available,
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// hence R2Q
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CCIfType<[f128], CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>,
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// Non fixed vector arguments are treated in the same way as long
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// doubles.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCIfNotFixed<CCCustom<"CC_XPLINK64_Allocate128BitVararg">>>>,
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// Other arguments are passed in 8-byte-aligned 8-byte stack slots.
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CCIfType<[i32, i64, f32, f64], CCAssignToStack<8, 8>>,
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// Other f128 arguments are passed in 8-byte-aligned 16-byte stack slots.
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CCIfType<[f128], CCAssignToStack<16, 8>>,
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// Vector arguments are passed in 8-byte-alinged 16-byte stack slots too.
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CCIfSubtarget<"hasVector()",
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CCIfType<[v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
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CCAssignToStack<16, 8>>>
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]>;
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//===----------------------------------------------------------------------===//
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// s390x return value calling convention
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//===----------------------------------------------------------------------===//
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def RetCC_SystemZ : CallingConv<[
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// zOS XPLINK64
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CCIfSubtarget<"isTargetXPLINK64()", CCDelegateTo<RetCC_SystemZ_XPLINK64>>,
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// ELF Linux SystemZ
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CCIfSubtarget<"isTargetELF()", CCDelegateTo<RetCC_SystemZ_ELF>>
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@ -176,6 +302,8 @@ def RetCC_SystemZ : CallingConv<[
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// s390x argument calling conventions
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//===----------------------------------------------------------------------===//
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def CC_SystemZ : CallingConv<[
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// zOS XPLINK64
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CCIfSubtarget<"isTargetXPLINK64()", CCDelegateTo<CC_SystemZ_XPLINK64>>,
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// ELF Linux SystemZ
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CCIfSubtarget<"isTargetELF()", CCDelegateTo<CC_SystemZ_ELF>>
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