mirror of
https://github.com/RPCS3/llvm-mirror.git
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GlobalISel/TableGen: Handle setcc patterns
This is a special case because one node maps to two different G_ instructions, and the operand order is changed. This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually selected for now since it has the SALU and VALU complication to deal with. llvm-svn: 370280
This commit is contained in:
Matt Arsenault
parent
e7c18d7291
commit
5bfe49f2ac
@ -208,6 +208,12 @@ enum {
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/// - Expected Intrinsic ID
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GIM_CheckIntrinsicID,
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/// Check the operand is a specific predicate
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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/// - Expected predicate
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GIM_CheckCmpPredicate,
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/// Check the specified operand is an MBB
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/// - InsnID - Instruction ID
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/// - OpIdx - Operand index
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@ -662,7 +662,21 @@ bool InstructionSelector::executeMatchTable(
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return false;
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break;
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}
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case GIM_CheckCmpPredicate: {
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int64_t InsnID = MatchTable[CurrentIdx++];
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int64_t OpIdx = MatchTable[CurrentIdx++];
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int64_t Value = MatchTable[CurrentIdx++];
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DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
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dbgs() << CurrentIdx << ": GIM_CheckCmpPredicate(MIs["
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<< InsnID << "]->getOperand(" << OpIdx
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<< "), Value=" << Value << ")\n");
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assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
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MachineOperand &MO = State.MIs[InsnID]->getOperand(OpIdx);
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if (!MO.isPredicate() || MO.getPredicate() != Value)
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if (handleReject() == RejectAndGiveUp)
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return false;
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break;
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}
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case GIM_CheckIsMBB: {
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int64_t InsnID = MatchTable[CurrentIdx++];
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int64_t OpIdx = MatchTable[CurrentIdx++];
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@ -34,6 +34,10 @@ class GINodeEquiv<Instruction i, SDNode node> {
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// depending on the predicates on the node.
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Instruction IfSignExtend = ?;
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Instruction IfZeroExtend = ?;
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// SelectionDAG has one setcc for all compares. This differentiates
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// for G_ICMP and G_FCMP.
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Instruction IfFloatingPoint = ?;
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}
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// These are defined in the same order as the G_* instructions.
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@ -122,6 +126,11 @@ def : GINodeEquiv<G_LOAD, ld> {
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let IfSignExtend = G_SEXTLOAD;
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let IfZeroExtend = G_ZEXTLOAD;
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}
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def : GINodeEquiv<G_ICMP, setcc> {
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let IfFloatingPoint = G_FCMP;
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}
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// Broadly speaking G_STORE is equivalent to ISD::STORE but there are some
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// complications that tablegen must take care of. For example, predicates such
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// as isTruncStore require that this is not a perfect 1:1 mapping since a
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@ -643,16 +643,32 @@ def assertzext : SDNode<"ISD::AssertZext", SDT_assertext>;
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//===----------------------------------------------------------------------===//
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// Selection DAG Condition Codes
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class CondCode; // ISD::CondCode enums
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def SETOEQ : CondCode; def SETOGT : CondCode;
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def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
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def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
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def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
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def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
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def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
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def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
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class CondCode<string fcmpName = "", string icmpName = ""> {
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string ICmpPredicate = icmpName;
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string FCmpPredicate = fcmpName;
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}
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// ISD::CondCode enums, and mapping to CmpInst::Predicate names
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def SETOEQ : CondCode<"FCMP_OEQ">;
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def SETOGT : CondCode<"FCMP_OGT">;
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def SETOGE : CondCode<"FCMP_OGE">;
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def SETOLT : CondCode<"FCMP_OLT">;
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def SETOLE : CondCode<"FCMP_OLE">;
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def SETONE : CondCode<"FCMP_ONE">;
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def SETO : CondCode<"FCMP_ORD">;
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def SETUO : CondCode<"FCMP_UNO">;
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def SETUEQ : CondCode<"FCMP_UEQ">;
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def SETUGT : CondCode<"FCMP_UGT", "ICMP_UGT">;
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def SETUGE : CondCode<"FCMP_UGE", "ICMP_UGE">;
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def SETULT : CondCode<"FCMP_ULT", "ICMP_ULT">;
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def SETULE : CondCode<"FCMP_ULE", "ICMP_ULE">;
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def SETUNE : CondCode<"FCMP_UNE">;
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def SETEQ : CondCode<"", "ICMP_EQ">;
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def SETGT : CondCode<"", "ICMP_SGT">;
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def SETGE : CondCode<"", "ICMP_SGE">;
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def SETLT : CondCode<"", "ICMP_SLT">;
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def SETLE : CondCode<"", "ICMP_SLE">;
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def SETNE : CondCode<"", "ICMP_NE">;
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//===----------------------------------------------------------------------===//
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// Selection DAG Node Transformation Functions.
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@ -163,11 +163,10 @@ unsigned AMDGPURegisterBankInfo::getBreakDownCost(
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const RegisterBank &AMDGPURegisterBankInfo::getRegBankFromRegClass(
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const TargetRegisterClass &RC) const {
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if (&RC == &AMDGPU::SReg_1RegClass)
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return AMDGPU::VCCRegBank;
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if (TRI->isSGPRClass(&RC))
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return getRegBank(AMDGPU::SGPRRegBankID);
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return getRegBank(AMDGPU::VGPRRegBankID);
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return TRI->isSGPRClass(&RC) ? AMDGPU::SGPRRegBank : AMDGPU::VGPRRegBank;
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}
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template <unsigned NumOps>
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@ -17,4 +17,4 @@ def VGPRRegBank : RegisterBank<"VGPR",
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def SCCRegBank : RegisterBank <"SCC", [SReg_32, SCC_CLASS]>;
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// It is helpful to distinguish conditions from ordinary SGPRs.
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def VCCRegBank : RegisterBank <"VCC", [SReg_64]>;
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def VCCRegBank : RegisterBank <"VCC", [SReg_1]>;
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799
test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
Normal file
799
test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.mir
Normal file
@ -0,0 +1,799 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
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# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE32 %s
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---
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name: fcmp_false_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: fcmp_false_s32_vv
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; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
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; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
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; WAVE32-LABEL: name: fcmp_false_s32_vv
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; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
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; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s32), [[COPY1]]
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; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_FCMP floatpred(false), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fcmp_oeq_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: fcmp_oeq_s32_vv
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
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; WAVE32-LABEL: name: fcmp_oeq_s32_vv
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_EQ_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fcmp_ogt_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: fcmp_ogt_s32_vv
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]
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; WAVE32-LABEL: name: fcmp_ogt_s32_vv
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_GT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fcmp_oge_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: fcmp_oge_s32_vv
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]
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; WAVE32-LABEL: name: fcmp_oge_s32_vv
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_GE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fcmp_olt_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: fcmp_olt_s32_vv
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]
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; WAVE32-LABEL: name: fcmp_olt_s32_vv
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_LT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fcmp_ole_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: fcmp_ole_s32_vv
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]
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; WAVE32-LABEL: name: fcmp_ole_s32_vv
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_LE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fcmp_one_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: fcmp_one_s32_vv
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]
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; WAVE32-LABEL: name: fcmp_one_s32_vv
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_LG_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vcc(s1) = G_FCMP floatpred(one), %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: fcmp_ord_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; WAVE64-LABEL: name: fcmp_ord_s32_vv
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; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE64: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]
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; WAVE32-LABEL: name: fcmp_ord_s32_vv
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; WAVE32: $vcc_hi = IMPLICIT_DEF
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; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; WAVE32: [[V_CMP_O_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_O_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
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; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F32_e64_]]
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||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_uno_s32_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_uno_s32_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_uno_s32_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_U_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_U_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ueq_s32_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ueq_s32_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ueq_s32_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NLG_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLG_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ugt_s32_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ugt_s32_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ugt_s32_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NLE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_uge_s32_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_uge_s32_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_uge_s32_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NLT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ult_s32_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ult_s32_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ult_s32_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NGE_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGE_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ule_s32_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ule_s32_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ule_s32_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NGT_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGT_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_une_s32_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_une_s32_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_une_s32_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NEQ_F32_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NEQ_F32_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F32_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_true_s32_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_true_s32_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s32), [[COPY1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
; WAVE32-LABEL: name: fcmp_true_s32_vv
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s32), [[COPY1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vcc(s1) = G_FCMP floatpred(true), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_false_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_false_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s64), [[COPY1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
; WAVE32-LABEL: name: fcmp_false_s64_vv
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[COPY]](s64), [[COPY1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(false), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_oeq_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_oeq_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_oeq_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_EQ_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(oeq), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ogt_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_ogt_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ogt_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_GT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(ogt), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_oge_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_oge_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_oge_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_GE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(oge), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_olt_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_olt_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_olt_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_LT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(olt), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ole_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_ole_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ole_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_LE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(ole), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_one_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_one_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_one_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_LG_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(one), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ord_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_ord_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ord_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_O_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_O_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_O_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(ord), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_uno_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_uno_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_uno_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_U_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_U_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(uno), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ueq_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_ueq_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ueq_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_NLG_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLG_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(ueq), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ugt_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_ugt_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ugt_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_NLE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(ugt), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_uge_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_uge_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_uge_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_NLT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(uge), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ult_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_ult_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ult_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_NGE_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGE_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(ult), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ule_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_ule_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ule_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_NGT_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGT_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(ule), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_une_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_une_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_une_s64_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[V_CMP_NEQ_F64_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NEQ_F64_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F64_e64_]]
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(une), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_true_s64_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
|
||||
; WAVE64-LABEL: name: fcmp_true_s64_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s64), [[COPY1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
; WAVE32-LABEL: name: fcmp_true_s64_vv
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[COPY]](s64), [[COPY1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
%0:vgpr(s64) = COPY $vgpr0_vgpr1
|
||||
%1:vgpr(s64) = COPY $vgpr2_vgpr3
|
||||
%2:vcc(s1) = G_FCMP floatpred(true), %0, %1
|
||||
S_ENDPGM 0, implicit %2
|
||||
...
|
||||
441
test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
Normal file
441
test/CodeGen/AMDGPU/GlobalISel/inst-select-fcmp.s16.mir
Normal file
@ -0,0 +1,441 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE64 %s
|
||||
# RUN: llc -march=amdgcn -mcpu=gfx1010 -run-pass=instruction-select -verify-machineinstrs -global-isel-abort=0 -o - %s | FileCheck -check-prefix=WAVE32 %s
|
||||
|
||||
---
|
||||
name: fcmp_false_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_false_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[TRUNC]](s16), [[TRUNC1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
; WAVE32-LABEL: name: fcmp_false_s16_vv
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(false), [[TRUNC]](s16), [[TRUNC1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(false), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_oeq_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_oeq_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_oeq_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_EQ_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_EQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_EQ_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(oeq), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ogt_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ogt_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ogt_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_GT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GT_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(ogt), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_oge_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_oge_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_oge_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_GE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_GE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_GE_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(oge), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_olt_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_olt_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_olt_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_LT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LT_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(olt), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ole_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ole_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ole_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_LE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LE_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(ole), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
---
|
||||
name: fcmp_one_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_one_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_one_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ord_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ord_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ord_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_LG_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_LG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_LG_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(one), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_uno_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_uno_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_uno_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_U_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_U_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_U_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(uno), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ueq_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ueq_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ueq_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NLG_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLG_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLG_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(ueq), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ugt_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ugt_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ugt_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NLE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLE_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(ugt), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_uge_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_uge_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_uge_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NLT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NLT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NLT_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(uge), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ult_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ult_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ult_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NGE_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGE_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGE_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(ult), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_ule_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_ule_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_ule_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NGT_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NGT_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NGT_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(ule), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_une_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_une_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE64: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_64 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE64: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]
|
||||
; WAVE32-LABEL: name: fcmp_une_s16_vv
|
||||
; WAVE32: $vcc_hi = IMPLICIT_DEF
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
|
||||
; WAVE32: [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_32_xm0 = V_CMP_NEQ_F16_e64 0, [[COPY]], 0, [[COPY1]], 0, implicit $exec
|
||||
; WAVE32: S_ENDPGM 0, implicit [[V_CMP_NEQ_F16_e64_]]
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(une), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
---
|
||||
name: fcmp_true_s16_vv
|
||||
legalized: true
|
||||
regBankSelected: true
|
||||
|
||||
body: |
|
||||
bb.0:
|
||||
liveins: $vgpr0, $vgpr1
|
||||
; WAVE64-LABEL: name: fcmp_true_s16_vv
|
||||
; WAVE64: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; WAVE64: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; WAVE64: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE64: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE64: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[TRUNC]](s16), [[TRUNC1]]
|
||||
; WAVE64: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
; WAVE32-LABEL: name: fcmp_true_s16_vv
|
||||
; WAVE32: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
|
||||
; WAVE32: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1
|
||||
; WAVE32: [[TRUNC:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY]](s32)
|
||||
; WAVE32: [[TRUNC1:%[0-9]+]]:vgpr(s16) = G_TRUNC [[COPY1]](s32)
|
||||
; WAVE32: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(true), [[TRUNC]](s16), [[TRUNC1]]
|
||||
; WAVE32: S_ENDPGM 0, implicit [[FCMP]](s1)
|
||||
%0:vgpr(s32) = COPY $vgpr0
|
||||
%1:vgpr(s32) = COPY $vgpr1
|
||||
%2:vgpr(s16) = G_TRUNC %0
|
||||
%3:vgpr(s16) = G_TRUNC %1
|
||||
%4:vcc(s1) = G_FCMP floatpred(true), %2, %3
|
||||
S_ENDPGM 0, implicit %4
|
||||
...
|
||||
|
||||
@ -49,11 +49,9 @@ body: |
|
||||
; MIPS32: [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY]], [[COPY1]], implicit-def dead $hi0, implicit-def dead $lo0
|
||||
; MIPS32: [[PseudoMULTu:%[0-9]+]]:acc64 = PseudoMULTu [[COPY]], [[COPY1]]
|
||||
; MIPS32: [[PseudoMFHI:%[0-9]+]]:gpr32 = PseudoMFHI [[PseudoMULTu]]
|
||||
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 0
|
||||
; MIPS32: [[XOR:%[0-9]+]]:gpr32 = XOR [[PseudoMFHI]], [[ORi]]
|
||||
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[XOR]]
|
||||
; MIPS32: [[ORi1:%[0-9]+]]:gpr32 = ORi $zero, 1
|
||||
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi1]]
|
||||
; MIPS32: [[SLTu:%[0-9]+]]:gpr32 = SLTu $zero, [[PseudoMFHI]]
|
||||
; MIPS32: [[ORi:%[0-9]+]]:gpr32 = ORi $zero, 1
|
||||
; MIPS32: [[AND:%[0-9]+]]:gpr32 = AND [[SLTu]], [[ORi]]
|
||||
; MIPS32: SB [[AND]], [[COPY3]], 0 :: (store 1 into %ir.pcarry_flag)
|
||||
; MIPS32: SW [[MUL]], [[COPY2]], 0 :: (store 4 into %ir.pmul)
|
||||
; MIPS32: RetRA
|
||||
|
||||
@ -290,8 +290,7 @@ define i64 @shl_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-NEXT: subu $3, $1, $6
|
||||
; MIPS32-NEXT: ori $8, $zero, 0
|
||||
; MIPS32-NEXT: sltu $1, $6, $1
|
||||
; MIPS32-NEXT: xor $9, $6, $8
|
||||
; MIPS32-NEXT: sltiu $9, $9, 1
|
||||
; MIPS32-NEXT: sltiu $9, $6, 1
|
||||
; MIPS32-NEXT: sllv $10, $4, $6
|
||||
; MIPS32-NEXT: srlv $3, $4, $3
|
||||
; MIPS32-NEXT: sllv $6, $5, $6
|
||||
@ -321,10 +320,8 @@ define i64 @ashl_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-NEXT: ori $1, $zero, 32
|
||||
; MIPS32-NEXT: subu $2, $6, $1
|
||||
; MIPS32-NEXT: subu $3, $1, $6
|
||||
; MIPS32-NEXT: ori $8, $zero, 0
|
||||
; MIPS32-NEXT: sltu $1, $6, $1
|
||||
; MIPS32-NEXT: xor $8, $6, $8
|
||||
; MIPS32-NEXT: sltiu $8, $8, 1
|
||||
; MIPS32-NEXT: sltiu $8, $6, 1
|
||||
; MIPS32-NEXT: srav $9, $5, $6
|
||||
; MIPS32-NEXT: srlv $6, $4, $6
|
||||
; MIPS32-NEXT: sllv $3, $5, $3
|
||||
@ -354,8 +351,7 @@ define i64 @lshr_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-NEXT: subu $3, $1, $6
|
||||
; MIPS32-NEXT: ori $8, $zero, 0
|
||||
; MIPS32-NEXT: sltu $1, $6, $1
|
||||
; MIPS32-NEXT: xor $9, $6, $8
|
||||
; MIPS32-NEXT: sltiu $9, $9, 1
|
||||
; MIPS32-NEXT: sltiu $9, $6, 1
|
||||
; MIPS32-NEXT: srlv $10, $5, $6
|
||||
; MIPS32-NEXT: srlv $6, $4, $6
|
||||
; MIPS32-NEXT: sllv $3, $5, $3
|
||||
|
||||
@ -164,8 +164,6 @@ define i1 @eq_i64(i64 %a, i64 %b){
|
||||
; MIPS32-NEXT: xor $1, $4, $6
|
||||
; MIPS32-NEXT: xor $2, $5, $7
|
||||
; MIPS32-NEXT: or $1, $1, $2
|
||||
; MIPS32-NEXT: ori $2, $zero, 0
|
||||
; MIPS32-NEXT: xor $1, $1, $2
|
||||
; MIPS32-NEXT: sltiu $2, $1, 1
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
@ -180,8 +178,6 @@ define i1 @ne_i64(i64 %a, i64 %b) {
|
||||
; MIPS32-NEXT: xor $1, $4, $6
|
||||
; MIPS32-NEXT: xor $2, $5, $7
|
||||
; MIPS32-NEXT: or $1, $1, $2
|
||||
; MIPS32-NEXT: ori $2, $zero, 0
|
||||
; MIPS32-NEXT: xor $1, $1, $2
|
||||
; MIPS32-NEXT: sltu $2, $zero, $1
|
||||
; MIPS32-NEXT: jr $ra
|
||||
; MIPS32-NEXT: nop
|
||||
|
||||
@ -186,8 +186,6 @@ define void @umul_with_overflow(i32 %lhs, i32 %rhs, i32* %pmul, i1* %pcarry_flag
|
||||
; MIPS32-NEXT: mul $1, $4, $5
|
||||
; MIPS32-NEXT: multu $4, $5
|
||||
; MIPS32-NEXT: mfhi $2
|
||||
; MIPS32-NEXT: ori $3, $zero, 0
|
||||
; MIPS32-NEXT: xor $2, $2, $3
|
||||
; MIPS32-NEXT: sltu $2, $zero, $2
|
||||
; MIPS32-NEXT: ori $3, $zero, 1
|
||||
; MIPS32-NEXT: and $2, $2, $3
|
||||
|
||||
@ -7,6 +7,7 @@ def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
|
||||
def GPR32Op : RegisterOperand<GPR32>;
|
||||
def F0 : Register<"f0"> { let Namespace = "MyTarget"; }
|
||||
def FPR32 : RegisterClass<"MyTarget", [f32], 32, (add F0)>;
|
||||
def FPR32Op : RegisterOperand<FPR32>;
|
||||
def p0 : PtrValueType <i32, 0>;
|
||||
|
||||
class I<dag OOps, dag IOps, list<dag> Pat>
|
||||
|
||||
24
test/TableGen/GlobalISelEmitter-setcc.td
Normal file
24
test/TableGen/GlobalISelEmitter-setcc.td
Normal file
@ -0,0 +1,24 @@
|
||||
// RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - 2> %t < %s | FileCheck -check-prefix=GISEL %s
|
||||
// RUN: FileCheck -DFILE=%s -check-prefix=ERR %s < %t
|
||||
|
||||
include "llvm/Target/Target.td"
|
||||
include "GlobalISelEmitterCommon.td"
|
||||
|
||||
// GISEL: GIM_Try
|
||||
// GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
|
||||
// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_FCMP,
|
||||
// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::FCMP_OEQ,
|
||||
def FCMPOEQ : I<(outs GPR32:$dst), (ins FPR32Op:$src0, FPR32:$src1),
|
||||
[(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, SETOEQ)))]>;
|
||||
|
||||
// GISEL: GIM_Try
|
||||
// GISEL: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4,
|
||||
// GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_ICMP,
|
||||
// GISEL: GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/CmpInst::ICMP_EQ,
|
||||
def ICMPEQ : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32:$src1),
|
||||
[(set GPR32:$dst, (i32 (setcc i32:$src0, i32:$src1, SETEQ)))]>;
|
||||
|
||||
// Check there is an error if not a CondCode operand.
|
||||
// ERR: [[FILE]]:[[@LINE+1]]:1: warning: Skipped pattern: Unable to handle CondCode
|
||||
def FCMP_NOTCC : I<(outs GPR32:$dst), (ins FPR32Op:$src0, FPR32:$src1),
|
||||
[(set GPR32:$dst, (i32 (setcc f32:$src0, f32:$src1, i32)))]>;
|
||||
@ -1064,6 +1064,7 @@ public:
|
||||
OPM_SameOperand,
|
||||
OPM_ComplexPattern,
|
||||
OPM_IntrinsicID,
|
||||
OPM_CmpPredicate,
|
||||
OPM_Instruction,
|
||||
OPM_Int,
|
||||
OPM_LiteralInt,
|
||||
@ -1389,6 +1390,36 @@ public:
|
||||
}
|
||||
};
|
||||
|
||||
/// Generates code to check that an operand is an CmpInst predicate
|
||||
class CmpPredicateOperandMatcher : public OperandPredicateMatcher {
|
||||
protected:
|
||||
std::string PredName;
|
||||
|
||||
public:
|
||||
CmpPredicateOperandMatcher(unsigned InsnVarID, unsigned OpIdx,
|
||||
std::string P)
|
||||
: OperandPredicateMatcher(OPM_CmpPredicate, InsnVarID, OpIdx), PredName(P) {}
|
||||
|
||||
bool isIdentical(const PredicateMatcher &B) const override {
|
||||
return OperandPredicateMatcher::isIdentical(B) &&
|
||||
PredName == cast<CmpPredicateOperandMatcher>(&B)->PredName;
|
||||
}
|
||||
|
||||
static bool classof(const PredicateMatcher *P) {
|
||||
return P->getKind() == OPM_CmpPredicate;
|
||||
}
|
||||
|
||||
void emitPredicateOpcodes(MatchTable &Table,
|
||||
RuleMatcher &Rule) const override {
|
||||
Table << MatchTable::Opcode("GIM_CheckCmpPredicate")
|
||||
<< MatchTable::Comment("MI") << MatchTable::IntValue(InsnVarID)
|
||||
<< MatchTable::Comment("Op") << MatchTable::IntValue(OpIdx)
|
||||
<< MatchTable::Comment("Predicate")
|
||||
<< MatchTable::NamedValue("CmpInst", PredName)
|
||||
<< MatchTable::LineBreak;
|
||||
}
|
||||
};
|
||||
|
||||
/// Generates code to check that an operand is an intrinsic ID.
|
||||
class IntrinsicIDOperandMatcher : public OperandPredicateMatcher {
|
||||
protected:
|
||||
@ -3256,6 +3287,13 @@ Record *GlobalISelEmitter::findNodeEquiv(Record *N) const {
|
||||
|
||||
const CodeGenInstruction *
|
||||
GlobalISelEmitter::getEquivNode(Record &Equiv, const TreePatternNode *N) const {
|
||||
if (N->getNumChildren() >= 1) {
|
||||
// setcc operation maps to two different G_* instructions based on the type.
|
||||
if (!Equiv.isValueUnset("IfFloatingPoint") &&
|
||||
MVT(N->getChild(0)->getSimpleType(0)).isFloatingPoint())
|
||||
return &Target.getInstruction(Equiv.getValueAsDef("IfFloatingPoint"));
|
||||
}
|
||||
|
||||
for (const TreePredicateCall &Call : N->getPredicateCalls()) {
|
||||
const TreePredicateFn &Predicate = Call.Fn;
|
||||
if (!Equiv.isValueUnset("IfSignExtend") && Predicate.isLoad() &&
|
||||
@ -3265,6 +3303,7 @@ GlobalISelEmitter::getEquivNode(Record &Equiv, const TreePatternNode *N) const {
|
||||
Predicate.isZeroExtLoad())
|
||||
return &Target.getInstruction(Equiv.getValueAsDef("IfZeroExtend"));
|
||||
}
|
||||
|
||||
return &Target.getInstruction(Equiv.getValueAsDef("I"));
|
||||
}
|
||||
|
||||
@ -3505,6 +3544,34 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
|
||||
return InsnMatcher;
|
||||
}
|
||||
|
||||
// Special case because the operand order is changed from setcc. The
|
||||
// predicate operand needs to be swapped from the last operand to the first
|
||||
// source.
|
||||
|
||||
unsigned NumChildren = Src->getNumChildren();
|
||||
bool IsFCmp = SrcGIOrNull->TheDef->getName() == "G_FCMP";
|
||||
|
||||
if (IsFCmp || SrcGIOrNull->TheDef->getName() == "G_ICMP") {
|
||||
TreePatternNode *SrcChild = Src->getChild(NumChildren - 1);
|
||||
if (SrcChild->isLeaf()) {
|
||||
DefInit *DI = dyn_cast<DefInit>(SrcChild->getLeafValue());
|
||||
Record *CCDef = DI ? DI->getDef() : nullptr;
|
||||
if (!CCDef || !CCDef->isSubClassOf("CondCode"))
|
||||
return failedImport("Unable to handle CondCode");
|
||||
|
||||
OperandMatcher &OM =
|
||||
InsnMatcher.addOperand(OpIdx++, SrcChild->getName(), TempOpIdx);
|
||||
StringRef PredType = IsFCmp ? CCDef->getValueAsString("FCmpPredicate") :
|
||||
CCDef->getValueAsString("ICmpPredicate");
|
||||
|
||||
if (!PredType.empty()) {
|
||||
OM.addPredicate<CmpPredicateOperandMatcher>(PredType);
|
||||
// Process the other 2 operands normally.
|
||||
--NumChildren;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Match the used operands (i.e. the children of the operator).
|
||||
bool IsIntrinsic =
|
||||
SrcGIOrNull->TheDef->getName() == "G_INTRINSIC" ||
|
||||
@ -3513,7 +3580,7 @@ Expected<InstructionMatcher &> GlobalISelEmitter::createAndImportSelDAGMatcher(
|
||||
if (IsIntrinsic && !II)
|
||||
return failedImport("Expected IntInit containing intrinsic ID)");
|
||||
|
||||
for (unsigned i = 0, e = Src->getNumChildren(); i != e; ++i) {
|
||||
for (unsigned i = 0; i != NumChildren; ++i) {
|
||||
TreePatternNode *SrcChild = Src->getChild(i);
|
||||
|
||||
// SelectionDAG allows pointers to be represented with iN since it doesn't
|
||||
|
||||
Loading…
Reference in New Issue
Block a user