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[AMDGPU] Assembler: rework parsing of optional operands.
Summary: Change process of parsing of optional operands. All optional operands use same parsing method - parseOptionalOperand(). No default values are added to OperandsVector. Get rid of WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS. Reviewers: tstellarAMD, vpykhtin, artem.tamazov, nhaustov Subscribers: arsenm, kzhuravl Differential Revision: http://reviews.llvm.org/D20527 llvm-svn: 270556
This commit is contained in:
Sam Kolton
parent
068739d10c
commit
5c1a0d6afe
@ -87,17 +87,6 @@ const char* const OpGsSymbolic[] = {
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using namespace llvm;
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// In some cases (e.g. buffer atomic instructions) MatchOperandParserImpl()
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// may invoke tryCustomParseOperand() multiple times with the same MCK value.
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// That leads to adding of the same "default" operand multiple times in a row,
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// which is wrong. The workaround adds only the 1st default operand, while for
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// the rest the "dummy" operands being added. The reason for dummies is that if
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// we just skip adding an operand, then parser would get stuck in endless loop.
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// Dummies shall be removed prior matching & emitting MCInsts.
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//
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// Comment out this macro to disable the workaround.
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#define WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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namespace {
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struct OptionalOperand;
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@ -110,9 +99,6 @@ class AMDGPUOperand : public MCParsedAsmOperand {
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Immediate,
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Register,
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Expression
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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,Dummy
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#endif
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} Kind;
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SMLoc StartLoc, EndLoc;
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@ -239,12 +225,6 @@ public:
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}
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}
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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bool isDummy() const {
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return Kind == Dummy;
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}
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#endif
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bool isToken() const override {
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return Kind == Token;
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}
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@ -481,11 +461,6 @@ public:
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case Expression:
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OS << "<expr " << *Expr << '>';
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break;
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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case Dummy:
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OS << "<dummy>";
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break;
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#endif
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}
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}
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@ -536,15 +511,6 @@ public:
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return Op;
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}
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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static AMDGPUOperand::Ptr CreateDummy(SMLoc S) {
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auto Op = llvm::make_unique<AMDGPUOperand>(Dummy);
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Op->StartLoc = S;
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Op->EndLoc = S;
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return Op;
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}
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#endif
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bool isSWaitCnt() const;
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bool isHwreg() const;
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bool isSendMsg() const;
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@ -642,6 +608,8 @@ public:
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std::unique_ptr<AMDGPUOperand> parseRegister();
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bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
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unsigned checkTargetMatchPredicate(MCInst &Inst) override;
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unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
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unsigned Kind) override;
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bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands, MCStreamer &Out,
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uint64_t &ErrorInfo,
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@ -651,29 +619,19 @@ public:
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bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
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SMLoc NameLoc, OperandVector &Operands) override;
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OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int,
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int64_t Default = 0, bool AddDefault = false);
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OperandMatchResultTy parseIntWithPrefix(const char *Prefix, int64_t &Int);
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OperandMatchResultTy parseIntWithPrefix(const char *Prefix,
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OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone,
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int64_t Default = 0, bool AddDefault = false,
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bool (*ConvertResult)(int64_t&) = 0);
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OperandMatchResultTy parseNamedBit(const char *Name, OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy =
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AMDGPUOperand::ImmTyNone,
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bool AddDefault = false);
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OperandMatchResultTy parseOptionalOps(
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const ArrayRef<OptionalOperand> &OptionalOps,
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OperandVector &Operands);
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enum AMDGPUOperand::ImmTy ImmTy = AMDGPUOperand::ImmTyNone);
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OperandMatchResultTy parseStringWithPrefix(const char *Prefix, StringRef &Value);
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OperandMatchResultTy parseImm(OperandVector &Operands);
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OperandMatchResultTy parseRegOrImm(OperandVector &Operands);
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OperandMatchResultTy parseRegOrImmWithInputMods(OperandVector &Operands);
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OperandMatchResultTy parseOptionalOperand(OperandVector &Operands, const OptionalOperand& Op, bool AddDefault);
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OperandMatchResultTy parseAMDGPUOperand(OperandVector &Operands, StringRef Name);
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void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
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void cvtDS(MCInst &Inst, const OperandVector &Operands);
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@ -681,14 +639,19 @@ public:
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OperandMatchResultTy parseSWaitCntOps(OperandVector &Operands);
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bool parseHwregOperand(int64_t &HwRegCode, int64_t &Offset, int64_t &Width, bool &IsIdentifier);
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OperandMatchResultTy parseHwreg(OperandVector &Operands);
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private:
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struct OperandInfoTy {
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int64_t Id;
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bool IsSymbolic;
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OperandInfoTy(int64_t Id_) : Id(Id_), IsSymbolic(false) { }
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};
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bool parseSendMsg(OperandInfoTy &Msg, OperandInfoTy &Operation, int64_t &StreamId);
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public:
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OperandMatchResultTy parseOptionalOperand(OperandVector &Operands);
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OperandMatchResultTy parseSendMsgOp(OperandVector &Operands);
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OperandMatchResultTy parseSOppBrTarget(OperandVector &Operands);
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AMDGPUOperand::Ptr defaultHwreg() const;
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@ -701,30 +664,6 @@ public:
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AMDGPUOperand::Ptr defaultSLC() const;
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AMDGPUOperand::Ptr defaultTFE() const;
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OperandMatchResultTy parseOModSI(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "omod"); }
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OperandMatchResultTy parseClampSI(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "clamp"); }
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OperandMatchResultTy parseSMRDOffset(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "smrd_offset"); }
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OperandMatchResultTy parseSMRDLiteralOffset(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "smrd_literal_offset"); }
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OperandMatchResultTy parseDPPCtrl(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "dpp_ctrl"); }
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OperandMatchResultTy parseRowMask(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "row_mask"); }
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OperandMatchResultTy parseBankMask(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "bank_mask"); }
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OperandMatchResultTy parseBoundCtrl(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "bound_ctrl"); }
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OperandMatchResultTy parseOffen(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "offen"); }
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OperandMatchResultTy parseIdxen(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "idxen"); }
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OperandMatchResultTy parseAddr64(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "addr64"); }
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OperandMatchResultTy parseOffset(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "offset"); }
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OperandMatchResultTy parseOffset0(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "offset0"); }
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OperandMatchResultTy parseOffset1(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "offset1"); }
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OperandMatchResultTy parseGLC(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "glc"); }
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OperandMatchResultTy parseSLC(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "slc"); }
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OperandMatchResultTy parseTFE(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "tfe"); }
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OperandMatchResultTy parseGDS(OperandVector &Operands) { return parseAMDGPUOperand(Operands, "gds"); }
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OperandMatchResultTy parseDMask(OperandVector &Operands);
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OperandMatchResultTy parseUNorm(OperandVector &Operands);
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OperandMatchResultTy parseDA(OperandVector &Operands);
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OperandMatchResultTy parseR128(OperandVector &Operands);
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OperandMatchResultTy parseLWE(OperandVector &Operands);
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AMDGPUOperand::Ptr defaultDMask() const;
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AMDGPUOperand::Ptr defaultUNorm() const;
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AMDGPUOperand::Ptr defaultDA() const;
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@ -745,7 +684,7 @@ public:
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void cvtMIMG(MCInst &Inst, const OperandVector &Operands);
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void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
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OperandMatchResultTy parseDPPCtrlOps(OperandVector &Operands, bool AddDefault);
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OperandMatchResultTy parseDPPCtrl(OperandVector &Operands);
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AMDGPUOperand::Ptr defaultRowMask() const;
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AMDGPUOperand::Ptr defaultBankMask() const;
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AMDGPUOperand::Ptr defaultBoundCtrl() const;
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@ -761,7 +700,6 @@ struct OptionalOperand {
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const char *Name;
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AMDGPUOperand::ImmTy Type;
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bool IsBit;
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int64_t Default;
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bool (*ConvertResult)(int64_t&);
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};
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@ -1104,7 +1042,6 @@ unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
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return Match_Success;
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}
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bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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OperandVector &Operands,
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MCStreamer &Out,
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@ -1112,17 +1049,6 @@ bool AMDGPUAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
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bool MatchingInlineAsm) {
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MCInst Inst;
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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// Remove dummies prior matching. Iterate backwards becase vector::erase()
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// invalidates all iterators which refer after erase point.
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for (auto I = Operands.rbegin(), E = Operands.rend(); I != E; ) {
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auto X = I++;
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if (static_cast<AMDGPUOperand*>(X->get())->isDummy()) {
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Operands.erase(X.base() -1);
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}
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}
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#endif
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switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
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default: break;
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case Match_Success:
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@ -1491,24 +1417,12 @@ bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
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//===----------------------------------------------------------------------===//
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int,
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int64_t Default, bool AddDefault) {
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// We are at the end of the statement, and this is a default argument, so
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// use a default value.
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if (getLexer().is(AsmToken::EndOfStatement)) {
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Int = Default;
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return MatchOperand_Success;
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}
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AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int) {
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switch(getLexer().getKind()) {
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default: return MatchOperand_NoMatch;
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case AsmToken::Identifier: {
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StringRef Name = Parser.getTok().getString();
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if (!Name.equals(Prefix)) {
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if (AddDefault) {
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Int = Default;
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return MatchOperand_Success;
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}
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return MatchOperand_NoMatch;
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}
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@ -1531,13 +1445,12 @@ AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, int64_t &Int,
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy,
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int64_t Default, bool AddDefault,
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bool (*ConvertResult)(int64_t&)) {
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SMLoc S = Parser.getTok().getLoc();
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int64_t Value = 0;
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AMDGPUAsmParser::OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Value, Default, AddDefault);
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AMDGPUAsmParser::OperandMatchResultTy Res = parseIntWithPrefix(Prefix, Value);
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if (Res != MatchOperand_Success)
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return Res;
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@ -1546,32 +1459,12 @@ AMDGPUAsmParser::parseIntWithPrefix(const char *Prefix, OperandVector &Operands,
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}
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Operands.push_back(AMDGPUOperand::CreateImm(Value, S, ImmTy));
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#ifdef WORKAROUND_USE_DUMMY_OPERANDS_INSTEAD_MUTIPLE_DEFAULT_OPERANDS
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if (Value == Default && AddDefault) {
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// Reverse lookup in previously added operands (skip just added one)
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// for the first non-dummy operand. If it is of the same type,
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// then replace just added default operand with dummy.
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for (auto I = Operands.rbegin(), E = Operands.rend(); I != E; ++I) {
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if (I == Operands.rbegin())
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continue;
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if (static_cast<AMDGPUOperand*>(I->get())->isDummy())
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continue;
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if (static_cast<AMDGPUOperand*>(I->get())->isImmTy(ImmTy)) {
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Operands.pop_back();
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Operands.push_back(AMDGPUOperand::CreateDummy(S)); // invalidates iterators
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break;
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}
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}
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}
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#endif
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return MatchOperand_Success;
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
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enum AMDGPUOperand::ImmTy ImmTy,
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bool AddDefault) {
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enum AMDGPUOperand::ImmTy ImmTy) {
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int64_t Bit = 0;
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SMLoc S = Parser.getTok().getLoc();
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@ -1588,11 +1481,7 @@ AMDGPUAsmParser::parseNamedBit(const char *Name, OperandVector &Operands,
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Bit = 0;
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Parser.Lex();
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} else {
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if (AddDefault) {
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Bit = 0;
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} else {
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return MatchOperand_NoMatch;
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}
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return MatchOperand_NoMatch;
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}
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break;
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}
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@ -1619,56 +1508,6 @@ void addOptionalImmOperand(MCInst& Inst, const OperandVector& Operands,
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}
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}
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static bool operandsHasOptionalOp(const OperandVector &Operands,
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const OptionalOperand &OOp) {
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for (unsigned i = 0; i < Operands.size(); i++) {
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const AMDGPUOperand &ParsedOp = ((const AMDGPUOperand &)*Operands[i]);
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if ((ParsedOp.isImm() && ParsedOp.getImmTy() == OOp.Type) ||
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(ParsedOp.isToken() && ParsedOp.getToken() == OOp.Name))
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return true;
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}
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return false;
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseOptionalOps(const ArrayRef<OptionalOperand> &OptionalOps,
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OperandVector &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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for (const OptionalOperand &Op : OptionalOps) {
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if (operandsHasOptionalOp(Operands, Op))
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continue;
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AMDGPUAsmParser::OperandMatchResultTy Res;
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int64_t Value;
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if (Op.IsBit) {
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Res = parseNamedBit(Op.Name, Operands, Op.Type);
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if (Res == MatchOperand_NoMatch)
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continue;
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return Res;
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}
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Res = parseIntWithPrefix(Op.Name, Value, Op.Default);
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if (Res == MatchOperand_NoMatch)
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continue;
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if (Res != MatchOperand_Success)
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return Res;
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bool DefaultValue = (Value == Op.Default);
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if (Op.ConvertResult && !Op.ConvertResult(Value)) {
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return MatchOperand_ParseFail;
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}
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if (!DefaultValue) {
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Operands.push_back(AMDGPUOperand::CreateImm(Value, S, Op.Type));
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}
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return MatchOperand_Success;
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}
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return MatchOperand_NoMatch;
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseStringWithPrefix(const char *Prefix, StringRef &Value) {
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if (getLexer().isNot(AsmToken::Identifier)) {
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@ -1896,7 +1735,7 @@ AMDGPUAsmParser::parseHwreg(OperandVector &Operands) {
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SMLoc S = Parser.getTok().getLoc();
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switch(getLexer().getKind()) {
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default: return MatchOperand_ParseFail;
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default: return MatchOperand_NoMatch;
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case AsmToken::Integer:
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// The operand can be an integer value.
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if (getParser().parseAbsoluteExpression(Imm16Val))
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@ -2154,10 +1993,6 @@ AMDGPUAsmParser::parseSOppBrTarget(OperandVector &Operands) {
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}
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}
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//===----------------------------------------------------------------------===//
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// flat
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// mubuf
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//===----------------------------------------------------------------------===//
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@ -2232,31 +2067,6 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
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// mimg
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//===----------------------------------------------------------------------===//
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseDMask(OperandVector &Operands) {
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return parseIntWithPrefix("dmask", Operands, AMDGPUOperand::ImmTyDMask);
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseUNorm(OperandVector &Operands) {
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return parseNamedBit("unorm", Operands, AMDGPUOperand::ImmTyUNorm);
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseDA(OperandVector &Operands) {
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return parseNamedBit("da", Operands, AMDGPUOperand::ImmTyDA);
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseR128(OperandVector &Operands) {
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return parseNamedBit("r128", Operands, AMDGPUOperand::ImmTyR128);
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}
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AMDGPUAsmParser::OperandMatchResultTy
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AMDGPUAsmParser::parseLWE(OperandVector &Operands) {
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return parseNamedBit("lwe", Operands, AMDGPUOperand::ImmTyLWE);
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}
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void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) {
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unsigned I = 1;
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const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
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@ -2409,74 +2219,48 @@ static bool ConvertBoundCtrl(int64_t &BoundCtrl) {
|
||||
}
|
||||
|
||||
// Note: the order in this table matches the order of operands in AsmString.
|
||||
static const OptionalOperand AMDGPUOperandTable[] = {
|
||||
{"offen", AMDGPUOperand::ImmTyOffen, true, 0, nullptr},
|
||||
{"offset0", AMDGPUOperand::ImmTyOffset0, false, 0, nullptr},
|
||||
{"offset1", AMDGPUOperand::ImmTyOffset1, false, 0, nullptr},
|
||||
{"gds", AMDGPUOperand::ImmTyGDS, true, 0, nullptr},
|
||||
{"offset", AMDGPUOperand::ImmTyOffset, false, 0, nullptr},
|
||||
{"glc", AMDGPUOperand::ImmTyGLC, true, 0, nullptr},
|
||||
{"slc", AMDGPUOperand::ImmTySLC, true, 0, nullptr},
|
||||
{"tfe", AMDGPUOperand::ImmTyTFE, true, 0, nullptr},
|
||||
{"clamp", AMDGPUOperand::ImmTyClampSI, true, 0, nullptr},
|
||||
{"omod", AMDGPUOperand::ImmTyOModSI, false, 1, ConvertOmodMul},
|
||||
{"unorm", AMDGPUOperand::ImmTyUNorm, true, 0, nullptr},
|
||||
{"da", AMDGPUOperand::ImmTyDA, true, 0, nullptr},
|
||||
{"r128", AMDGPUOperand::ImmTyR128, true, 0, nullptr},
|
||||
{"lwe", AMDGPUOperand::ImmTyLWE, true, 0, nullptr},
|
||||
{"dmask", AMDGPUOperand::ImmTyDMask, false, 0, nullptr},
|
||||
{"dpp_ctrl", AMDGPUOperand::ImmTyDppCtrl, false, -1, nullptr},
|
||||
{"row_mask", AMDGPUOperand::ImmTyDppRowMask, false, 0xf, nullptr},
|
||||
{"bank_mask", AMDGPUOperand::ImmTyDppBankMask, false, 0xf, nullptr},
|
||||
{"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, -1, ConvertBoundCtrl},
|
||||
static const OptionalOperand AMDGPUOptionalOperandTable[] = {
|
||||
{"offen", AMDGPUOperand::ImmTyOffen, true, nullptr},
|
||||
{"idxen", AMDGPUOperand::ImmTyIdxen, true, nullptr},
|
||||
{"addr64", AMDGPUOperand::ImmTyAddr64, true, nullptr},
|
||||
{"offset0", AMDGPUOperand::ImmTyOffset0, false, nullptr},
|
||||
{"offset1", AMDGPUOperand::ImmTyOffset1, false, nullptr},
|
||||
{"gds", AMDGPUOperand::ImmTyGDS, true, nullptr},
|
||||
{"offset", AMDGPUOperand::ImmTyOffset, false, nullptr},
|
||||
{"glc", AMDGPUOperand::ImmTyGLC, true, nullptr},
|
||||
{"slc", AMDGPUOperand::ImmTySLC, true, nullptr},
|
||||
{"tfe", AMDGPUOperand::ImmTyTFE, true, nullptr},
|
||||
{"clamp", AMDGPUOperand::ImmTyClampSI, true, nullptr},
|
||||
{"omod", AMDGPUOperand::ImmTyOModSI, false, ConvertOmodMul},
|
||||
{"unorm", AMDGPUOperand::ImmTyUNorm, true, nullptr},
|
||||
{"da", AMDGPUOperand::ImmTyDA, true, nullptr},
|
||||
{"r128", AMDGPUOperand::ImmTyR128, true, nullptr},
|
||||
{"lwe", AMDGPUOperand::ImmTyLWE, true, nullptr},
|
||||
{"dmask", AMDGPUOperand::ImmTyDMask, false, nullptr},
|
||||
{"row_mask", AMDGPUOperand::ImmTyDppRowMask, false, nullptr},
|
||||
{"bank_mask", AMDGPUOperand::ImmTyDppBankMask, false, nullptr},
|
||||
{"bound_ctrl", AMDGPUOperand::ImmTyDppBoundCtrl, false, ConvertBoundCtrl},
|
||||
{"sdwa_sel", AMDGPUOperand::ImmTySdwaSel, false, nullptr},
|
||||
{"dst_unused", AMDGPUOperand::ImmTySdwaDstUnused, false, nullptr},
|
||||
};
|
||||
|
||||
AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands, const OptionalOperand& Op, bool AddDefault)
|
||||
{
|
||||
if (Op.IsBit) {
|
||||
return parseNamedBit(Op.Name, Operands, Op.Type, AddDefault);
|
||||
} else if (Op.Type == AMDGPUOperand::ImmTyDppCtrl) {
|
||||
return parseDPPCtrlOps(Operands, AddDefault);
|
||||
} else if (Op.Type == AMDGPUOperand::ImmTyOModSI) {
|
||||
return parseOModOperand(Operands);
|
||||
} else {
|
||||
return parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.Default, AddDefault, Op.ConvertResult);
|
||||
}
|
||||
}
|
||||
|
||||
AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseAMDGPUOperand(OperandVector &Operands, StringRef Name)
|
||||
{
|
||||
StringRef Tok;
|
||||
if (getLexer().is(AsmToken::Identifier)) {
|
||||
Tok = Parser.getTok().getString();
|
||||
}
|
||||
bool optional = false;
|
||||
if (Tok == "mul" || Tok == "div") { optional = true; }
|
||||
for (const OptionalOperand &Op1 : AMDGPUOperandTable) {
|
||||
if (Op1.Name == Tok) { optional = true; break; }
|
||||
}
|
||||
// Attemp to parse current optional operand.
|
||||
for (const OptionalOperand &Op : AMDGPUOperandTable) {
|
||||
// TODO: For now, omod is handled separately because
|
||||
// token name does not match name in table.
|
||||
bool parseThis =
|
||||
Name == "" ||
|
||||
(Op.Name == Name) ||
|
||||
(Name == "omod" && Op.Type == AMDGPUOperand::ImmTyOModSI);
|
||||
if (parseThis && Tok == Name) {
|
||||
// Exactly the expected token for optional operand.
|
||||
// Parse it and add operand normally.
|
||||
return parseOptionalOperand(Operands, Op, true);
|
||||
} else if (parseThis) {
|
||||
// Token for optional operand which is later in the table
|
||||
// than the one we expect. If needed, add default value
|
||||
// for the operand we expect, do not consume anything
|
||||
// and return MatchOperand_NoMatch. Parsing will continue.
|
||||
return parseOptionalOperand(Operands, Op, optional);
|
||||
} else if (Op.Name == Tok) {
|
||||
// This looks like optional operand, but we do not expect it.
|
||||
// This is the case when AsmString has token in it.
|
||||
return MatchOperand_NoMatch;
|
||||
AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOptionalOperand(OperandVector &Operands) {
|
||||
OperandMatchResultTy res;
|
||||
for (const OptionalOperand &Op : AMDGPUOptionalOperandTable) {
|
||||
// try to parse any optional operand here
|
||||
if (Op.IsBit) {
|
||||
res = parseNamedBit(Op.Name, Operands, Op.Type);
|
||||
} else if (Op.Type == AMDGPUOperand::ImmTyOModSI) {
|
||||
res = parseOModOperand(Operands);
|
||||
} else if (Op.Type == AMDGPUOperand::ImmTySdwaSel) {
|
||||
res = parseSDWASel(Operands);
|
||||
} else if (Op.Type == AMDGPUOperand::ImmTySdwaDstUnused) {
|
||||
res = parseSDWADstUnused(Operands);
|
||||
} else {
|
||||
res = parseIntWithPrefix(Op.Name, Operands, Op.Type, Op.ConvertResult);
|
||||
}
|
||||
if (res != MatchOperand_NoMatch) {
|
||||
return res;
|
||||
}
|
||||
}
|
||||
return MatchOperand_NoMatch;
|
||||
@ -2486,9 +2270,9 @@ AMDGPUAsmParser::OperandMatchResultTy AMDGPUAsmParser::parseOModOperand(OperandV
|
||||
{
|
||||
StringRef Name = Parser.getTok().getString();
|
||||
if (Name == "mul") {
|
||||
return parseIntWithPrefix("mul", Operands, AMDGPUOperand::ImmTyOModSI, 0, false, ConvertOmodMul);
|
||||
return parseIntWithPrefix("mul", Operands, AMDGPUOperand::ImmTyOModSI, ConvertOmodMul);
|
||||
} else if (Name == "div") {
|
||||
return parseIntWithPrefix("div", Operands, AMDGPUOperand::ImmTyOModSI, 0, false, ConvertOmodDiv);
|
||||
return parseIntWithPrefix("div", Operands, AMDGPUOperand::ImmTyOModSI, ConvertOmodDiv);
|
||||
} else {
|
||||
return MatchOperand_NoMatch;
|
||||
}
|
||||
@ -2569,7 +2353,7 @@ bool AMDGPUOperand::isDPPCtrl() const {
|
||||
}
|
||||
|
||||
AMDGPUAsmParser::OperandMatchResultTy
|
||||
AMDGPUAsmParser::parseDPPCtrlOps(OperandVector &Operands, bool AddDefault) {
|
||||
AMDGPUAsmParser::parseDPPCtrl(OperandVector &Operands) {
|
||||
SMLoc S = Parser.getTok().getLoc();
|
||||
StringRef Prefix;
|
||||
int64_t Int;
|
||||
@ -2595,12 +2379,7 @@ AMDGPUAsmParser::parseDPPCtrlOps(OperandVector &Operands, bool AddDefault) {
|
||||
&& Prefix != "wave_shr"
|
||||
&& Prefix != "wave_ror"
|
||||
&& Prefix != "row_bcast") {
|
||||
if (AddDefault) {
|
||||
Operands.push_back(AMDGPUOperand::CreateImm(0, S, AMDGPUOperand::ImmTyDppCtrl));
|
||||
return MatchOperand_Success;
|
||||
} else {
|
||||
return MatchOperand_NoMatch;
|
||||
}
|
||||
return MatchOperand_NoMatch;
|
||||
}
|
||||
|
||||
Parser.Lex();
|
||||
@ -2820,3 +2599,28 @@ extern "C" void LLVMInitializeAMDGPUAsmParser() {
|
||||
#define GET_REGISTER_MATCHER
|
||||
#define GET_MATCHER_IMPLEMENTATION
|
||||
#include "AMDGPUGenAsmMatcher.inc"
|
||||
|
||||
|
||||
// This fuction should be defined after auto-generated include so that we have
|
||||
// MatchClassKind enum defined
|
||||
unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
|
||||
unsigned Kind) {
|
||||
// Tokens like "glc" would be parsed as immediate operands in ParseOperand().
|
||||
// But MatchInstructionImpl() expects to meet token and fails to validate
|
||||
// operand. This method checks if we are given immediate operand but expect to
|
||||
// get corresponding token.
|
||||
AMDGPUOperand &Operand = (AMDGPUOperand&)Op;
|
||||
switch (Kind) {
|
||||
case MCK_addr64:
|
||||
return Operand.isAddr64() ? Match_Success : Match_InvalidOperand;
|
||||
case MCK_gds:
|
||||
return Operand.isGDS() ? Match_Success : Match_InvalidOperand;
|
||||
case MCK_glc:
|
||||
return Operand.isGLC() ? Match_Success : Match_InvalidOperand;
|
||||
case MCK_idxen:
|
||||
return Operand.isIdxen() ? Match_Success : Match_InvalidOperand;
|
||||
case MCK_offen:
|
||||
return Operand.isOffen() ? Match_Success : Match_InvalidOperand;
|
||||
default: return Match_InvalidOperand;
|
||||
}
|
||||
}
|
||||
|
||||
@ -486,7 +486,7 @@ include "VIInstrFormats.td"
|
||||
class NamedMatchClass<string CName, bit Optional = 1> : AsmOperandClass {
|
||||
let Name = "Imm"#CName;
|
||||
let PredicateMethod = "is"#CName;
|
||||
let ParserMethod = "parse"#CName;
|
||||
let ParserMethod = !if(Optional, "parseOptionalOperand", "parse"#CName);
|
||||
let RenderMethod = "addImmOperands";
|
||||
let IsOptional = Optional;
|
||||
let DefaultMethod = "default"#CName;
|
||||
@ -552,7 +552,7 @@ def src0_sel : NamedOperandU32<"SDWASrc0Sel", sdwa_sel>;
|
||||
def src1_sel : NamedOperandU32<"SDWASrc1Sel", sdwa_sel>;
|
||||
def dst_unused : NamedOperandU32<"SDWADstUnused", NamedMatchClass<"SDWADstUnused">>;
|
||||
|
||||
def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg">>;
|
||||
def hwreg : NamedOperandU16<"Hwreg", NamedMatchClass<"Hwreg", 0>>;
|
||||
|
||||
} // End OperandType = "OPERAND_IMMEDIATE"
|
||||
|
||||
|
||||
@ -6,11 +6,11 @@
|
||||
ds_add_u32 v2, v4 offset:1000000000
|
||||
|
||||
// offset0 twice
|
||||
// CHECK: error: not a valid operand.
|
||||
// CHECK: error: invalid operand for instruction
|
||||
ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
|
||||
|
||||
// offset1 twice
|
||||
// CHECK: error: not a valid operand.
|
||||
// CHECK: error: invalid operand for instruction
|
||||
ds_write2_b32 v2, v4, v6 offset1:4 offset1:8
|
||||
|
||||
// offset0 too big
|
||||
|
||||
Loading…
Reference in New Issue
Block a user