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misched: Release bottom roots in reverse order.
llvm-svn: 157426
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0e174b3a0e
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@ -396,6 +396,8 @@ protected:
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void moveInstruction(MachineInstr *MI, MachineBasicBlock::iterator InsertPos);
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bool checkSchedLimit();
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void releaseRoots();
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void releaseSucc(SUnit *SU, SDep *SuccEdge);
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void releaseSuccessors(SUnit *SU);
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void releasePred(SUnit *SU, SDep *PredEdge);
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@ -554,6 +556,26 @@ updateScheduledPressure(std::vector<unsigned> NewMaxPressure) {
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}
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}
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// Release all DAG roots for scheduling.
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void ScheduleDAGMI::releaseRoots() {
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SmallVector<SUnit*, 16> BotRoots;
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for (std::vector<SUnit>::iterator
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I = SUnits.begin(), E = SUnits.end(); I != E; ++I) {
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// A SUnit is ready to top schedule if it has no predecessors.
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if (I->Preds.empty())
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SchedImpl->releaseTopNode(&(*I));
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// A SUnit is ready to bottom schedule if it has no successors.
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if (I->Succs.empty())
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BotRoots.push_back(&(*I));
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}
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// Release bottom roots in reverse order so the higher priority nodes appear
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// first. This is more natural and slightly more efficient.
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for (SmallVectorImpl<SUnit*>::const_reverse_iterator
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I = BotRoots.rbegin(), E = BotRoots.rend(); I != E; ++I)
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SchedImpl->releaseBottomNode(*I);
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}
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/// schedule - Called back from MachineScheduler::runOnMachineFunction
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/// after setting up the current scheduling region. [RegionBegin, RegionEnd)
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/// only includes instructions that have DAG nodes, not scheduling boundaries.
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@ -584,15 +606,7 @@ void ScheduleDAGMI::schedule() {
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releasePredecessors(&ExitSU);
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// Release all DAG roots for scheduling.
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for (std::vector<SUnit>::iterator I = SUnits.begin(), E = SUnits.end();
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I != E; ++I) {
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// A SUnit is ready to top schedule if it has no predecessors.
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if (I->Preds.empty())
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SchedImpl->releaseTopNode(&(*I));
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// A SUnit is ready to bottom schedule if it has no successors.
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if (I->Succs.empty())
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SchedImpl->releaseBottomNode(&(*I));
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}
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releaseRoots();
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CurrentTop = nextIfDebug(RegionBegin, RegionEnd);
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CurrentBottom = RegionEnd;
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