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AMDGPU: Don't count mask branch pseudo towards skip threshold

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llvm-svn: 362761
This commit is contained in:
Matt Arsenault 2019-06-07 00:14:55 +00:00
parent 9adbf6ad64
commit 5ccc752a9c
2 changed files with 62 additions and 10 deletions
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18
lib/Target/AMDGPU/SIInsertSkips.cpp
View File

@ -92,15 +92,13 @@ INITIALIZE_PASS(SIInsertSkips, DEBUG_TYPE,
char &llvm::SIInsertSkipsPassID = SIInsertSkips::ID;
static bool opcodeEmitsNoInsts(unsigned Opc) {
switch (Opc) {
case TargetOpcode::IMPLICIT_DEF:
case TargetOpcode::KILL:
case TargetOpcode::BUNDLE:
case TargetOpcode::CFI_INSTRUCTION:
case TargetOpcode::EH_LABEL:
case TargetOpcode::GC_LABEL:
case TargetOpcode::DBG_VALUE:
static bool opcodeEmitsNoInsts(const MachineInstr &MI) {
if (MI.isMetaInstruction())
return true;
// Handle target specific opcodes.
switch (MI.getOpcode()) {
case AMDGPU::SI_MASK_BRANCH:
return true;
default:
return false;
@ -118,7 +116,7 @@ bool SIInsertSkips::shouldSkip(const MachineBasicBlock &From,
for (MachineBasicBlock::const_iterator I = MBB.begin(), E = MBB.end();
NumInstr < SkipThreshold && I != E; ++I) {
if (opcodeEmitsNoInsts(I->getOpcode()))
if (opcodeEmitsNoInsts(*I))
continue;
// FIXME: Since this is required for correctness, this should be inserted

54
test/CodeGen/AMDGPU/insert-skips-ignored-insts.mir Normal file
View File

@ -0,0 +1,54 @@
# RUN: llc -mtriple=amdgcn-amd-amdhsa -run-pass si-insert-skips -amdgpu-skip-threshold=2 %s -o - | FileCheck %s
---
# CHECK-LABEL: name: no_count_mask_branch_pseudo
# CHECK: $vgpr1 = V_MOV_B32_e32 7, implicit $exec
# CHECK-NEXT: SI_MASK_BRANCH
# CHECK-NOT: S_CBRANCH_EXECZ
name: no_count_mask_branch_pseudo
body: |
bb.0:
successors: %bb.1
$vgpr1 = V_MOV_B32_e32 7, implicit $exec
SI_MASK_BRANCH %bb.2, implicit $exec
bb.1:
successors: %bb.2
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
SI_MASK_BRANCH %bb.3, implicit $exec
bb.2:
$vgpr0 = V_MOV_B32_e32 1, implicit $exec
bb.3:
S_ENDPGM 0
...
---
# CHECK-LABEL: name: no_count_dbg_value
# CHECK: $vgpr1 = V_MOV_B32_e32 7, implicit $exec
# CHECK-NEXT: SI_MASK_BRANCH
# CHECK-NOT: S_CBRANCH_EXECZ
name: no_count_dbg_value
body: |
bb.0:
successors: %bb.1
$vgpr1 = V_MOV_B32_e32 7, implicit $exec
SI_MASK_BRANCH %bb.2, implicit $exec
bb.1:
successors: %bb.2
$vgpr0 = V_MOV_B32_e32 0, implicit $exec
DBG_VALUE
bb.2:
$vgpr0 = V_MOV_B32_e32 1, implicit $exec
bb.3:
S_ENDPGM 0
...