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Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead.
llvm-svn: 163878
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064f380b12
commit
5cd6b912e7
@ -581,12 +581,13 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName,
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StringTable.add(AsmName);
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StringTable.add(AsmName);
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}
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}
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StringTable.layout();
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unsigned Entries = StringTable.layout();
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O << " static const char AsmStrs" << AltName << "[] = {\n";
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O << " static const char AsmStrs" << AltName << "[] = {\n";
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StringTable.emit(O, printChar);
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StringTable.emit(O, printChar);
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O << " };\n\n";
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O << " };\n\n";
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O << " static const unsigned RegAsmOffset" << AltName << "[] = {";
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O << " static const uint" << ((Entries > 0xffff) ? "32" : "16")
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<< "_t RegAsmOffset" << AltName << "[] = {";
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
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if ((i % 14) == 0)
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if ((i % 14) == 0)
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O << "\n ";
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O << "\n ";
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@ -84,7 +84,7 @@ public:
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bool empty() const { return Seqs.empty(); }
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bool empty() const { return Seqs.empty(); }
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/// layout - Computes the final table layout.
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/// layout - Computes the final table layout.
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void layout() {
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unsigned layout() {
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assert(Entries == 0 && "Can only call layout() once");
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assert(Entries == 0 && "Can only call layout() once");
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// Lay out the table in Seqs iteration order.
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// Lay out the table in Seqs iteration order.
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for (typename SeqMap::iterator I = Seqs.begin(), E = Seqs.end(); I != E;
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for (typename SeqMap::iterator I = Seqs.begin(), E = Seqs.end(); I != E;
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@ -93,6 +93,7 @@ public:
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// Include space for a terminator.
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// Include space for a terminator.
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Entries += I->first.size() + 1;
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Entries += I->first.size() + 1;
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}
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}
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return Entries;
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}
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}
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/// get - Returns the offset of Seq in the final table.
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/// get - Returns the offset of Seq in the final table.
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