mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 19:23:23 +01:00
Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead.
llvm-svn: 163878
This commit is contained in:
parent
064f380b12
commit
5cd6b912e7
@ -581,12 +581,13 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName,
|
||||
StringTable.add(AsmName);
|
||||
}
|
||||
|
||||
StringTable.layout();
|
||||
unsigned Entries = StringTable.layout();
|
||||
O << " static const char AsmStrs" << AltName << "[] = {\n";
|
||||
StringTable.emit(O, printChar);
|
||||
O << " };\n\n";
|
||||
|
||||
O << " static const unsigned RegAsmOffset" << AltName << "[] = {";
|
||||
O << " static const uint" << ((Entries > 0xffff) ? "32" : "16")
|
||||
<< "_t RegAsmOffset" << AltName << "[] = {";
|
||||
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
|
||||
if ((i % 14) == 0)
|
||||
O << "\n ";
|
||||
|
@ -84,7 +84,7 @@ public:
|
||||
bool empty() const { return Seqs.empty(); }
|
||||
|
||||
/// layout - Computes the final table layout.
|
||||
void layout() {
|
||||
unsigned layout() {
|
||||
assert(Entries == 0 && "Can only call layout() once");
|
||||
// Lay out the table in Seqs iteration order.
|
||||
for (typename SeqMap::iterator I = Seqs.begin(), E = Seqs.end(); I != E;
|
||||
@ -93,6 +93,7 @@ public:
|
||||
// Include space for a terminator.
|
||||
Entries += I->first.size() + 1;
|
||||
}
|
||||
return Entries;
|
||||
}
|
||||
|
||||
/// get - Returns the offset of Seq in the final table.
|
||||
|
Loading…
Reference in New Issue
Block a user