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[Hexagon] Check for .cur def without use without using a map data structure
Patch by Colin LeMahieu. llvm-svn: 301943
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@ -159,12 +159,6 @@ void HexagonMCChecker::init(MCInst const &MCI) {
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isPredicateRegister(*SRI))
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// Some insns produce predicates too late to be used in the same packet.
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LatePreds.insert(*SRI);
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else if (i == 0 && HexagonMCInstrInfo::isCVINew(MCII, MCI) &&
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MCID.mayLoad())
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// Current loads should be used in the same packet.
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// TODO: relies on the impossibility of a current and a temporary loads
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// in the same packet.
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CurDefs.insert(*SRI), Defs[*SRI].insert(PredSense(PredReg, isTrue));
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else if (i == 0 && llvm::HexagonMCInstrInfo::getType(MCII, MCI) ==
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HexagonII::TypeCVI_VM_TMP_LD)
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// Temporary loads should be used in the same packet, but don't commit
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@ -252,6 +246,7 @@ bool HexagonMCChecker::check(bool FullCheck) {
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bool chkNV = checkNewValues();
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bool chkR = checkRegisters();
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bool chkRRO = checkRegistersReadOnly();
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checkRegisterCurDefs();
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bool chkS = checkSolo();
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bool chkSh = true;
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if (FullCheck)
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@ -396,6 +391,43 @@ bool HexagonMCChecker::checkRegistersReadOnly() {
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return true;
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}
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bool HexagonMCChecker::registerUsed(MCInst const &Inst, unsigned Register) {
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if (HexagonMCInstrInfo::isDuplex(MCII, Inst)) {
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if (registerUsed(*Inst.getOperand(0).getInst(), Register) ||
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registerUsed(*Inst.getOperand(1).getInst(), Register))
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return true;
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} else {
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unsigned Defs = HexagonMCInstrInfo::getDesc(MCII, Inst).getNumDefs();
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for (unsigned j = Defs, n = Inst.getNumOperands(); j < n; ++j) {
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MCOperand const &Operand = Inst.getOperand(j);
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if (Operand.isReg() && Operand.getReg() == Register)
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return true;
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}
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}
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return false;
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}
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bool HexagonMCChecker::registerUsed(unsigned Register) {
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auto Range = HexagonMCInstrInfo::bundleInstructions(MCB);
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return std::any_of(Range.begin(), Range.end(), [&](MCOperand const &Operand) {
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return registerUsed(*Operand.getInst(), Register);
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});
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}
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void HexagonMCChecker::checkRegisterCurDefs() {
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for (auto const &I : HexagonMCInstrInfo::bundleInstructions(MCB)) {
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MCInst const &Inst = *I.getInst();
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if (HexagonMCInstrInfo::isCVINew(MCII, Inst) &&
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HexagonMCInstrInfo::getDesc(MCII, Inst).mayLoad()) {
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unsigned Register = Inst.getOperand(0).getReg();
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if (!registerUsed(Register))
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reportWarning("Register `" + llvm::Twine(RI.getName(Register)) +
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"' used with `.cur' "
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"but not used in the same packet");
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}
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}
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}
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// Check for legal register uses and definitions.
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bool HexagonMCChecker::checkRegisters() {
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// Check for proper register definitions.
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@ -456,19 +488,6 @@ bool HexagonMCChecker::checkRegisters() {
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}
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}
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// Check for use of current definitions.
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for (const auto &I : CurDefs) {
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unsigned R = I;
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if (!Uses.count(R)) {
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// Warn on an unused current definition.
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reportWarning("register `" + llvm::Twine(RI.getName(R)) +
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"' used with `.cur' "
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"but not used in the same packet");
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return true;
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}
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}
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// Check for use of temporary definitions.
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for (const auto &I : TmpDefs) {
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unsigned R = I;
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@ -78,10 +78,6 @@ class HexagonMCChecker {
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typedef std::set<unsigned>::iterator SoftDefsIterator;
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std::set<unsigned> SoftDefs;
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/// Set of current definitions committed to the register file.
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typedef std::set<unsigned>::iterator CurDefsIterator;
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std::set<unsigned> CurDefs;
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/// Set of temporary definitions not committed to the register file.
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typedef std::set<unsigned>::iterator TmpDefsIterator;
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std::set<unsigned> TmpDefs;
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@ -109,13 +105,16 @@ class HexagonMCChecker {
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void init();
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void init(MCInst const &);
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void initReg(MCInst const &, unsigned, unsigned &PredReg, bool &isTrue);
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bool registerUsed(unsigned Register);
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bool registerUsed(MCInst const &Inst, unsigned Register);
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// Checks performed.
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bool checkBranches();
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bool checkPredicates();
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bool checkNewValues();
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bool checkRegisters();
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bool checkRegistersReadOnly();
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void checkRegisterCurDefs();
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bool checkSolo();
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bool checkShuffle();
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bool checkSlots();
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