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[mips] Add missing schedinfo for LONG_BRANCH_* instructions

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llvm-svn: 364848
This commit is contained in:
Simon Atanasyan 2019-07-01 21:24:51 +00:00
parent 3300711f28
commit 5d1338df67
2 changed files with 27 additions and 11 deletions
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22
lib/Target/Mips/Mips64InstrInfo.td
View File

@ -417,17 +417,25 @@ let isCodeGenOnly = 1, rs = 0, shamt = 0 in {
// explanation.
// Expands to: lui $dst, %highest/%higher/%hi/%lo($tgt)
def LONG_BRANCH_LUi2Op_64 : PseudoSE<(outs GPR64Opnd:$dst),
(ins brtarget:$tgt), []>, GPR_64;
def LONG_BRANCH_LUi2Op_64 :
PseudoSE<(outs GPR64Opnd:$dst), (ins brtarget:$tgt), []>, GPR_64 {
bit hasNoSchedulingInfo = 1;
}
// Expands to: addiu $dst, %highest/%higher/%hi/%lo($tgt)
def LONG_BRANCH_DADDiu2Op : PseudoSE<(outs GPR64Opnd:$dst),
(ins GPR64Opnd:$src, brtarget:$tgt), []>, GPR_64;
def LONG_BRANCH_DADDiu2Op :
PseudoSE<(outs GPR64Opnd:$dst), (ins GPR64Opnd:$src, brtarget:$tgt), []>,
GPR_64 {
bit hasNoSchedulingInfo = 1;
}
// Expands to: daddiu $dst, $src, %PART($tgt - $baltgt)
// where %PART may be %hi or %lo, depending on the relocation kind
// that $tgt is annotated with.
def LONG_BRANCH_DADDiu : PseudoSE<(outs GPR64Opnd:$dst),
(ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>, GPR_64;
def LONG_BRANCH_DADDiu :
PseudoSE<(outs GPR64Opnd:$dst),
(ins GPR64Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>,
GPR_64 {
bit hasNoSchedulingInfo = 1;
}
// Cavium Octeon cnMIPS instructions
let DecoderNamespace = "CnMips",

16
lib/Target/Mips/MipsInstrInfo.td
View File

@ -2014,17 +2014,25 @@ let isPseudo = 1, isCodeGenOnly = 1, hasNoSchedulingInfo = 1 in {
// Expands to: lui $dst, %highest/%higher/%hi/%lo($tgt - $baltgt)
def LONG_BRANCH_LUi : PseudoSE<(outs GPR32Opnd:$dst),
(ins brtarget:$tgt, brtarget:$baltgt), []>;
(ins brtarget:$tgt, brtarget:$baltgt), []> {
bit hasNoSchedulingInfo = 1;
}
// Expands to: lui $dst, highest/%higher/%hi/%lo($tgt)
def LONG_BRANCH_LUi2Op : PseudoSE<(outs GPR32Opnd:$dst),
(ins brtarget:$tgt), []>;
(ins brtarget:$tgt), []> {
bit hasNoSchedulingInfo = 1;
}
// Expands to: addiu $dst, $src, %highest/%higher/%hi/%lo($tgt - $baltgt)
def LONG_BRANCH_ADDiu : PseudoSE<(outs GPR32Opnd:$dst),
(ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []>;
(ins GPR32Opnd:$src, brtarget:$tgt, brtarget:$baltgt), []> {
bit hasNoSchedulingInfo = 1;
}
// Expands to: addiu $dst, $src, %highest/%higher/%hi/%lo($tgt)
def LONG_BRANCH_ADDiu2Op : PseudoSE<(outs GPR32Opnd:$dst),
(ins GPR32Opnd:$src, brtarget:$tgt), []>;
(ins GPR32Opnd:$src, brtarget:$tgt), []> {
bit hasNoSchedulingInfo = 1;
}
//===----------------------------------------------------------------------===//
// Instruction definition