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Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print"
This reverts commit r324681. llvm-svn: 325505
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c73a5be0c2
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@ -387,7 +387,6 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
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if (!LI.LaneMask.all())
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OS << ":0x" << PrintLaneMask(LI.LaneMask);
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}
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OS << '\n';
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HasLineAttributes = true;
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}
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@ -1473,6 +1473,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
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if (isIndirectDebugValue())
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OS << " indirect";
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}
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OS << '\n';
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}
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bool MachineInstr::addRegisterKilled(unsigned IncomingReg,
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@ -549,13 +549,9 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
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}
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DEBUG(dbgs() << "********** MI Scheduling **********\n");
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DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB) << " "
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<< MBB->getName() << "\n From: " << *I << '\n'
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<< " To: ";
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if (RegionEnd != MBB->end()) {
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dbgs() << *RegionEnd << '\n';
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} else {
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dbgs() << "End";
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}
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<< MBB->getName() << "\n From: " << *I << " To: ";
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if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
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else dbgs() << "End";
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dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n');
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if (DumpCriticalPathLength) {
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errs() << MF->getName();
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@ -1137,7 +1133,7 @@ void ScheduleDAGMILive::updatePressureDiffs(
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DEBUG(
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dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "
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<< printReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)
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<< ' ' << *SU.getInstr() << '\n';
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<< ' ' << *SU.getInstr();
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dbgs() << " to ";
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PDiff.dump(*TRI);
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);
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@ -1174,7 +1170,7 @@ void ScheduleDAGMILive::updatePressureDiffs(
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PDiff.addPressureChange(Reg, true, &MRI);
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DEBUG(
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dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
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<< *SU->getInstr() << '\n';
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<< *SU->getInstr();
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dbgs() << " to ";
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PDiff.dump(*TRI);
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);
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@ -3338,8 +3334,7 @@ SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
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IsTopNode = true;
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Top.removeReady(SU);
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DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr()
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<< '\n');
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DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
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return SU;
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}
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@ -1099,7 +1099,6 @@ void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
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// Cannot completely remove virtual function even in release mode.
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#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
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SU->getInstr()->dump();
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dbgs() << '\n';
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#endif
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}
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@ -380,9 +380,8 @@ static bool handleMiddleInst(const MachineInstr &MI, LOHInfo &DefInfo,
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static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI,
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LOHInfo &Info) {
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if (Info.LastADRP != nullptr) {
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DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n"
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<< '\t' << MI << '\n'
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<< '\t' << *Info.LastADRP << '\n');
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DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n" << '\t' << MI << '\t'
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<< *Info.LastADRP);
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AFI.addLOHDirective(MCLOH_AdrpAdrp, {&MI, Info.LastADRP});
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++NumADRPSimpleCandidate;
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}
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@ -391,59 +390,48 @@ static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI,
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if (Info.IsCandidate) {
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switch (Info.Type) {
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case MCLOH_AdrpAdd:
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DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n"
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<< '\t' << MI << '\n'
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<< '\t' << *Info.MI0 << '\n');
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DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n" << '\t' << MI << '\t'
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<< *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpAdd, {&MI, Info.MI0});
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++NumADRSimpleCandidate;
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break;
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case MCLOH_AdrpLdr:
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if (supportLoadFromLiteral(*Info.MI0)) {
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DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n"
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<< '\t' << MI << '\n'
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<< '\t' << *Info.MI0 << '\n');
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DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n" << '\t' << MI << '\t'
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<< *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpLdr, {&MI, Info.MI0});
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++NumADRPToLDR;
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}
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break;
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case MCLOH_AdrpAddLdr:
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DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n"
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<< '\t' << MI << '\n'
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<< '\t' << *Info.MI1 << '\n'
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<< '\t' << *Info.MI0 << '\n');
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DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n" << '\t' << MI << '\t'
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<< *Info.MI1 << '\t' << *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpAddLdr, {&MI, Info.MI1, Info.MI0});
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++NumADDToLDR;
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break;
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case MCLOH_AdrpAddStr:
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if (Info.MI1 != nullptr) {
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DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n"
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<< '\t' << MI << '\n'
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<< '\t' << *Info.MI1 << '\n'
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<< '\t' << *Info.MI0 << '\n');
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DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n" << '\t' << MI << '\t'
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<< *Info.MI1 << '\t' << *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpAddStr, {&MI, Info.MI1, Info.MI0});
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++NumADDToSTR;
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}
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break;
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case MCLOH_AdrpLdrGotLdr:
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DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n"
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<< '\t' << MI << '\n'
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<< '\t' << *Info.MI1 << '\n'
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<< '\t' << *Info.MI0 << '\n');
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DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n" << '\t' << MI << '\t'
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<< *Info.MI1 << '\t' << *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpLdrGotLdr, {&MI, Info.MI1, Info.MI0});
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++NumLDRToLDR;
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break;
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case MCLOH_AdrpLdrGotStr:
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DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n"
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<< '\t' << MI << '\n'
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<< '\t' << *Info.MI1 << '\n'
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<< '\t' << *Info.MI0 << '\n');
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DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n" << '\t' << MI << '\t'
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<< *Info.MI1 << '\t' << *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpLdrGotStr, {&MI, Info.MI1, Info.MI0});
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++NumLDRToSTR;
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break;
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case MCLOH_AdrpLdrGot:
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DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n"
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<< '\t' << MI << '\n'
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<< '\t' << *Info.MI0 << '\n');
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DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n" << '\t' << MI << '\t'
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<< *Info.MI0);
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AFI.addLOHDirective(MCLOH_AdrpLdrGot, {&MI, Info.MI0});
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break;
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case MCLOH_AdrpAdrp:
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