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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 12:41:49 +01:00

Revert "[CodeGen] Move printing '\n' from MachineInstr::print to MachineBasicBlock::print"

This reverts commit r324681.

llvm-svn: 325505
This commit is contained in:
Francis Visoiu Mistrih 2018-02-19 15:08:49 +00:00
parent c73a5be0c2
commit 5d2e990b7d
5 changed files with 24 additions and 41 deletions

View File

@ -387,7 +387,6 @@ void MachineBasicBlock::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (!LI.LaneMask.all())
OS << ":0x" << PrintLaneMask(LI.LaneMask);
}
OS << '\n';
HasLineAttributes = true;
}

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@ -1473,6 +1473,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (isIndirectDebugValue())
OS << " indirect";
}
OS << '\n';
}
bool MachineInstr::addRegisterKilled(unsigned IncomingReg,

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@ -549,13 +549,9 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
}
DEBUG(dbgs() << "********** MI Scheduling **********\n");
DEBUG(dbgs() << MF->getName() << ":" << printMBBReference(*MBB) << " "
<< MBB->getName() << "\n From: " << *I << '\n'
<< " To: ";
if (RegionEnd != MBB->end()) {
dbgs() << *RegionEnd << '\n';
} else {
dbgs() << "End";
}
<< MBB->getName() << "\n From: " << *I << " To: ";
if (RegionEnd != MBB->end()) dbgs() << *RegionEnd;
else dbgs() << "End";
dbgs() << " RegionInstrs: " << NumRegionInstrs << '\n');
if (DumpCriticalPathLength) {
errs() << MF->getName();
@ -1137,7 +1133,7 @@ void ScheduleDAGMILive::updatePressureDiffs(
DEBUG(
dbgs() << " UpdateRegP: SU(" << SU.NodeNum << ") "
<< printReg(Reg, TRI) << ':' << PrintLaneMask(P.LaneMask)
<< ' ' << *SU.getInstr() << '\n';
<< ' ' << *SU.getInstr();
dbgs() << " to ";
PDiff.dump(*TRI);
);
@ -1174,7 +1170,7 @@ void ScheduleDAGMILive::updatePressureDiffs(
PDiff.addPressureChange(Reg, true, &MRI);
DEBUG(
dbgs() << " UpdateRegP: SU(" << SU->NodeNum << ") "
<< *SU->getInstr() << '\n';
<< *SU->getInstr();
dbgs() << " to ";
PDiff.dump(*TRI);
);
@ -3338,8 +3334,7 @@ SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
IsTopNode = true;
Top.removeReady(SU);
DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr()
<< '\n');
DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") " << *SU->getInstr());
return SU;
}

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@ -1099,7 +1099,6 @@ void ScheduleDAGInstrs::dumpNode(const SUnit *SU) const {
// Cannot completely remove virtual function even in release mode.
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
SU->getInstr()->dump();
dbgs() << '\n';
#endif
}

View File

@ -380,9 +380,8 @@ static bool handleMiddleInst(const MachineInstr &MI, LOHInfo &DefInfo,
static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI,
LOHInfo &Info) {
if (Info.LastADRP != nullptr) {
DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n"
<< '\t' << MI << '\n'
<< '\t' << *Info.LastADRP << '\n');
DEBUG(dbgs() << "Adding MCLOH_AdrpAdrp:\n" << '\t' << MI << '\t'
<< *Info.LastADRP);
AFI.addLOHDirective(MCLOH_AdrpAdrp, {&MI, Info.LastADRP});
++NumADRPSimpleCandidate;
}
@ -391,59 +390,48 @@ static void handleADRP(const MachineInstr &MI, AArch64FunctionInfo &AFI,
if (Info.IsCandidate) {
switch (Info.Type) {
case MCLOH_AdrpAdd:
DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n"
<< '\t' << MI << '\n'
<< '\t' << *Info.MI0 << '\n');
DEBUG(dbgs() << "Adding MCLOH_AdrpAdd:\n" << '\t' << MI << '\t'
<< *Info.MI0);
AFI.addLOHDirective(MCLOH_AdrpAdd, {&MI, Info.MI0});
++NumADRSimpleCandidate;
break;
case MCLOH_AdrpLdr:
if (supportLoadFromLiteral(*Info.MI0)) {
DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n"
<< '\t' << MI << '\n'
<< '\t' << *Info.MI0 << '\n');
DEBUG(dbgs() << "Adding MCLOH_AdrpLdr:\n" << '\t' << MI << '\t'
<< *Info.MI0);
AFI.addLOHDirective(MCLOH_AdrpLdr, {&MI, Info.MI0});
++NumADRPToLDR;
}
break;
case MCLOH_AdrpAddLdr:
DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n"
<< '\t' << MI << '\n'
<< '\t' << *Info.MI1 << '\n'
<< '\t' << *Info.MI0 << '\n');
DEBUG(dbgs() << "Adding MCLOH_AdrpAddLdr:\n" << '\t' << MI << '\t'
<< *Info.MI1 << '\t' << *Info.MI0);
AFI.addLOHDirective(MCLOH_AdrpAddLdr, {&MI, Info.MI1, Info.MI0});
++NumADDToLDR;
break;
case MCLOH_AdrpAddStr:
if (Info.MI1 != nullptr) {
DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n"
<< '\t' << MI << '\n'
<< '\t' << *Info.MI1 << '\n'
<< '\t' << *Info.MI0 << '\n');
DEBUG(dbgs() << "Adding MCLOH_AdrpAddStr:\n" << '\t' << MI << '\t'
<< *Info.MI1 << '\t' << *Info.MI0);
AFI.addLOHDirective(MCLOH_AdrpAddStr, {&MI, Info.MI1, Info.MI0});
++NumADDToSTR;
}
break;
case MCLOH_AdrpLdrGotLdr:
DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n"
<< '\t' << MI << '\n'
<< '\t' << *Info.MI1 << '\n'
<< '\t' << *Info.MI0 << '\n');
DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotLdr:\n" << '\t' << MI << '\t'
<< *Info.MI1 << '\t' << *Info.MI0);
AFI.addLOHDirective(MCLOH_AdrpLdrGotLdr, {&MI, Info.MI1, Info.MI0});
++NumLDRToLDR;
break;
case MCLOH_AdrpLdrGotStr:
DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n"
<< '\t' << MI << '\n'
<< '\t' << *Info.MI1 << '\n'
<< '\t' << *Info.MI0 << '\n');
DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGotStr:\n" << '\t' << MI << '\t'
<< *Info.MI1 << '\t' << *Info.MI0);
AFI.addLOHDirective(MCLOH_AdrpLdrGotStr, {&MI, Info.MI1, Info.MI0});
++NumLDRToSTR;
break;
case MCLOH_AdrpLdrGot:
DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n"
<< '\t' << MI << '\n'
<< '\t' << *Info.MI0 << '\n');
DEBUG(dbgs() << "Adding MCLOH_AdrpLdrGot:\n" << '\t' << MI << '\t'
<< *Info.MI0);
AFI.addLOHDirective(MCLOH_AdrpLdrGot, {&MI, Info.MI0});
break;
case MCLOH_AdrpAdrp: