mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 03:23:01 +02:00
The new LDR* instruction patterns should handle the necessary encoding of
operands in the TableGen'erated bits, so we don't need to do the additional magic explicitly. llvm-svn: 117461
This commit is contained in:
parent
32da0e6e3f
commit
5d4415c6b0
@ -946,6 +946,13 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
|
||||
// Part of binary is determined by TableGn.
|
||||
unsigned Binary = getBinaryCodeForInstr(MI);
|
||||
|
||||
// If this is an LDRi12, LDRrs, or LDRcp, nothing more needs be done.
|
||||
if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRrs
|
||||
|| MI.getOpcode() == ARM::LDRcp) {
|
||||
emitWordLE(Binary);
|
||||
return;
|
||||
}
|
||||
|
||||
// Set the conditional execution predicate
|
||||
Binary |= II->getPredicate(&MI) << ARMII::CondShift;
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user