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The new LDR* instruction patterns should handle the necessary encoding of

operands in the TableGen'erated bits, so we don't need to do the additional
magic explicitly.

llvm-svn: 117461
This commit is contained in:
Jim Grosbach 2010-10-27 17:52:51 +00:00
parent 32da0e6e3f
commit 5d4415c6b0

View File

@ -946,6 +946,13 @@ void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
// Part of binary is determined by TableGn.
unsigned Binary = getBinaryCodeForInstr(MI);
// If this is an LDRi12, LDRrs, or LDRcp, nothing more needs be done.
if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRrs
|| MI.getOpcode() == ARM::LDRcp) {
emitWordLE(Binary);
return;
}
// Set the conditional execution predicate
Binary |= II->getPredicate(&MI) << ARMII::CondShift;