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AMDGPU/SI: Use ComplexPatterns for SMRD addressing modes
Summary: This allows us to consolidate several of the TableGen patterns. Reviewers: arsenm Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11602 llvm-svn: 244253
This commit is contained in:
Tom Stellard
parent
36aa0fcc7f
commit
5d9e608825
@ -108,6 +108,14 @@ private:
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SDValue &TFE) const;
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bool SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc, SDValue &Soffset,
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SDValue &Offset, SDValue &GLC) const;
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bool SelectSMRDOffset(SDValue ByteOffsetNode, SDValue &Offset,
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bool &Imm) const;
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bool SelectSMRD(SDValue Addr, SDValue &SBase, SDValue &Offset,
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bool &Imm) const;
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bool SelectSMRDImm(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
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bool SelectSMRDSgpr(SDValue Addr, SDValue &SBase, SDValue &Offset) const;
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bool SelectSMRDBufferImm(SDValue Addr, SDValue &Offset) const;
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bool SelectSMRDBufferSgpr(SDValue Addr, SDValue &Offset) const;
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SDNode *SelectAddrSpaceCast(SDNode *N);
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bool SelectVOP3Mods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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bool SelectVOP3NoMods(SDValue In, SDValue &Src, SDValue &SrcMods) const;
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@ -1153,6 +1161,89 @@ bool AMDGPUDAGToDAGISel::SelectMUBUFOffset(SDValue Addr, SDValue &SRsrc,
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return SelectMUBUFOffset(Addr, SRsrc, Soffset, Offset, GLC, SLC, TFE);
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}
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///
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/// \param EncodedOffset This is the immediate value that will be encoded
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/// directly into the instruction. On SI/CI the \p EncodedOffset
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/// will be in units of dwords and on VI+ it will be units of bytes.
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static bool isLegalSMRDImmOffset(const AMDGPUSubtarget *ST,
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int64_t EncodedOffset) {
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return ST->getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
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isUInt<8>(EncodedOffset) : isUInt<20>(EncodedOffset);
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDOffset(SDValue ByteOffsetNode,
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SDValue &Offset, bool &Imm) const {
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// FIXME: Handle non-constant offsets.
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ConstantSDNode *C = dyn_cast<ConstantSDNode>(ByteOffsetNode);
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if (!C)
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return false;
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SDLoc SL(ByteOffsetNode);
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AMDGPUSubtarget::Generation Gen = Subtarget->getGeneration();
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int64_t ByteOffset = C->getSExtValue();
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int64_t EncodedOffset = Gen < AMDGPUSubtarget::VOLCANIC_ISLANDS ?
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ByteOffset >> 2 : ByteOffset;
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if (isLegalSMRDImmOffset(Subtarget, EncodedOffset)) {
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Offset = CurDAG->getTargetConstant(EncodedOffset, SL, MVT::i32);
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Imm = true;
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return true;
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}
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if (isUInt<32>(ByteOffset)) {
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SDValue C32Bit = CurDAG->getTargetConstant(ByteOffset, SL, MVT::i32);
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Offset = SDValue(CurDAG->getMachineNode(AMDGPU::S_MOV_B32, SL, MVT::i32,
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C32Bit), 0);
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Imm = false;
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return true;
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}
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return false;
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}
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bool AMDGPUDAGToDAGISel::SelectSMRD(SDValue Addr, SDValue &SBase,
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SDValue &Offset, bool &Imm) const {
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SDLoc SL(Addr);
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if (CurDAG->isBaseWithConstantOffset(Addr)) {
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SDValue N0 = Addr.getOperand(0);
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SDValue N1 = Addr.getOperand(1);
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if (SelectSMRDOffset(N1, Offset, Imm)) {
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SBase = N0;
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return true;
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}
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}
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SBase = Addr;
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Offset = CurDAG->getTargetConstant(0, SL, MVT::i32);
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Imm = true;
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return true;
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDImm(SDValue Addr, SDValue &SBase,
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SDValue &Offset) const {
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bool Imm;
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return SelectSMRD(Addr, SBase, Offset, Imm) && Imm;
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDSgpr(SDValue Addr, SDValue &SBase,
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SDValue &Offset) const {
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bool Imm;
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return SelectSMRD(Addr, SBase, Offset, Imm) && !Imm;
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDBufferImm(SDValue Addr,
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SDValue &Offset) const {
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bool Imm;
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return SelectSMRDOffset(Addr, Offset, Imm) && Imm;
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}
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bool AMDGPUDAGToDAGISel::SelectSMRDBufferSgpr(SDValue Addr,
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SDValue &Offset) const {
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bool Imm;
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return SelectSMRDOffset(Addr, Offset, Imm) && !Imm;
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}
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// FIXME: This is incorrect and only enough to be able to compile.
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SDNode *AMDGPUDAGToDAGISel::SelectAddrSpaceCast(SDNode *N) {
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AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(N);
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@ -222,6 +222,19 @@ class SMRDe <bits<5> op, bits<1> imm> : Enc32 {
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let Inst{31-27} = 0x18; //encoding
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}
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class SMRD_IMMe_ci <bits<5> op> : Enc64 {
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bits<7> sdst;
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bits<7> sbase;
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bits<32> offset;
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let Inst{7-0} = 0xff;
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let Inst{8} = 0;
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let Inst{14-9} = sbase{6-1};
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let Inst{21-15} = sdst;
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let Inst{26-22} = 0x18; //encoding
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let Inst{63-32} = offset;
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}
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let SchedRW = [WriteSALU] in {
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class SOP1 <dag outs, dag ins, string asm, list<dag> pattern> :
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InstSI<outs, ins, asm, pattern> {
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@ -528,6 +528,12 @@ def MUBUFScratch : ComplexPattern<i64, 4, "SelectMUBUFScratch">;
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def MUBUFOffset : ComplexPattern<i64, 6, "SelectMUBUFOffset">;
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def MUBUFOffsetAtomic : ComplexPattern<i64, 4, "SelectMUBUFOffset">;
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def SMRDImm : ComplexPattern<i64, 2, "SelectSMRDImm">;
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def SMRDSgpr : ComplexPattern<i64, 2, "SelectSMRDSgpr">;
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def SMRDBufferImm : ComplexPattern<i32, 1, "SelectSMRDBufferImm">;
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def SMRDBufferSgpr : ComplexPattern<i32, 1, "SelectSMRDBufferSgpr">;
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def VOP3Mods0 : ComplexPattern<untyped, 4, "SelectVOP3Mods0">;
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def VOP3NoMods0 : ComplexPattern<untyped, 4, "SelectVOP3NoMods0">;
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def VOP3Mods0Clamp : ComplexPattern<untyped, 3, "SelectVOP3Mods0Clamp">;
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@ -891,6 +897,12 @@ multiclass SMRD_Helper <bits<5> op, string opName, RegisterClass baseClass,
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opName#" $dst, $sbase, $offset", []
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>;
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def _IMM_ci : SMRD <
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(outs dstClass:$dst), (ins baseClass:$sbase, u32imm:$offset),
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opName#" $dst, $sbase, $offset", []>, SMRD_IMMe_ci <op> {
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let AssemblerPredicates = [isCI];
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}
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defm _SGPR : SMRD_m <
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op, opName#"_SGPR", 0, (outs dstClass:$dst),
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(ins baseClass:$sbase, SReg_32:$soff),
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@ -2074,79 +2074,36 @@ def : Pat <
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multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
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// 1. SI-CI: Offset as 8bit DWORD immediate
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// 1. IMM offset
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def : Pat <
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(constant_load (add i64:$sbase, (i64 IMM8bitDWORD:$offset))),
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(vt (Instr_IMM $sbase, (as_dword_i32imm $offset)))
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(constant_load (SMRDImm i64:$sbase, i32:$offset)),
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(vt (Instr_IMM $sbase, $offset))
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>;
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// 2. Offset loaded in an 32bit SGPR
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// 2. SGPR offset
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def : Pat <
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(constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
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(vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
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>;
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// 3. No offset at all
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def : Pat <
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(constant_load i64:$sbase),
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(vt (Instr_IMM $sbase, 0))
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(constant_load (SMRDSgpr i64:$sbase, i32:$offset)),
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(vt (Instr_SGPR $sbase, $offset))
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>;
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}
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multiclass SMRD_Pattern_vi <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
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// 1. VI: Offset as 20bit immediate in bytes
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def : Pat <
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(constant_load (add i64:$sbase, (i64 IMM20bit:$offset))),
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(vt (Instr_IMM $sbase, (as_i32imm $offset)))
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>;
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// 2. Offset loaded in an 32bit SGPR
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def : Pat <
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(constant_load (add i64:$sbase, (i64 IMM32bit:$offset))),
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(vt (Instr_SGPR $sbase, (S_MOV_B32 (i32 (as_i32imm $offset)))))
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>;
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// 3. No offset at all
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def : Pat <
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(constant_load i64:$sbase),
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(vt (Instr_IMM $sbase, 0))
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>;
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}
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let Predicates = [isSICI] in {
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defm : SMRD_Pattern <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
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defm : SMRD_Pattern <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
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defm : SMRD_Pattern <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
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} // End Predicates = [isSICI]
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let Predicates = [isVI] in {
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defm : SMRD_Pattern_vi <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, f32>;
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defm : SMRD_Pattern_vi <S_LOAD_DWORD_IMM, S_LOAD_DWORD_SGPR, i32>;
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defm : SMRD_Pattern_vi <S_LOAD_DWORDX2_IMM, S_LOAD_DWORDX2_SGPR, v2i32>;
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defm : SMRD_Pattern_vi <S_LOAD_DWORDX4_IMM, S_LOAD_DWORDX4_SGPR, v4i32>;
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defm : SMRD_Pattern_vi <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v32i8>;
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defm : SMRD_Pattern_vi <S_LOAD_DWORDX8_IMM, S_LOAD_DWORDX8_SGPR, v8i32>;
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defm : SMRD_Pattern_vi <S_LOAD_DWORDX16_IMM, S_LOAD_DWORDX16_SGPR, v16i32>;
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} // End Predicates = [isVI]
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let Predicates = [isSICI] in {
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// 1. Offset as 8bit DWORD immediate
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// 1. Offset as an immediate
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def : Pat <
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(SIload_constant v4i32:$sbase, IMM8bitDWORD:$offset),
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(S_BUFFER_LOAD_DWORD_IMM $sbase, (as_dword_i32imm $offset))
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(SIload_constant v4i32:$sbase, (SMRDBufferImm i32:$offset)),
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(S_BUFFER_LOAD_DWORD_IMM $sbase, $offset)
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>;
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} // End Predicates = [isSICI]
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// 2. Offset loaded in an 32bit SGPR
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def : Pat <
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(SIload_constant v4i32:$sbase, imm:$offset),
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(S_BUFFER_LOAD_DWORD_SGPR $sbase, (S_MOV_B32 imm:$offset))
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(SIload_constant v4i32:$sbase, (SMRDBufferSgpr i32:$offset)),
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(S_BUFFER_LOAD_DWORD_SGPR $sbase, $offset)
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>;
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//===----------------------------------------------------------------------===//
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@ -54,6 +54,33 @@ entry:
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ret void
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}
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; SMRD load with the largest possible immediate offset on VI
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; GCN-LABEL: {{^}}smrd4:
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; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
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define void @smrd4(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 262143
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%1 = load i32, i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate on VI
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; GCN-LABEL: {{^}}smrd5:
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; GCN: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; GCN: s_endpgm
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define void @smrd5(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {
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entry:
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%0 = getelementptr i32, i32 addrspace(2)* %ptr, i64 262144
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%1 = load i32, i32 addrspace(2)* %0
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store i32 %1, i32 addrspace(1)* %out
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ret void
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}
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; SMRD load using the load.const intrinsic with an immediate offset
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; GCN-LABEL: {{^}}smrd_load_const0:
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4 ; encoding: [0x04
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@ -96,6 +123,35 @@ main_body:
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ret void
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}
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; SMRD load with the largest possible immediate offset on VI
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; GCN-LABEL: {{^}}smrd_load_const3:
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; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
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define void @smrd_load_const3(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1048572)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate on VI
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; GCN-LABEL: {{^}}smrd_load_const4:
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; GCN: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; VI: s_buffer_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; GCN: s_endpgm
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define void @smrd_load_const4(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, float, float, float) #0 {
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main_body:
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%20 = getelementptr <16 x i8>, <16 x i8> addrspace(2)* %0, i32 0
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%21 = load <16 x i8>, <16 x i8> addrspace(2)* %20
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%22 = call float @llvm.SI.load.const(<16 x i8> %21, i32 1048576)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %22, float %22, float %22, float %22)
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ret void
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}
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.load.const(<16 x i8>, i32) #1
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