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AArch64: support the Apple NEON syntax for v8.2 crypto instructions.
Very simple change, just adding the extra syntax variant.
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@ -10407,9 +10407,9 @@ class CryptoRRTied<bits<1>op0, bits<2>op1, string asm, string asmops>
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let Inst{11-10} = op1;
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}
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class CryptoRRTied_2D<bits<1>op0, bits<2>op1, string asm>
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: CryptoRRTied<op0, op1, asm, "{\t$Vd.2d, $Vn.2d}">;
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: CryptoRRTied<op0, op1, asm, "{\t$Vd.2d, $Vn.2d|.2d\t$Vd, $Vn}">;
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class CryptoRRTied_4S<bits<1>op0, bits<2>op1, string asm>
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: CryptoRRTied<op0, op1, asm, "{\t$Vd.4s, $Vn.4s}">;
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: CryptoRRTied<op0, op1, asm, "{\t$Vd.4s, $Vn.4s|.4s\t$Vd, $Vn}">;
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class CryptoRRR<bits<1> op0, bits<2>op1, dag oops, dag iops, string asm,
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string asmops, string cst>
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@ -10424,19 +10424,19 @@ class CryptoRRR<bits<1> op0, bits<2>op1, dag oops, dag iops, string asm,
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}
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class CryptoRRR_2D<bits<1> op0, bits<2>op1, string asm>
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: CryptoRRR<op0, op1, (outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm,
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"{\t$Vd.2d, $Vn.2d, $Vm.2d}", "">;
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"{\t$Vd.2d, $Vn.2d, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "">;
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class CryptoRRRTied_2D<bits<1> op0, bits<2>op1, string asm>
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: CryptoRRR<op0, op1, (outs V128:$Vdst), (ins V128:$Vd, V128:$Vn, V128:$Vm), asm,
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"{\t$Vd.2d, $Vn.2d, $Vm.2d}", "$Vd = $Vdst">;
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"{\t$Vd.2d, $Vn.2d, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "$Vd = $Vdst">;
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class CryptoRRR_4S<bits<1> op0, bits<2>op1, string asm>
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: CryptoRRR<op0, op1, (outs V128:$Vd), (ins V128:$Vn, V128:$Vm), asm,
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"{\t$Vd.4s, $Vn.4s, $Vm.4s}", "">;
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"{\t$Vd.4s, $Vn.4s, $Vm.4s|.4s\t$Vd, $Vn, $Vm}", "">;
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class CryptoRRRTied_4S<bits<1> op0, bits<2>op1, string asm>
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: CryptoRRR<op0, op1, (outs V128:$Vdst), (ins V128:$Vd, V128:$Vn, V128:$Vm), asm,
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"{\t$Vd.4s, $Vn.4s, $Vm.4s}", "$Vd = $Vdst">;
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"{\t$Vd.4s, $Vn.4s, $Vm.4s|.4s\t$Vd, $Vn, $Vm}", "$Vd = $Vdst">;
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class CryptoRRRTied<bits<1> op0, bits<2>op1, string asm>
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: CryptoRRR<op0, op1, (outs FPR128:$Vdst), (ins FPR128:$Vd, FPR128:$Vn, V128:$Vm),
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asm, "{\t$Vd, $Vn, $Vm.2d}", "$Vd = $Vdst">;
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asm, "{\t$Vd, $Vn, $Vm.2d|.2d\t$Vd, $Vn, $Vm}", "$Vd = $Vdst">;
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class CryptoRRRR<bits<2>op0, string asm, string asmops>
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: BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm, V128:$Va), asm,
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@ -10450,15 +10450,18 @@ class CryptoRRRR<bits<2>op0, string asm, string asmops>
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let Inst{14-10} = Va;
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}
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class CryptoRRRR_16B<bits<2>op0, string asm>
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: CryptoRRRR<op0, asm, "{\t$Vd.16b, $Vn.16b, $Vm.16b, $Va.16b}"> {
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: CryptoRRRR<op0, asm, "{\t$Vd.16b, $Vn.16b, $Vm.16b, $Va.16b" #
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"|.16b\t$Vd, $Vn, $Vm, $Va}"> {
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}
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class CryptoRRRR_4S<bits<2>op0, string asm>
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: CryptoRRRR<op0, asm, "{\t$Vd.4s, $Vn.4s, $Vm.4s, $Va.4s}"> {
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: CryptoRRRR<op0, asm, "{\t$Vd.4s, $Vn.4s, $Vm.4s, $Va.4s" #
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"|.4s\t$Vd, $Vn, $Vm, $Va}"> {
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}
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class CryptoRRRi6<string asm>
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: BaseCryptoV82<(outs V128:$Vd), (ins V128:$Vn, V128:$Vm, uimm6:$imm), asm,
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"{\t$Vd.2d, $Vn.2d, $Vm.2d, $imm}", "", []> {
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"{\t$Vd.2d, $Vn.2d, $Vm.2d, $imm" #
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"|.2d\t$Vd, $Vn, $Vm, $imm}", "", []> {
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bits<6> imm;
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bits<5> Vm;
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let Inst{24-21} = 0b0100;
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@ -10471,7 +10474,8 @@ class CryptoRRRi6<string asm>
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class CryptoRRRi2Tied<bits<1>op0, bits<2>op1, string asm>
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: BaseCryptoV82<(outs V128:$Vdst),
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(ins V128:$Vd, V128:$Vn, V128:$Vm, VectorIndexS:$imm),
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asm, "{\t$Vd.4s, $Vn.4s, $Vm.s$imm}", "$Vd = $Vdst", []> {
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asm, "{\t$Vd.4s, $Vn.4s, $Vm.s$imm" #
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"|.4s\t$Vd, $Vn, $Vm$imm}", "$Vd = $Vdst", []> {
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bits<2> imm;
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bits<5> Vm;
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let Inst{24-21} = 0b0010;
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41
test/MC/AArch64/armv8.2a-crypto-apple.s
Normal file
41
test/MC/AArch64/armv8.2a-crypto-apple.s
Normal file
@ -0,0 +1,41 @@
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// RUN: llvm-mc -output-asm-variant=1 -triple aarch64-apple-ios -mattr=+sha3,+sm4 -show-encoding < %s | FileCheck %s
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sha512h.2d q0, q1, v2
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sha512h2.2d q0, q1, v2
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sha512su0.2d v11, v12
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sha512su1.2d v11, v13, v14
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eor3.16b v25, v12, v7, v2
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rax1.2d v30, v29, v26
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xar.2d v26, v21, v27, #63
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bcax.16b v31, v26, v2, v1
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//CHECK: sha512h.2d q0, q1, v2 ; encoding: [0x20,0x80,0x62,0xce]
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//CHECK: sha512h2.2d q0, q1, v2 ; encoding: [0x20,0x84,0x62,0xce]
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//CHECK: sha512su0.2d v11, v12 ; encoding: [0x8b,0x81,0xc0,0xce]
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//CHECK: sha512su1.2d v11, v13, v14 ; encoding: [0xab,0x89,0x6e,0xce]
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//CHECK: eor3.16b v25, v12, v7, v2 ; encoding: [0x99,0x09,0x07,0xce]
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//CHECK: rax1.2d v30, v29, v26 ; encoding: [0xbe,0x8f,0x7a,0xce]
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//CHECK: xar.2d v26, v21, v27, #63 ; encoding: [0xba,0xfe,0x9b,0xce]
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//CHECK: bcax.16b v31, v26, v2, v1 ; encoding: [0x5f,0x07,0x22,0xce]
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sm3ss1.4s v20, v23, v21, v22
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sm3tt1a.4s v20, v23, v21[3]
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sm3tt1b.4s v20, v23, v21[3]
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sm3tt2a.4s v20, v23, v21[3]
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sm3tt2b.4s v20, v23, v21[3]
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sm3partw1.4s v30, v29, v26
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sm3partw2.4s v30, v29, v26
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sm4ekey.4s v11, v11, v19
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sm4e.4s v2, v15
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// CHECK: sm3ss1.4s v20, v23, v21, v22 ; encoding: [0xf4,0x5a,0x55,0xce]
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// CHECK: sm3tt1a.4s v20, v23, v21[3] ; encoding: [0xf4,0xb2,0x55,0xce]
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// CHECK: sm3tt1b.4s v20, v23, v21[3] ; encoding: [0xf4,0xb6,0x55,0xce]
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// CHECK: sm3tt2a.4s v20, v23, v21[3] ; encoding: [0xf4,0xba,0x55,0xce]
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// CHECK: sm3tt2b.4s v20, v23, v21[3] ; encoding: [0xf4,0xbe,0x55,0xce]
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// CHECK: sm3partw1.4s v30, v29, v26 ; encoding: [0xbe,0xc3,0x7a,0xce]
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// CHECK: sm3partw2.4s v30, v29, v26 ; encoding: [0xbe,0xc7,0x7a,0xce]
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// CHECK: sm4ekey.4s v11, v11, v19 ; encoding: [0x6b,0xc9,0x73,0xce]
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// CHECK: sm4e.4s v2, v15 ; encoding: [0xe2,0x85,0xc0,0xce]
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