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[Target][ARM] Adding MVE VPT Optimisation Pass
Differential Revision: https://reviews.llvm.org/D76709
This commit is contained in:
Pierre-vh
parent
9d34186bb4
commit
5ddbe3862b
@ -47,6 +47,7 @@ FunctionPass *createARMConstantIslandPass();
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FunctionPass *createMLxExpansionPass();
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FunctionPass *createThumb2ITBlockPass();
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FunctionPass *createMVEVPTBlockPass();
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FunctionPass *createMVEVPTOptimisationsPass();
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FunctionPass *createARMOptimizeBarriersPass();
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FunctionPass *createThumb2SizeReductionPass(
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std::function<bool(const Function &)> Ftor = nullptr);
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@ -66,6 +67,7 @@ void initializeARMExpandPseudoPass(PassRegistry &);
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void initializeThumb2SizeReducePass(PassRegistry &);
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void initializeThumb2ITBlockPass(PassRegistry &);
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void initializeMVEVPTBlockPass(PassRegistry &);
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void initializeMVEVPTOptimisationsPass(PassRegistry &);
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void initializeARMLowOverheadLoopsPass(PassRegistry &);
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void initializeMVETailPredicationPass(PassRegistry &);
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void initializeMVEGatherScatterLoweringPass(PassRegistry &);
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@ -96,6 +96,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeARMTarget() {
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initializeARMExpandPseudoPass(Registry);
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initializeThumb2SizeReducePass(Registry);
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initializeMVEVPTBlockPass(Registry);
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initializeMVEVPTOptimisationsPass(Registry);
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initializeMVETailPredicationPass(Registry);
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initializeARMLowOverheadLoopsPass(Registry);
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initializeMVEGatherScatterLoweringPass(Registry);
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@ -487,6 +488,8 @@ bool ARMPassConfig::addGlobalInstructionSelect() {
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void ARMPassConfig::addPreRegAlloc() {
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if (getOptLevel() != CodeGenOpt::None) {
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addPass(createMVEVPTOptimisationsPass());
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addPass(createMLxExpansionPass());
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if (EnableARMLoadStoreOpt)
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@ -54,6 +54,7 @@ add_llvm_target(ARMCodeGen
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MVEGatherScatterLowering.cpp
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MVETailPredication.cpp
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MVEVPTBlockPass.cpp
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MVEVPTOptimisationsPass.cpp
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Thumb1FrameLowering.cpp
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Thumb1InstrInfo.cpp
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ThumbRegisterInfo.cpp
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232
lib/Target/ARM/MVEVPTOptimisationsPass.cpp
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232
lib/Target/ARM/MVEVPTOptimisationsPass.cpp
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@ -0,0 +1,232 @@
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//===-- MVEVPTOptimisationsPass.cpp ---------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This pass does a few optimisations related to MVE VPT blocks before
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/// register allocation is performed. The goal is to maximize the sizes of the
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/// blocks that will be created by the MVE VPT Block Insertion pass (which runs
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/// after register allocation). Currently, this pass replaces VCMPs with VPNOTs
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/// when possible, so the Block Insertion pass can delete them later to create
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/// larger VPT blocks.
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//===----------------------------------------------------------------------===//
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#include "ARM.h"
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#include "ARMSubtarget.h"
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#include "MCTargetDesc/ARMBaseInfo.h"
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#include "Thumb2InstrInfo.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/Support/Debug.h"
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#include <cassert>
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using namespace llvm;
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#define DEBUG_TYPE "arm-mve-vpt-opts"
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namespace {
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class MVEVPTOptimisations : public MachineFunctionPass {
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public:
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static char ID;
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const Thumb2InstrInfo *TII;
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MachineRegisterInfo *MRI;
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MVEVPTOptimisations() : MachineFunctionPass(ID) {}
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bool runOnMachineFunction(MachineFunction &Fn) override;
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StringRef getPassName() const override {
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return "ARM MVE VPT Optimisation Pass";
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}
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private:
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bool ReplaceVCMPsByVPNOTs(MachineBasicBlock &MBB);
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};
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char MVEVPTOptimisations::ID = 0;
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} // end anonymous namespace
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INITIALIZE_PASS(MVEVPTOptimisations, DEBUG_TYPE,
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"ARM MVE VPT Optimisations pass", false, false)
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// Returns true if Opcode is any VCMP Opcode.
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static bool IsVCMP(unsigned Opcode) { return VCMPOpcodeToVPT(Opcode) != 0; }
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// Returns true if a VCMP with this Opcode can have its operands swapped.
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// There is 2 kind of VCMP that can't have their operands swapped: Float VCMPs,
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// and VCMPr instructions (since the r is always on the right).
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static bool CanHaveSwappedOperands(unsigned Opcode) {
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switch (Opcode) {
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default:
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return true;
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case ARM::MVE_VCMPf32:
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case ARM::MVE_VCMPf16:
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case ARM::MVE_VCMPf32r:
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case ARM::MVE_VCMPf16r:
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case ARM::MVE_VCMPi8r:
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case ARM::MVE_VCMPi16r:
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case ARM::MVE_VCMPi32r:
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case ARM::MVE_VCMPu8r:
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case ARM::MVE_VCMPu16r:
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case ARM::MVE_VCMPu32r:
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case ARM::MVE_VCMPs8r:
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case ARM::MVE_VCMPs16r:
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case ARM::MVE_VCMPs32r:
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return false;
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}
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}
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// Returns the CondCode of a VCMP Instruction.
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static ARMCC::CondCodes GetCondCode(MachineInstr &Instr) {
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assert(IsVCMP(Instr.getOpcode()) && "Inst must be a VCMP");
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return ARMCC::CondCodes(Instr.getOperand(3).getImm());
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}
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// Returns true if Cond is equivalent to a VPNOT instruction on the result of
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// Prev. Cond and Prev must be VCMPs.
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static bool IsVPNOTEquivalent(MachineInstr &Cond, MachineInstr &Prev) {
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assert(IsVCMP(Cond.getOpcode()) && IsVCMP(Prev.getOpcode()));
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// Opcodes must match.
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if (Cond.getOpcode() != Prev.getOpcode())
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return false;
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MachineOperand &CondOP1 = Cond.getOperand(1), &CondOP2 = Cond.getOperand(2);
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MachineOperand &PrevOP1 = Prev.getOperand(1), &PrevOP2 = Prev.getOperand(2);
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// If the VCMP has the opposite condition with the same operands, we can
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// replace it with a VPNOT
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ARMCC::CondCodes ExpectedCode = GetCondCode(Cond);
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ExpectedCode = ARMCC::getOppositeCondition(ExpectedCode);
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if (ExpectedCode == GetCondCode(Prev))
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if (CondOP1.isIdenticalTo(PrevOP1) && CondOP2.isIdenticalTo(PrevOP2))
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return true;
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// Check again with operands swapped if possible
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if (!CanHaveSwappedOperands(Cond.getOpcode()))
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return false;
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ExpectedCode = ARMCC::getSwappedCondition(ExpectedCode);
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return ExpectedCode == GetCondCode(Prev) && CondOP1.isIdenticalTo(PrevOP2) &&
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CondOP2.isIdenticalTo(PrevOP1);
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}
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// Returns true if Instr writes to VCCR.
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static bool IsWritingToVCCR(MachineInstr &Instr) {
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if (Instr.getNumOperands() == 0)
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return false;
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MachineOperand &Dst = Instr.getOperand(0);
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if (!Dst.isReg())
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return false;
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Register DstReg = Dst.getReg();
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if (!DstReg.isVirtual())
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return false;
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MachineRegisterInfo &RegInfo = Instr.getMF()->getRegInfo();
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const TargetRegisterClass *RegClass = RegInfo.getRegClassOrNull(DstReg);
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return RegClass && (RegClass->getID() == ARM::VCCRRegClassID);
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}
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// This optimisation replaces VCMPs with VPNOTs when they are equivalent.
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bool MVEVPTOptimisations::ReplaceVCMPsByVPNOTs(MachineBasicBlock &MBB) {
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SmallVector<MachineInstr *, 4> DeadInstructions;
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// The last VCMP that we have seen and that couldn't be replaced.
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// This is reset when an instruction that writes to VCCR/VPR is found, or when
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// a VCMP is replaced with a VPNOT.
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// We'll only replace VCMPs with VPNOTs when this is not null, and when the
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// current VCMP is the opposite of PrevVCMP.
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MachineInstr *PrevVCMP = nullptr;
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// If we find an instruction that kills the result of PrevVCMP, we save the
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// operand here to remove the kill flag in case we need to use PrevVCMP's
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// result.
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MachineOperand *PrevVCMPResultKiller = nullptr;
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for (MachineInstr &Instr : MBB.instrs()) {
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if (PrevVCMP) {
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if (MachineOperand *MO = Instr.findRegisterUseOperand(
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PrevVCMP->getOperand(0).getReg(), /*isKill*/ true)) {
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// If we come accross the instr that kills PrevVCMP's result, record it
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// so we can remove the kill flag later if we need to.
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PrevVCMPResultKiller = MO;
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}
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}
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// Ignore predicated instructions.
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if (getVPTInstrPredicate(Instr) != ARMVCC::None)
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continue;
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// Only look at VCMPs
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if (!IsVCMP(Instr.getOpcode())) {
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// If the instruction writes to VCCR, forget the previous VCMP.
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if (IsWritingToVCCR(Instr))
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PrevVCMP = nullptr;
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continue;
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}
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if (!PrevVCMP || !IsVPNOTEquivalent(Instr, *PrevVCMP)) {
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PrevVCMP = &Instr;
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continue;
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}
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// The register containing the result of the VCMP that we're going to
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// replace.
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Register PrevVCMPResultReg = PrevVCMP->getOperand(0).getReg();
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// Build a VPNOT to replace the VCMP, reusing its operands.
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MachineInstrBuilder MIBuilder =
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BuildMI(MBB, &Instr, Instr.getDebugLoc(), TII->get(ARM::MVE_VPNOT))
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.add(Instr.getOperand(0))
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.addReg(PrevVCMPResultReg);
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addUnpredicatedMveVpredNOp(MIBuilder);
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LLVM_DEBUG(dbgs() << "Inserting VPNOT (to replace VCMP): ";
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MIBuilder.getInstr()->dump(); dbgs() << " Removed VCMP: ";
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Instr.dump());
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// If we found an instruction that uses, and kills PrevVCMP's result,
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// remove the kill flag.
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if (PrevVCMPResultKiller)
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PrevVCMPResultKiller->setIsKill(false);
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// Finally, mark the old VCMP for removal and reset
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// PrevVCMP/PrevVCMPResultKiller.
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DeadInstructions.push_back(&Instr);
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PrevVCMP = nullptr;
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PrevVCMPResultKiller = nullptr;
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}
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for (MachineInstr *DeadInstruction : DeadInstructions)
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DeadInstruction->removeFromParent();
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return !DeadInstructions.empty();
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}
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bool MVEVPTOptimisations::runOnMachineFunction(MachineFunction &Fn) {
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const ARMSubtarget &STI =
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static_cast<const ARMSubtarget &>(Fn.getSubtarget());
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if (!STI.isThumb2() || !STI.hasMVEIntegerOps())
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return false;
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TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
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MRI = &Fn.getRegInfo();
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LLVM_DEBUG(dbgs() << "********** ARM MVE VPT Optimisations **********\n"
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<< "********** Function: " << Fn.getName() << '\n');
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bool Modified = false;
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for (MachineBasicBlock &MBB : Fn)
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Modified |= ReplaceVCMPsByVPNOTs(MBB);
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LLVM_DEBUG(dbgs() << "**************************************\n");
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return Modified;
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}
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/// createMVEVPTOptimisationsPass
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FunctionPass *llvm::createMVEVPTOptimisationsPass() {
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return new MVEVPTOptimisations();
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}
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@ -92,6 +92,7 @@
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; CHECK-NEXT: Machine code sinking
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; CHECK-NEXT: Peephole Optimizations
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; CHECK-NEXT: Remove dead machine instructions
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; CHECK-NEXT: MVE VPT Optimisation Pass
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; CHECK-NEXT: ARM MLA / MLS expansion pass
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; CHECK-NEXT: ARM pre- register allocation load / store optimization pass
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; CHECK-NEXT: ARM A15 S->D optimizer
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323
test/CodeGen/Thumb2/mve-vpt-blocks.ll
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323
test/CodeGen/Thumb2/mve-vpt-blocks.ll
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@ -0,0 +1,323 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -mtriple=thumbv8.1m.main-arm-none-eabi --verify-machineinstrs -mattr=+mve.fp %s -o - | FileCheck %s
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declare <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32>, <4 x i32>, <4 x i1>, <4 x i32>)
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define arm_aapcs_vfpcc <4 x i32> @vpt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: vpt_block:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpt.s32 ge, q0, q2
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; CHECK-NEXT: vorrt q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp sge <4 x i32> %a, %c
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%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
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ret <4 x i32> %1
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}
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define arm_aapcs_vfpcc <4 x i32> @vptt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: vptt_block:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmov q3, q0
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; CHECK-NEXT: vptt.s32 ge, q0, q2
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; CHECK-NEXT: vorrt q3, q1, q2
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; CHECK-NEXT: vorrt q0, q3, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp sge <4 x i32> %a, %c
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%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
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%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %1, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
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ret <4 x i32> %2
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}
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define arm_aapcs_vfpcc <4 x i32> @vpttt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: vpttt_block:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpttt.s32 ge, q0, q2
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; CHECK-NEXT: vorrt q0, q1, q2
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; CHECK-NEXT: vorrt q0, q1, q2
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; CHECK-NEXT: vorrt q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp sge <4 x i32> %a, %c
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%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
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%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)
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%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %2)
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vptttt_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: vptttt_block:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vptttt.s32 ge, q0, q2
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; CHECK-NEXT: vorrt q0, q1, q2
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; CHECK-NEXT: vorrt q0, q1, q2
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; CHECK-NEXT: vorrt q0, q1, q2
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; CHECK-NEXT: vorrt q0, q1, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp sge <4 x i32> %a, %c
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%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
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%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)
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%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %2)
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%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)
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ret <4 x i32> %4
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}
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define arm_aapcs_vfpcc <4 x i32> @vpte_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: vpte_block:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vpte.s32 ge, q0, q2
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; CHECK-NEXT: vorrt q0, q1, q2
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; CHECK-NEXT: vmove q0, q2
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; CHECK-NEXT: bx lr
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entry:
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%0 = icmp sge <4 x i32> %a, %c
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%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
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%2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
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%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)
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ret <4 x i32> %3
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}
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define arm_aapcs_vfpcc <4 x i32> @vptte_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
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; CHECK-LABEL: vptte_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vptte.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vorre q0, q1, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %2)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %1, <4 x i32> %3)
|
||||
ret <4 x i32> %4
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @vptee_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: vptee_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vptee.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vorre q0, q1, q2
|
||||
; CHECK-NEXT: vorre q0, q1, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%2 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %1, <4 x i32> %2)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %1, <4 x i32> %3)
|
||||
ret <4 x i32> %4
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @vptet_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: vptet_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .pad #4
|
||||
; CHECK-NEXT: sub sp, #4
|
||||
; CHECK-NEXT: vcmp.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpnot
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: add sp, #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)
|
||||
ret <4 x i32> %4
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @vpttet_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: vpttet_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .pad #4
|
||||
; CHECK-NEXT: sub sp, #4
|
||||
; CHECK-NEXT: vcmp.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
|
||||
; CHECK-NEXT: vpstt
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpnot
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: add sp, #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %3)
|
||||
%5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %4)
|
||||
ret <4 x i32> %5
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @vptett_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: vptett_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .pad #4
|
||||
; CHECK-NEXT: sub sp, #4
|
||||
; CHECK-NEXT: vcmp.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpnot
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpstt
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: add sp, #4
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)
|
||||
%5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %4)
|
||||
ret <4 x i32> %5
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @vpteet_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: vpteet_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .pad #8
|
||||
; CHECK-NEXT: sub sp, #8
|
||||
; CHECK-NEXT: vcmp.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpnot
|
||||
; CHECK-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
|
||||
; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: add sp, #8
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %3)
|
||||
%5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %4)
|
||||
ret <4 x i32> %5
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @vpteee_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: vpteee_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vpteee.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vmove q0, q2
|
||||
; CHECK-NEXT: vmove q0, q2
|
||||
; CHECK-NEXT: vmove q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %3)
|
||||
%5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %4)
|
||||
ret <4 x i32> %5
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @vptete_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: vptete_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: .pad #8
|
||||
; CHECK-NEXT: sub sp, #8
|
||||
; CHECK-NEXT: vcmp.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vstr p0, [sp] @ 4-byte Spill
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpnot
|
||||
; CHECK-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
|
||||
; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vldr p0, [sp] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vldr p0, [sp, #4] @ 4-byte Reload
|
||||
; CHECK-NEXT: vpst
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: add sp, #8
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %1)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)
|
||||
%5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %4)
|
||||
ret <4 x i32> %5
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @vpttte_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: vpttte_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vpttte.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vmove q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %3)
|
||||
%5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %4)
|
||||
ret <4 x i32> %5
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x i32> @vpttee_block(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c) {
|
||||
; CHECK-LABEL: vpttee_block:
|
||||
; CHECK: @ %bb.0: @ %entry
|
||||
; CHECK-NEXT: vpttee.s32 ge, q0, q2
|
||||
; CHECK-NEXT: vorrt q0, q1, q2
|
||||
; CHECK-NEXT: vmovt q0, q2
|
||||
; CHECK-NEXT: vmove q0, q2
|
||||
; CHECK-NEXT: vmove q0, q2
|
||||
; CHECK-NEXT: bx lr
|
||||
entry:
|
||||
%0 = icmp sge <4 x i32> %a, %c
|
||||
%1 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %b, <4 x i32> %c, <4 x i1> %0, <4 x i32> %a)
|
||||
%2 = xor <4 x i1> %0, <i1 true, i1 true, i1 true, i1 true>
|
||||
%3 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %0, <4 x i32> %1)
|
||||
%4 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %3)
|
||||
%5 = tail call <4 x i32> @llvm.arm.mve.orr.predicated.v4i32.v4i1(<4 x i32> %c, <4 x i32> %c, <4 x i1> %2, <4 x i32> %4)
|
||||
ret <4 x i32> %5
|
||||
}
|
||||
547
test/CodeGen/Thumb2/mve-vpt-optimisations.mir
Normal file
547
test/CodeGen/Thumb2/mve-vpt-optimisations.mir
Normal file
@ -0,0 +1,547 @@
|
||||
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
|
||||
# RUN: llc -run-pass arm-mve-vpt-opts %s -o - | FileCheck %s
|
||||
|
||||
--- |
|
||||
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
|
||||
target triple = "thumbv8.1m.main-arm-none-eabi"
|
||||
|
||||
; Functions are intentionally left blank - see the MIR sequences below.
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @vcmp_with_opposite_cond(<4 x float> %inactive1) #0 {
|
||||
entry:
|
||||
ret <4 x float> %inactive1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @vcmp_with_opposite_cond_and_swapped_operands(<4 x float> %inactive1) #0 {
|
||||
entry:
|
||||
ret <4 x float> %inactive1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @triple_vcmp(<4 x float> %inactive1) #0 {
|
||||
entry:
|
||||
ret <4 x float> %inactive1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @killed_vccr_values(<4 x float> %inactive1) #0 {
|
||||
entry:
|
||||
ret <4 x float> %inactive1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @predicated_vcmps(<4 x float> %inactive1) #0 {
|
||||
entry:
|
||||
ret <4 x float> %inactive1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @flt_with_swapped_operands(<4 x float> %inactive1) #0 {
|
||||
entry:
|
||||
ret <4 x float> %inactive1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @different_opcodes(<4 x float> %inactive1) #0 {
|
||||
entry:
|
||||
ret <4 x float> %inactive1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @incorrect_condcode(<4 x float> %inactive1) #0 {
|
||||
entry:
|
||||
ret <4 x float> %inactive1
|
||||
}
|
||||
|
||||
define arm_aapcs_vfpcc <4 x float> @vpr_or_vccr_write_between_vcmps(<4 x float> %inactive1) #0 {
|
||||
entry:
|
||||
ret <4 x float> %inactive1
|
||||
}
|
||||
|
||||
attributes #0 = { "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" }
|
||||
...
|
||||
---
|
||||
name: vcmp_with_opposite_cond
|
||||
alignment: 4
|
||||
body: |
|
||||
; CHECK-LABEL: name: vcmp_with_opposite_cond
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32_]], 0, $noreg
|
||||
; CHECK: bb.2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg
|
||||
; CHECK: bb.3:
|
||||
; CHECK: successors: %bb.4(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg
|
||||
; CHECK: bb.4:
|
||||
; CHECK: successors: %bb.5(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg
|
||||
; CHECK: bb.5:
|
||||
; CHECK: successors: %bb.6(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg
|
||||
; CHECK: bb.6:
|
||||
; CHECK: successors: %bb.7(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg
|
||||
; CHECK: bb.7:
|
||||
; CHECK: successors: %bb.8(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg
|
||||
; CHECK: bb.8:
|
||||
; CHECK: successors: %bb.9(0x80000000)
|
||||
; CHECK: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg
|
||||
; CHECK: bb.9:
|
||||
; CHECK: successors: %bb.10(0x80000000)
|
||||
; CHECK: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT9:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg
|
||||
; CHECK: bb.10:
|
||||
; CHECK: successors: %bb.11(0x80000000)
|
||||
; CHECK: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT10:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg
|
||||
; CHECK: bb.11:
|
||||
; CHECK: successors: %bb.12(0x80000000)
|
||||
; CHECK: [[MVE_VCMPf16r:%[0-9]+]]:vccr = MVE_VCMPf16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT11:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16r]], 0, $noreg
|
||||
; CHECK: bb.12:
|
||||
; CHECK: successors: %bb.13(0x80000000)
|
||||
; CHECK: [[MVE_VCMPf32r:%[0-9]+]]:vccr = MVE_VCMPf32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT12:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf32r]], 0, $noreg
|
||||
; CHECK: bb.13:
|
||||
; CHECK: successors: %bb.14(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi16r:%[0-9]+]]:vccr = MVE_VCMPi16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT13:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16r]], 0, $noreg
|
||||
; CHECK: bb.14:
|
||||
; CHECK: successors: %bb.15(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi32r:%[0-9]+]]:vccr = MVE_VCMPi32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT14:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32r]], 0, $noreg
|
||||
; CHECK: bb.15:
|
||||
; CHECK: successors: %bb.16(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi8r:%[0-9]+]]:vccr = MVE_VCMPi8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT15:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8r]], 0, $noreg
|
||||
; CHECK: bb.16:
|
||||
; CHECK: successors: %bb.17(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs16r:%[0-9]+]]:vccr = MVE_VCMPs16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT16:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16r]], 0, $noreg
|
||||
; CHECK: bb.17:
|
||||
; CHECK: successors: %bb.18(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs32r:%[0-9]+]]:vccr = MVE_VCMPs32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT17:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32r]], 0, $noreg
|
||||
; CHECK: bb.18:
|
||||
; CHECK: successors: %bb.19(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs8r:%[0-9]+]]:vccr = MVE_VCMPs8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT18:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8r]], 0, $noreg
|
||||
; CHECK: bb.19:
|
||||
; CHECK: successors: %bb.20(0x80000000)
|
||||
; CHECK: [[MVE_VCMPu16r:%[0-9]+]]:vccr = MVE_VCMPu16r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT19:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16r]], 0, $noreg
|
||||
; CHECK: bb.20:
|
||||
; CHECK: successors: %bb.21(0x80000000)
|
||||
; CHECK: [[MVE_VCMPu32r:%[0-9]+]]:vccr = MVE_VCMPu32r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT20:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32r]], 0, $noreg
|
||||
; CHECK: bb.21:
|
||||
; CHECK: successors: %bb.22(0x80000000)
|
||||
; CHECK: [[MVE_VCMPu8r:%[0-9]+]]:vccr = MVE_VCMPu8r %1:mqpr, %25:gprwithzr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT21:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r]], 0, $noreg
|
||||
; CHECK: bb.22:
|
||||
; CHECK: [[MVE_VCMPu8r1:%[0-9]+]]:vccr = MVE_VCMPu8r %1:mqpr, $zr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT22:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8r1]], 0, $noreg
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||||
;
|
||||
; Tests that VCMPs with an opposite condition are correctly converted into VPNOTs.
|
||||
;
|
||||
bb.0:
|
||||
%3:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%4:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.1:
|
||||
%5:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%6:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.2:
|
||||
%7:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%8:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.3:
|
||||
%9:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%10:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.4:
|
||||
%11:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%12:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.5:
|
||||
%13:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%14:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.6:
|
||||
%15:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%16:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.7:
|
||||
%17:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%18:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.8:
|
||||
%19:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%20:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.9:
|
||||
%21:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%22:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.10:
|
||||
%23:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%24:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.11:
|
||||
%25:vccr = MVE_VCMPf16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%26:vccr = MVE_VCMPf16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.12:
|
||||
%27:vccr = MVE_VCMPf32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%28:vccr = MVE_VCMPf32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.13:
|
||||
%29:vccr = MVE_VCMPi16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%30:vccr = MVE_VCMPi16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.14:
|
||||
%31:vccr = MVE_VCMPi32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%32:vccr = MVE_VCMPi32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.15:
|
||||
%33:vccr = MVE_VCMPi8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%34:vccr = MVE_VCMPi8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.16:
|
||||
%35:vccr = MVE_VCMPs16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%36:vccr = MVE_VCMPs16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.17:
|
||||
%37:vccr = MVE_VCMPs32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%38:vccr = MVE_VCMPs32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.18:
|
||||
%39:vccr = MVE_VCMPs8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%40:vccr = MVE_VCMPs8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.19:
|
||||
%41:vccr = MVE_VCMPu16r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%42:vccr = MVE_VCMPu16r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.20:
|
||||
%43:vccr = MVE_VCMPu32r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%44:vccr = MVE_VCMPu32r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.21:
|
||||
%45:vccr = MVE_VCMPu8r %0:mqpr, %2:gprwithzr, 10, 0, $noreg
|
||||
%46:vccr = MVE_VCMPu8r %0:mqpr, %2:gprwithzr, 11, 0, $noreg
|
||||
|
||||
bb.22:
|
||||
; There shouldn't be any exception for $zr, so the second VCMP should
|
||||
; be transformed into a VPNOT.
|
||||
%47:vccr = MVE_VCMPu8r %0:mqpr, $zr, 10, 0, $noreg
|
||||
%48:vccr = MVE_VCMPu8r %0:mqpr, $zr, 11, 0, $noreg
|
||||
|
||||
tBX_RET 14, $noreg, implicit %0:mqpr
|
||||
...
|
||||
---
|
||||
name: vcmp_with_opposite_cond_and_swapped_operands
|
||||
alignment: 4
|
||||
body: |
|
||||
; CHECK-LABEL: name: vcmp_with_opposite_cond_and_swapped_operands
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi16_]], 0, $noreg
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT1:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi32_]], 0, $noreg
|
||||
; CHECK: bb.2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi8_:%[0-9]+]]:vccr = MVE_VCMPi8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT2:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPi8_]], 0, $noreg
|
||||
; CHECK: bb.3:
|
||||
; CHECK: successors: %bb.4(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs16_:%[0-9]+]]:vccr = MVE_VCMPs16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT3:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs16_]], 0, $noreg
|
||||
; CHECK: bb.4:
|
||||
; CHECK: successors: %bb.5(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT4:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg
|
||||
; CHECK: bb.5:
|
||||
; CHECK: successors: %bb.6(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs8_:%[0-9]+]]:vccr = MVE_VCMPs8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT5:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs8_]], 0, $noreg
|
||||
; CHECK: bb.6:
|
||||
; CHECK: successors: %bb.7(0x80000000)
|
||||
; CHECK: [[MVE_VCMPu16_:%[0-9]+]]:vccr = MVE_VCMPu16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT6:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu16_]], 0, $noreg
|
||||
; CHECK: bb.7:
|
||||
; CHECK: successors: %bb.8(0x80000000)
|
||||
; CHECK: [[MVE_VCMPu32_:%[0-9]+]]:vccr = MVE_VCMPu32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT7:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu32_]], 0, $noreg
|
||||
; CHECK: bb.8:
|
||||
; CHECK: [[MVE_VCMPu8_:%[0-9]+]]:vccr = MVE_VCMPu8 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT8:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPu8_]], 0, $noreg
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||||
;
|
||||
; Tests that VCMPs with an opposite condition and swapped operands are
|
||||
; correctly converted into VPNOTs.
|
||||
;
|
||||
bb.0:
|
||||
%2:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%3:vccr = MVE_VCMPi16 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.1:
|
||||
%4:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%5:vccr = MVE_VCMPi32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.2:
|
||||
%6:vccr = MVE_VCMPi8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%7:vccr = MVE_VCMPi8 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.3:
|
||||
%8:vccr = MVE_VCMPs16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%9:vccr = MVE_VCMPs16 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.4:
|
||||
%10:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%11:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.5:
|
||||
%12:vccr = MVE_VCMPs8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%13:vccr = MVE_VCMPs8 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.6:
|
||||
%14:vccr = MVE_VCMPu16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%15:vccr = MVE_VCMPu16 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.7:
|
||||
%16:vccr = MVE_VCMPu32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%17:vccr = MVE_VCMPu32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.8:
|
||||
%18:vccr = MVE_VCMPu8 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%19:vccr = MVE_VCMPu8 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
tBX_RET 14, $noreg, implicit %0:mqpr
|
||||
...
|
||||
---
|
||||
name: triple_vcmp
|
||||
alignment: 4
|
||||
body: |
|
||||
;
|
||||
; Tests that, when there are 2 "VPNOT-like VCMPs" in a row, only the first
|
||||
; becomes a VPNOT.
|
||||
;
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: triple_vcmp
|
||||
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPs32_]], 0, $noreg
|
||||
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 12, 0, $noreg
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||||
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
%4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
tBX_RET 14, $noreg, implicit %0:mqpr
|
||||
...
|
||||
---
|
||||
name: killed_vccr_values
|
||||
alignment: 4
|
||||
body: |
|
||||
bb.0:
|
||||
;
|
||||
; Tests that, if the result of the VCMP is killed before the
|
||||
; second VCMP (that will be converted into a VPNOT) is found,
|
||||
; the kill flag is removed.
|
||||
;
|
||||
; CHECK-LABEL: name: killed_vccr_values
|
||||
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR %1:mqpr, %2:mqpr, 1, [[MVE_VCMPf16_]], undef [[MVE_VORR]]
|
||||
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT [[MVE_VCMPf16_]], 0, $noreg
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||||
%2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%3:mqpr = MVE_VORR %0:mqpr, %1:mqpr, 1, killed %2:vccr, undef %3:mqpr
|
||||
%4:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
tBX_RET 14, $noreg, implicit %0:mqpr
|
||||
...
|
||||
---
|
||||
name: predicated_vcmps
|
||||
alignment: 4
|
||||
body: |
|
||||
; CHECK-LABEL: name: predicated_vcmps
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi16_:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPi16_1:%[0-9]+]]:vccr = MVE_VCMPi16 %2:mqpr, %1:mqpr, 12, 1, [[MVE_VCMPi16_]]
|
||||
; CHECK: [[MVE_VCMPi16_2:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi16_]]
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi32_:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPi32_1:%[0-9]+]]:vccr = MVE_VCMPi32 %2:mqpr, %1:mqpr, 12, 1, [[MVE_VCMPi32_]]
|
||||
; CHECK: [[MVE_VCMPi32_2:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi32_]]
|
||||
; CHECK: bb.2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPf16_]]
|
||||
; CHECK: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPf16_]]
|
||||
; CHECK: bb.3:
|
||||
; CHECK: successors: %bb.4(0x80000000)
|
||||
; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPf32_]]
|
||||
; CHECK: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPf32_]]
|
||||
; CHECK: bb.4:
|
||||
; CHECK: successors: %bb.5(0x80000000)
|
||||
; CHECK: [[MVE_VCMPi16_3:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPi16_4:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPi16_3]]
|
||||
; CHECK: [[MVE_VCMPi16_5:%[0-9]+]]:vccr = MVE_VCMPi16 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi16_3]]
|
||||
; CHECK: bb.5:
|
||||
; CHECK: [[MVE_VCMPi32_3:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPi32_4:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 11, 1, [[MVE_VCMPi32_3]]
|
||||
; CHECK: [[MVE_VCMPi32_5:%[0-9]+]]:vccr = MVE_VCMPi32 %1:mqpr, %2:mqpr, 10, 1, [[MVE_VCMPi32_3]]
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||||
;
|
||||
; Tests that predicated VCMPs are not replaced.
|
||||
;
|
||||
bb.0:
|
||||
%2:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%3:vccr = MVE_VCMPi16 %1:mqpr, %0:mqpr, 12, 1, %2:vccr
|
||||
%4:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 1, %2:vccr
|
||||
|
||||
bb.1:
|
||||
%5:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%6:vccr = MVE_VCMPi32 %1:mqpr, %0:mqpr, 12, 1, %5:vccr
|
||||
%7:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 1, %5:vccr
|
||||
|
||||
bb.2:
|
||||
%8:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%9:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 11, 1, %8:vccr
|
||||
%10:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 1, %8:vccr
|
||||
|
||||
bb.3:
|
||||
%11:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%12:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 11, 1, %11:vccr
|
||||
%13:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 1, %11:vccr
|
||||
|
||||
bb.4:
|
||||
%14:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%15:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 11, 1, %14:vccr
|
||||
%16:vccr = MVE_VCMPi16 %0:mqpr, %1:mqpr, 10, 1, %14:vccr
|
||||
|
||||
bb.5:
|
||||
%17:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%18:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 11, 1, %17:vccr
|
||||
%19:vccr = MVE_VCMPi32 %0:mqpr, %1:mqpr, 10, 1, %17:vccr
|
||||
|
||||
tBX_RET 14, $noreg, implicit %0:mqpr
|
||||
...
|
||||
---
|
||||
name: flt_with_swapped_operands
|
||||
alignment: 4
|
||||
body: |
|
||||
; CHECK-LABEL: name: flt_with_swapped_operands
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPf16_1:%[0-9]+]]:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 12, 0, $noreg
|
||||
; CHECK: bb.1:
|
||||
; CHECK: successors: %bb.2(0x80000000)
|
||||
; CHECK: [[MVE_VCMPf32_:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPf32_1:%[0-9]+]]:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 12, 0, $noreg
|
||||
; CHECK: bb.2:
|
||||
; CHECK: successors: %bb.3(0x80000000)
|
||||
; CHECK: [[MVE_VCMPf16_2:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPf16_3:%[0-9]+]]:vccr = MVE_VCMPf16 %2:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
; CHECK: bb.3:
|
||||
; CHECK: [[MVE_VCMPf32_2:%[0-9]+]]:vccr = MVE_VCMPf32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPf32_3:%[0-9]+]]:vccr = MVE_VCMPf32 %2:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||||
;
|
||||
; Tests that float VCMPs with an opposite condition and swapped operands
|
||||
; are not transformed into VPNOTs.
|
||||
;
|
||||
bb.0:
|
||||
%2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%3:vccr = MVE_VCMPf16 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.1:
|
||||
%4:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%5:vccr = MVE_VCMPf32 %1:mqpr, %0:mqpr, 12, 0, $noreg
|
||||
|
||||
bb.2:
|
||||
%6:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%7:vccr = MVE_VCMPf16 %1:mqpr, %0:mqpr, 11, 0, $noreg
|
||||
|
||||
bb.3:
|
||||
%8:vccr = MVE_VCMPf32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%9:vccr = MVE_VCMPf32 %1:mqpr, %0:mqpr, 11, 0, $noreg
|
||||
tBX_RET 14, $noreg, implicit %0:mqpr
|
||||
...
|
||||
---
|
||||
name: different_opcodes
|
||||
alignment: 4
|
||||
body: |
|
||||
;
|
||||
; Tests that a "VPNOT-like VCMP" with an opcode different from the previous VCMP
|
||||
; is not transformed into a VPNOT.
|
||||
;
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: different_opcodes
|
||||
; CHECK: [[MVE_VCMPf16_:%[0-9]+]]:vccr = MVE_VCMPf16 %1:mqpr, %2:mqpr, 0, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 1, 1, $noreg
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||||
%2:vccr = MVE_VCMPf16 %0:mqpr, %1:mqpr, 0, 0, $noreg
|
||||
%3:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 1, 1, $noreg
|
||||
tBX_RET 14, $noreg, implicit %0:mqpr
|
||||
...
|
||||
---
|
||||
name: incorrect_condcode
|
||||
alignment: 4
|
||||
body: |
|
||||
; CHECK-LABEL: name: incorrect_condcode
|
||||
; CHECK: bb.0:
|
||||
; CHECK: successors: %bb.1(0x80000000)
|
||||
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 11, 0, $noreg
|
||||
; CHECK: bb.1:
|
||||
; CHECK: [[MVE_VCMPs32_2:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 10, 0, $noreg
|
||||
; CHECK: [[MVE_VCMPs32_3:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||||
;
|
||||
; Tests that a VCMP is not transformed into a VPNOT if its CondCode is not
|
||||
; the opposite CondCode.
|
||||
;
|
||||
bb.0:
|
||||
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%3:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 11, 0, $noreg
|
||||
bb.1:
|
||||
%4:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
%5:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 12, 0, $noreg
|
||||
tBX_RET 14, $noreg, implicit %0:mqpr
|
||||
...
|
||||
---
|
||||
name: vpr_or_vccr_write_between_vcmps
|
||||
alignment: 4
|
||||
body: |
|
||||
;
|
||||
; Tests that a "VPNOT-like VCMP" will not be transformed into a VPNOT if
|
||||
; VCCR/VPR is written to in-between.
|
||||
;
|
||||
bb.0:
|
||||
; CHECK-LABEL: name: vpr_or_vccr_write_between_vcmps
|
||||
; CHECK: [[MVE_VCMPs32_:%[0-9]+]]:vccr = MVE_VCMPs32 %1:mqpr, %2:mqpr, 12, 0, $noreg
|
||||
; CHECK: [[MVE_VPNOT:%[0-9]+]]:vccr = MVE_VPNOT killed [[MVE_VCMPs32_]], 0, $noreg
|
||||
; CHECK: [[MVE_VCMPs32_1:%[0-9]+]]:vccr = MVE_VCMPs32 %2:mqpr, %1:mqpr, 10, 0, $noreg
|
||||
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit %1:mqpr
|
||||
%2:vccr = MVE_VCMPs32 %0:mqpr, %1:mqpr, 12, 0, $noreg
|
||||
%3:vccr = MVE_VPNOT killed %2:vccr, 0, $noreg
|
||||
%4:vccr = MVE_VCMPs32 %1:mqpr, %0:mqpr, 10, 0, $noreg
|
||||
tBX_RET 14, $noreg, implicit %0:mqpr
|
||||
...
|
||||
Loading…
Reference in New Issue
Block a user