RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Code Issues Projects Releases Wiki Activity

Tweak ARM fixup value adjustments for Thumb to better handle the half-word

Browse Source 
ordering of thumb mode.

llvm-svn: 121280
This commit is contained in:
Jim Grosbach 2010-12-08 20:32:07 +00:00
parent 53f05af4c1
commit 5e900612ff
1 changed files with 15 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
lib/Target/ARM/ARMAsmBackend.cpp
View File

@ -134,17 +134,24 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
// xxxxxSIIIIIIIIII xxxxxIIIIIIIIIII
// Note that the halfwords are stored high first, low second; so we need
// to transpose the fixup value here to map properly.
// FIXME: Something isn't quite right with this. Some, but not all, BLX
// instructions are getting the encoded value off by one.
uint32_t Binary = 0x3fffff & ((Value - 4) >> 1);
Binary = ((Binary & 0x7ff) << 16) | (Binary >> 11);
return Binary;
}
case ARM::fixup_arm_thumb_cp:
// Offset by 4, and don't encode the low two bits.
return ((Value - 4) >> 2) & 0xff;
case ARM::fixup_t2_pcrel_10:
case ARM::fixup_arm_pcrel_10: {
// Offset by 8 just as above.
Value = Value - 8;
// Offset by 4, and don't encode the low two bits. Two bytes of that
// 'off by 4' is implicitly handled by the half-word ordering of the
// Thumb encoding, so we only need to adjust by 2 here.
return ((Value - 2) >> 2) & 0xff;
case ARM::fixup_arm_pcrel_10:
Value = Value - 6; // ARM fixups offset by an additional word and don't
// need to adjust for the half-word ordering.
// Fall through.
case ARM::fixup_t2_pcrel_10: {
// Offset by 4, adjusted by two due to the half-word ordering of thumb.
Value = Value - 2;
bool isAdd = true;
if ((int64_t)Value < 0) {
Value = -Value;
@ -154,7 +161,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
Value >>= 2;
assert ((Value < 256) && "Out of range pc-relative fixup value!");
Value |= isAdd << 23;
// Same addressing mode as fixup_arm_pcrel_10,
// but with 16-bit halfwords swapped.
if (Kind == ARM::fixup_t2_pcrel_10) {
@ -162,7 +169,7 @@ static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) {
swapped |= (Value & 0x0000FFFF) << 16;
return swapped;
}
return Value;
}
}