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AMDGPU: Allow rcp and rsq usage with f16
llvm-svn: 290302
This commit is contained in:
Matt Arsenault
parent
a844bf67ff
commit
5ecf306700
@ -324,7 +324,6 @@ static bool shouldKeepFDivF32(Value *Num, bool UnsafeDiv) {
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bool AMDGPUCodeGenPrepare::visitFDiv(BinaryOperator &FDiv) {
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Type *Ty = FDiv.getType();
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// TODO: Handle half
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if (!Ty->getScalarType()->isFloatTy())
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return false;
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@ -2925,16 +2925,18 @@ SDValue SITargetLowering::lowerFastUnsafeFDIV(SDValue Op,
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bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
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if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
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if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals()))) {
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if (Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals()) ||
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VT == MVT::f16) {
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if (CLHS->isExactlyValue(1.0)) {
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// v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
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// the CI documentation has a worst case error of 1 ulp.
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// OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
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// use it as long as we aren't trying to use denormals.
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//
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// v_rcp_f16 and v_rsq_f16 DO support denormals.
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// 1.0 / sqrt(x) -> rsq(x)
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//
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// XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
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// error seems really high at 2^29 ULP.
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if (RHS.getOpcode() == ISD::FSQRT)
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@ -3009,6 +3011,9 @@ static SDValue getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL,
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}
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SDValue SITargetLowering::LowerFDIV16(SDValue Op, SelectionDAG &DAG) const {
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if (SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
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return FastLowered;
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SDLoc SL(Op);
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SDValue Src0 = Op.getOperand(0);
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SDValue Src1 = Op.getOperand(1);
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@ -1,9 +1,10 @@
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=+fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-fp16-denormals -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; Make sure fdiv is promoted to f32.
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; GCN-LABEL: {{^}}fdiv_f16
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; GCN-LABEL: {{^}}v_fdiv_f16
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; SI: v_cvt_f32_f16
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; SI: v_cvt_f32_f16
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; SI: v_div_scale_f32
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@ -19,8 +20,8 @@
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; SI: v_div_fixup_f32
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; SI: v_cvt_f16_f32
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; VI: buffer_load_ushort [[LHS:v[0-9]+]]
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; VI: buffer_load_ushort [[RHS:v[0-9]+]]
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; VI: flat_load_ushort [[LHS:v[0-9]+]]
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; VI: flat_load_ushort [[RHS:v[0-9]+]]
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; VI-DAG: v_cvt_f32_f16_e32 [[CVT_LHS:v[0-9]+]], [[LHS]]
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; VI-DAG: v_cvt_f32_f16_e32 [[CVT_RHS:v[0-9]+]], [[RHS]]
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@ -29,15 +30,184 @@
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; VI: v_mul_f32_e32 [[MUL:v[0-9]+]], [[RCP_RHS]], [[CVT_LHS]]
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; VI: v_cvt_f16_f32_e32 [[CVT_BACK:v[0-9]+]], [[MUL]]
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; VI: v_div_fixup_f16 [[RESULT:v[0-9]+]], [[CVT_BACK]], [[RHS]], [[LHS]]
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; VI: buffer_store_short [[RESULT]]
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define void @fdiv_f16(
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_fdiv_f16(
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half addrspace(1)* %r,
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half addrspace(1)* %a,
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half addrspace(1)* %b) {
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half addrspace(1)* %b) #0 {
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entry:
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%a.val = load volatile half, half addrspace(1)* %a
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%b.val = load volatile half, half addrspace(1)* %b
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.a = getelementptr inbounds half, half addrspace(1)* %a, i64 %tid.ext
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%a.val = load volatile half, half addrspace(1)* %gep.a
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv half %a.val, %b.val
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store half %r.val, half addrspace(1)* %r
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rcp_f16:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; VI-NOT: [[RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rcp_f16(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv half 1.0, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rcp_f16_abs:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e64 [[RESULT:v[0-9]+]], |[[VAL]]|
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rcp_f16_abs(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%b.abs = call half @llvm.fabs.f16(half %b.val)
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%r.val = fdiv half 1.0, %b.abs
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rcp_f16_arcp:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; VI-NOT: [[RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rcp_f16_arcp(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv arcp half 1.0, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rcp_f16_neg:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rcp_f16_e64 [[RESULT:v[0-9]+]], -[[VAL]]
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rcp_f16_neg(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv half -1.0, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rsq_f16:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_rsq_f16_e32 [[RESULT:v[0-9]+]], [[VAL]]
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rsq_f16(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%b.sqrt = call half @llvm.sqrt.f16(half %b.val)
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%r.val = fdiv half 1.0, %b.sqrt
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_rsq_f16_neg:
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; VI: flat_load_ushort [[VAL:v[0-9]+]]
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; VI-NOT: [[VAL]]
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; VI: v_sqrt_f16_e32 [[SQRT:v[0-9]+]], [[VAL]]
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; VI-NEXT: v_rcp_f16_e64 [[RESULT:v[0-9]+]], -[[SQRT]]
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; VI-NOT: [RESULT]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_rsq_f16_neg(half addrspace(1)* %r, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%b.sqrt = call half @llvm.sqrt.f16(half %b.val)
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%r.val = fdiv half -1.0, %b.sqrt
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_fdiv_f16_arcp:
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; VI: flat_load_ushort [[LHS:v[0-9]+]]
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; VI: flat_load_ushort [[RHS:v[0-9]+]]
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; VI: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
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; VI: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[RCP]], [[LHS]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_fdiv_f16_arcp(half addrspace(1)* %r, half addrspace(1)* %a, half addrspace(1)* %b) #0 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.a = getelementptr inbounds half, half addrspace(1)* %a, i64 %tid.ext
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%a.val = load volatile half, half addrspace(1)* %gep.a
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv arcp half %a.val, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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; GCN-LABEL: {{^}}v_fdiv_f16_unsafe:
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; VI: flat_load_ushort [[LHS:v[0-9]+]]
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; VI: flat_load_ushort [[RHS:v[0-9]+]]
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; VI: v_rcp_f16_e32 [[RCP:v[0-9]+]], [[RHS]]
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; VI: v_mul_f16_e32 [[RESULT:v[0-9]+]], [[RCP]], [[LHS]]
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; VI: flat_store_short v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define void @v_fdiv_f16_unsafe(half addrspace(1)* %r, half addrspace(1)* %a, half addrspace(1)* %b) #2 {
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entry:
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%gep.a = getelementptr inbounds half, half addrspace(1)* %a, i64 %tid.ext
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%gep.b = getelementptr inbounds half, half addrspace(1)* %b, i64 %tid.ext
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%gep.r = getelementptr inbounds half, half addrspace(1)* %r, i64 %tid.ext
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%a.val = load volatile half, half addrspace(1)* %gep.a
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%b.val = load volatile half, half addrspace(1)* %gep.b
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%r.val = fdiv half %a.val, %b.val
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store half %r.val, half addrspace(1)* %gep.r
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare half @llvm.sqrt.f16(half) #1
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declare half @llvm.fabs.f16(half) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "unsafe-fp-math"="true" }
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