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[Sparc] Return true in enableMultipleCopyHints().

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Enable multiple COPY hints to eliminate more COPYs during register allocation.

Note that this is something all targets should do, see
https://reviews.llvm.org/D38128.

Review: James Y Knight
llvm-svn: 326028
This commit is contained in:
Jonas Paulsson 2018-02-24 08:24:31 +00:00
parent 02a56efa23
commit 5ed8793589
4 changed files with 25 additions and 33 deletions
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2
lib/Target/Sparc/SparcRegisterInfo.h
View File

@ -35,6 +35,8 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
unsigned Kind) const override;
bool enableMultipleCopyHints() const override { return true; }
void eliminateFrameIndex(MachineBasicBlock::iterator II,
int SPAdj, unsigned FIOperandNum,
RegScavenger *RS = nullptr) const override;

24
test/CodeGen/SPARC/32abi.ll
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@ -88,36 +88,28 @@ define void @call_intarg(i32 %i0, i8* %i1) {
; SOFT-NEXT: mov %i2, %o0
; SOFT-NEXT: call __extendsfdf2
; SOFT-NEXT: nop
; SOFT-NEXT: mov %o0, %i2
; SOFT-NEXT: mov %o1, %g2
; SOFT-NEXT: mov %o0, %o2
; SOFT-NEXT: mov %o1, %o3
; SOFT-NEXT: mov %i0, %o0
; SOFT-NEXT: mov %i1, %o1
; SOFT-NEXT: mov %i2, %o2
; SOFT-NEXT: mov %g2, %o3
; SOFT-NEXT: call __adddf3
; SOFT-NEXT: nop
; SOFT-NEXT: mov %o0, %i0
; SOFT-NEXT: mov %o1, %i1
; SOFT-NEXT: mov %o0, %o2
; SOFT-NEXT: mov %o1, %o3
; SOFT-NEXT: mov %i3, %o0
; SOFT-NEXT: mov %i4, %o1
; SOFT-NEXT: mov %i0, %o2
; SOFT-NEXT: mov %i1, %o3
; SOFT-NEXT: call __adddf3
; SOFT-NEXT: nop
; SOFT-NEXT: mov %o0, %i0
; SOFT-NEXT: mov %o1, %i1
; SOFT-NEXT: mov %o0, %o2
; SOFT-NEXT: mov %o1, %o3
; SOFT-NEXT: mov %i5, %o0
; SOFT-NEXT: mov %l3, %o1
; SOFT-NEXT: mov %i0, %o2
; SOFT-NEXT: mov %i1, %o3
; SOFT-NEXT: call __adddf3
; SOFT-NEXT: nop
; SOFT-NEXT: mov %o0, %i0
; SOFT-NEXT: mov %o1, %i1
; SOFT-NEXT: mov %o0, %o2
; SOFT-NEXT: mov %o1, %o3
; SOFT-NEXT: mov %l1, %o0
; SOFT-NEXT: mov %l2, %o1
; SOFT-NEXT: mov %i0, %o2
; SOFT-NEXT: mov %i1, %o3
; SOFT-NEXT: call __adddf3
; SOFT-NEXT: nop
; SOFT-NEXT: mov %o0, %i0

19
test/CodeGen/SPARC/64abi.ll
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@ -65,7 +65,7 @@ define void @call_intarg(i32 %i0, i8* %i1) {
; SOFT: save %sp, -176, %sp
; SOFT: srl %i0, 0, %o0
; SOFT-NEXT: call __extendsfdf2
; SOFT: mov %o0, %i0
; SOFT: mov %o0, %o1
; SOFT: mov %i1, %o0
; SOFT: mov %i2, %o0
; SOFT: mov %i3, %o0
@ -145,13 +145,11 @@ define void @call_floatarg(float %f1, double %d2, float %f5, double *%p) {
; HARD: fstod %f3
; HARD: faddd %f6
; HARD: faddd %f16
; SOFT: mov %o0, %i1
; SOFT: mov %o0, %o1
; SOFT-NEXT: mov %i3, %o0
; SOFT-NEXT: mov %i1, %o1
; SOFT-NEXT: call __adddf3
; SOFT: mov %o0, %i1
; SOFT: mov %o0, %o1
; SOFT-NEXT: mov %i0, %o0
; SOFT-NEXT: mov %i1, %o1
; SOFT-NEXT: call __adddf3
; HARD: std %f0, [%i1]
; SOFT: stx %o0, [%i5]
@ -217,8 +215,8 @@ define i32 @inreg_fi(i32 inreg %a0, ; high bits of %i0
; CHECK-LABEL: call_inreg_fi:
; Allocate space for 6 arguments, even when only 2 are used.
; CHECK: save %sp, -176, %sp
; HARD: sllx %i1, 32, %o0
; HARD: fmovs %f5, %f1
; HARD-DAG: sllx %i1, 32, %o0
; HARD-DAG: fmovs %f5, %f1
; SOFT: srl %i2, 0, %i0
; SOFT: sllx %i1, 32, %i1
; SOFT: or %i1, %i0, %o0
@ -240,8 +238,8 @@ define float @inreg_ff(float inreg %a0, ; %f0
}
; CHECK-LABEL: call_inreg_ff:
; HARD: fmovs %f3, %f0
; HARD: fmovs %f5, %f1
; HARD-DAG: fmovs %f3, %f0
; HARD-DAG: fmovs %f5, %f1
; SOFT: srl %i2, 0, %i0
; SOFT: sllx %i1, 32, %i1
; SOFT: or %i1, %i0, %o0
@ -527,9 +525,8 @@ entry:
; CHECK: call sinf
; HARD: ld [%fp+[[Offset1]]], %f1
; HARD: fmuls %f1, %f0, %f0
; SOFT: mov %o0, %i0
; SOFT: mov %o0, %o1
; SOFT: mov %i1, %o0
; SOFT: mov %i0, %o1
; SOFT: call __mulsf3
; SOFT: sllx %o0, 32, %i0

13
test/CodeGen/SPARC/64cond.ll
View File

@ -67,9 +67,10 @@ entry:
}
; CHECK: selecti64_fcc
; CHECK: mov %i3, %i0
; CHECK: fcmps %f1, %f3
; CHECK: movul %fcc0, %i2, %i3
; CHECK: restore %g0, %i3, %o0
; CHECK: movul %fcc0, %i2, %i0
; CHECK: restore
define i64 @selecti64_fcc(float %x, float %y, i64 %a, i64 %b) {
entry:
%tobool = fcmp ult float %x, %y
@ -78,9 +79,9 @@ entry:
}
; CHECK: selectf32_xcc
; CHECK: cmp %i0, %i1
; CHECK: fmovsg %xcc, %f5, %f7
; CHECK: fmovs %f7, %f0
; CHECK: cmp %i0, %i1
; CHECK: fmovsg %xcc, %f5, %f0
define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
entry:
%tobool = icmp sgt i64 %x, %y
@ -89,9 +90,9 @@ entry:
}
; CHECK: selectf64_xcc
; CHECK: cmp %i0, %i1
; CHECK: fmovdg %xcc, %f4, %f6
; CHECK: fmovd %f6, %f0
; CHECK: cmp %i0, %i1
; CHECK: fmovdg %xcc, %f4, %f0
define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
entry:
%tobool = icmp sgt i64 %x, %y