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[MIPS GlobalISel] NarrowScalar G_ZEXT and G_SEXT
NarrowScalar G_ZEXT and G_SEXT to s32 for MIPS32. Differential Revision: https://reviews.llvm.org/D66204 llvm-svn: 369511
This commit is contained in:
Petar Avramovic
parent
4e0138bea0
commit
5f102eeffc
@ -54,6 +54,10 @@ MipsLegalizerInfo::MipsLegalizerInfo(const MipsSubtarget &ST) {
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{s32, p0, 16, 8}})
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.minScalar(0, s32);
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getActionDefinitionsBuilder({G_ZEXT, G_SEXT})
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.legalIf([](const LegalityQuery &Query) { return false; })
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.maxScalar(0, s32);
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getActionDefinitionsBuilder(G_TRUNC)
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.legalIf([](const LegalityQuery &Query) { return false; })
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.maxScalar(1, s32);
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61
test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
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61
test/CodeGen/Mips/GlobalISel/legalizer/zext_and_sext.mir
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@ -0,0 +1,61 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @zext() {entry: ret void}
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define void @sext() {entry: ret void}
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...
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---
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name: zext
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: zext
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[C]](s32)
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; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
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; MIPS32: $v0 = COPY [[UV]](s32)
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; MIPS32: $v1 = COPY [[UV1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(s32) = COPY $a0
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%1:_(s64) = G_ZEXT %0(s32)
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%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
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$v0 = COPY %2(s32)
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$v1 = COPY %3(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: sext
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alignment: 2
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: sext
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:_(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
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; MIPS32: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
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; MIPS32: [[COPY1:%[0-9]+]]:_(s32) = COPY [[C]](s32)
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; MIPS32: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
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; MIPS32: [[MV:%[0-9]+]]:_(s64) = G_MERGE_VALUES [[COPY]](s32), [[ASHR]](s32)
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; MIPS32: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[MV]](s64)
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; MIPS32: $v0 = COPY [[UV]](s32)
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; MIPS32: $v1 = COPY [[UV1]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(s32) = COPY $a0
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%1:_(s64) = G_SEXT %0(s32)
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%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
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$v0 = COPY %2(s32)
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$v1 = COPY %3(s32)
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RetRA implicit $v0, implicit $v1
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...
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27
test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
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27
test/CodeGen/Mips/GlobalISel/llvm-ir/zext_and_sext.ll
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@ -0,0 +1,27 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O0 -mtriple=mipsel-linux-gnu -global-isel -verify-machineinstrs %s -o -| FileCheck %s -check-prefixes=MIPS32
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define i64 @zext(i32 %x) {
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; MIPS32-LABEL: zext:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: ori $3, $zero, 0
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; MIPS32-NEXT: move $2, $4
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = zext i32 %x to i64
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ret i64 %conv
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}
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define i64 @sext(i32 %x) {
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; MIPS32-LABEL: sext:
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; MIPS32: # %bb.0: # %entry
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; MIPS32-NEXT: ori $1, $zero, 31
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; MIPS32-NEXT: srav $3, $4, $1
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; MIPS32-NEXT: move $2, $4
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; MIPS32-NEXT: jr $ra
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; MIPS32-NEXT: nop
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entry:
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%conv = sext i32 %x to i64
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ret i64 %conv
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}
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64
test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
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64
test/CodeGen/Mips/GlobalISel/regbankselect/zext_and_sext.mir
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@ -0,0 +1,64 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -O0 -mtriple=mipsel-linux-gnu -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s -check-prefixes=MIPS32
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--- |
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define void @zext() {entry: ret void}
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define void @sext() {entry: ret void}
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...
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---
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name: zext
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: zext
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
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; MIPS32: $v0 = COPY [[COPY]](s32)
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; MIPS32: $v1 = COPY [[C]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(s32) = COPY $a0
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%4:_(s32) = G_CONSTANT i32 0
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%1:_(s64) = G_MERGE_VALUES %0(s32), %4(s32)
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%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
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$v0 = COPY %2(s32)
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$v1 = COPY %3(s32)
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RetRA implicit $v0, implicit $v1
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...
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---
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name: sext
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alignment: 2
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legalized: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $a0
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; MIPS32-LABEL: name: sext
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; MIPS32: liveins: $a0
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; MIPS32: [[COPY:%[0-9]+]]:gprb(s32) = COPY $a0
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; MIPS32: [[C:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 31
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; MIPS32: [[C1:%[0-9]+]]:gprb(s32) = G_CONSTANT i32 0
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; MIPS32: [[COPY1:%[0-9]+]]:gprb(s32) = COPY [[C]](s32)
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; MIPS32: [[ASHR:%[0-9]+]]:gprb(s32) = G_ASHR [[COPY]], [[COPY1]](s32)
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; MIPS32: $v0 = COPY [[COPY]](s32)
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; MIPS32: $v1 = COPY [[ASHR]](s32)
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; MIPS32: RetRA implicit $v0, implicit $v1
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%0:_(s32) = COPY $a0
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%7:_(s32) = G_CONSTANT i32 31
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%8:_(s32) = G_CONSTANT i32 0
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%6:_(s32) = COPY %7(s32)
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%5:_(s32) = G_ASHR %0, %6(s32)
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%1:_(s64) = G_MERGE_VALUES %0(s32), %5(s32)
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%2:_(s32), %3:_(s32) = G_UNMERGE_VALUES %1(s64)
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$v0 = COPY %2(s32)
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$v1 = COPY %3(s32)
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RetRA implicit $v0, implicit $v1
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...
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