diff --git a/include/llvm/IR/IntrinsicsSystemZ.td b/include/llvm/IR/IntrinsicsSystemZ.td index 9be37d3645b..89136ad9c68 100644 --- a/include/llvm/IR/IntrinsicsSystemZ.td +++ b/include/llvm/IR/IntrinsicsSystemZ.td @@ -373,6 +373,33 @@ let TargetPrefix = "s390" in { def int_s390_vfidb : Intrinsic<[llvm_v2f64_ty], [llvm_v2f64_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; + + // Instructions from the Vector Enhancements Facility 1 + def int_s390_vbperm : SystemZBinaryConv<"vbperm", llvm_v2i64_ty, + llvm_v16i8_ty>; + + def int_s390_vmslg : GCCBuiltin<"__builtin_s390_vmslg">, + Intrinsic<[llvm_v16i8_ty], + [llvm_v2i64_ty, llvm_v2i64_ty, llvm_v16i8_ty, + llvm_i32_ty], [IntrNoMem]>; + + def int_s390_vfmaxdb : Intrinsic<[llvm_v2f64_ty], + [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty], + [IntrNoMem]>; + def int_s390_vfmindb : Intrinsic<[llvm_v2f64_ty], + [llvm_v2f64_ty, llvm_v2f64_ty, llvm_i32_ty], + [IntrNoMem]>; + + // Instructions from the Vector Packed Decimal Facility + def int_s390_vlrl : GCCBuiltin<"__builtin_s390_vlrl">, + Intrinsic<[llvm_v16i8_ty], [llvm_i32_ty, llvm_ptr_ty], + [IntrReadMem, IntrArgMemOnly]>; + + def int_s390_vstrl : GCCBuiltin<"__builtin_s390_vstrl">, + Intrinsic<[], [llvm_v16i8_ty, llvm_i32_ty, llvm_ptr_ty], + // In fact write-only but there's no property + // for that. + [IntrArgMemOnly]>; } //===----------------------------------------------------------------------===// diff --git a/lib/Support/Host.cpp b/lib/Support/Host.cpp index 4318f1d96ec..5cf0316d4d7 100644 --- a/lib/Support/Host.cpp +++ b/lib/Support/Host.cpp @@ -250,6 +250,8 @@ StringRef sys::detail::getHostCPUNameForS390x( Pos += sizeof("machine = ") - 1; unsigned int Id; if (!Lines[I].drop_front(Pos).getAsInteger(10, Id)) { + if (Id >= 3906 && HaveVectorSupport) + return "z14"; if (Id >= 2964 && HaveVectorSupport) return "z13"; if (Id >= 2827) diff --git a/lib/Target/SystemZ/SystemZFeatures.td b/lib/Target/SystemZ/SystemZFeatures.td index c5faa0d6288..ec62ebadd1f 100644 --- a/lib/Target/SystemZ/SystemZFeatures.td +++ b/lib/Target/SystemZ/SystemZFeatures.td @@ -187,6 +187,57 @@ def Arch11NewFeatures : SystemZFeatureList<[ FeatureVector ]>; +//===----------------------------------------------------------------------===// +// +// New features added in the Twelvth Edition of the z/Architecture +// +//===----------------------------------------------------------------------===// + +def FeatureMiscellaneousExtensions2 : SystemZFeature< + "miscellaneous-extensions-2", "MiscellaneousExtensions2", + "Assume that the miscellaneous-extensions facility 2 is installed" +>; + +def FeatureGuardedStorage : SystemZFeature< + "guarded-storage", "GuardedStorage", + "Assume that the guarded-storage facility is installed" +>; + +def FeatureMessageSecurityAssist7 : SystemZFeature< + "message-security-assist-extension7", "MessageSecurityAssist7", + "Assume that the message-security-assist extension facility 7 is installed" +>; + +def FeatureMessageSecurityAssist8 : SystemZFeature< + "message-security-assist-extension8", "MessageSecurityAssist8", + "Assume that the message-security-assist extension facility 8 is installed" +>; + +def FeatureVectorEnhancements1 : SystemZFeature< + "vector-enhancements-1", "VectorEnhancements1", + "Assume that the vector enhancements facility 1 is installed" +>; + +def FeatureVectorPackedDecimal : SystemZFeature< + "vector-packed-decimal", "VectorPackedDecimal", + "Assume that the vector packed decimal facility is installed" +>; + +def FeatureInsertReferenceBitsMultiple : SystemZFeature< + "insert-reference-bits-multiple", "InsertReferenceBitsMultiple", + "Assume that the insert-reference-bits-multiple facility is installed" +>; + +def Arch12NewFeatures : SystemZFeatureList<[ + FeatureMiscellaneousExtensions2, + FeatureGuardedStorage, + FeatureMessageSecurityAssist7, + FeatureMessageSecurityAssist8, + FeatureVectorEnhancements1, + FeatureVectorPackedDecimal, + FeatureInsertReferenceBitsMultiple +]>; + //===----------------------------------------------------------------------===// // // Cumulative supported and unsupported feature sets @@ -201,9 +252,13 @@ def Arch10SupportedFeatures : SystemZFeatureAdd; def Arch11SupportedFeatures : SystemZFeatureAdd; +def Arch12SupportedFeatures + : SystemZFeatureAdd; -def Arch11UnsupportedFeatures +def Arch12UnsupportedFeatures : SystemZFeatureList<[]>; +def Arch11UnsupportedFeatures + : SystemZFeatureAdd; def Arch10UnsupportedFeatures : SystemZFeatureAdd; def Arch9UnsupportedFeatures diff --git a/lib/Target/SystemZ/SystemZISelLowering.cpp b/lib/Target/SystemZ/SystemZISelLowering.cpp index 2801141cd95..40d1f6df820 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -316,7 +316,10 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, setOperationAction(ISD::AND, VT, Legal); setOperationAction(ISD::OR, VT, Legal); setOperationAction(ISD::XOR, VT, Legal); - setOperationAction(ISD::CTPOP, VT, Custom); + if (Subtarget.hasVectorEnhancements1()) + setOperationAction(ISD::CTPOP, VT, Legal); + else + setOperationAction(ISD::CTPOP, VT, Custom); setOperationAction(ISD::CTTZ, VT, Legal); setOperationAction(ISD::CTLZ, VT, Legal); @@ -414,6 +417,19 @@ SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FROUND, MVT::v2f64, Legal); } + // The vector enhancements facility 1 has instructions for these. + if (Subtarget.hasVectorEnhancements1()) { + setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); + setOperationAction(ISD::FMAXNAN, MVT::f64, Legal); + setOperationAction(ISD::FMINNUM, MVT::f64, Legal); + setOperationAction(ISD::FMINNAN, MVT::f64, Legal); + + setOperationAction(ISD::FMAXNUM, MVT::v2f64, Legal); + setOperationAction(ISD::FMAXNAN, MVT::v2f64, Legal); + setOperationAction(ISD::FMINNUM, MVT::v2f64, Legal); + setOperationAction(ISD::FMINNAN, MVT::v2f64, Legal); + } + // We have fused multiply-addition for f32 and f64 but not f128. setOperationAction(ISD::FMA, MVT::f32, Legal); setOperationAction(ISD::FMA, MVT::f64, Legal); @@ -2960,6 +2976,12 @@ SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op, // We define this so that it can be used for constant division. lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]); + else if (Subtarget.hasMiscellaneousExtensions2()) + // SystemZISD::SMUL_LOHI returns the low result in the odd register and + // the high result in the even register. ISD::SMUL_LOHI is defined to + // return the low half first, so the results are in reverse order. + lowerGR128Binary(DAG, DL, VT, SystemZISD::SMUL_LOHI, + Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]); else { // Do a full 128-bit multiplication based on SystemZISD::UMUL_LOHI: // @@ -4658,6 +4680,7 @@ const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const { OPCODE(SELECT_CCMASK); OPCODE(ADJDYNALLOC); OPCODE(POPCNT); + OPCODE(SMUL_LOHI); OPCODE(UMUL_LOHI); OPCODE(SDIVREM); OPCODE(UDIVREM); diff --git a/lib/Target/SystemZ/SystemZISelLowering.h b/lib/Target/SystemZ/SystemZISelLowering.h index 6c9c404816f..0be2721963e 100644 --- a/lib/Target/SystemZ/SystemZISelLowering.h +++ b/lib/Target/SystemZ/SystemZISelLowering.h @@ -88,6 +88,7 @@ enum NodeType : unsigned { // Wrappers around the ISD opcodes of the same name. The output is GR128. // Input operands may be GR64 or GR32, depending on the instruction. + SMUL_LOHI, UMUL_LOHI, SDIVREM, UDIVREM, diff --git a/lib/Target/SystemZ/SystemZInstrFormats.td b/lib/Target/SystemZ/SystemZInstrFormats.td index 7620e06ccbc..f36e58889af 100644 --- a/lib/Target/SystemZ/SystemZInstrFormats.td +++ b/lib/Target/SystemZ/SystemZInstrFormats.td @@ -1091,6 +1091,94 @@ class InstVRIe op, dag outs, dag ins, string asmstr, list pattern> let Inst{7-0} = op{7-0}; } +class InstVRIf op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<5> V3; + bits<8> I4; + bits<4> M5; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V2{3-0}; + let Inst{31-28} = V3{3-0}; + let Inst{27-24} = 0; + let Inst{23-20} = M5; + let Inst{19-12} = I4; + let Inst{11} = V1{4}; + let Inst{10} = V2{4}; + let Inst{9} = V3{4}; + let Inst{8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRIg op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<8> I3; + bits<8> I4; + bits<4> M5; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = V2{3-0}; + let Inst{31-24} = I4; + let Inst{23-20} = M5; + let Inst{19-12} = I3; + let Inst{11} = V1{4}; + let Inst{10} = V2{4}; + let Inst{9-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRIh op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<16> I2; + bits<4> I3; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = 0; + let Inst{31-16} = I2; + let Inst{15-12} = I3; + let Inst{11} = V1{4}; + let Inst{10-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRIi op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<4> R2; + bits<8> I3; + bits<4> M4; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = V1{3-0}; + let Inst{35-32} = R2; + let Inst{31-24} = 0; + let Inst{23-20} = M4; + let Inst{19-12} = I3; + let Inst{11} = V1{4}; + let Inst{10-8} = 0; + let Inst{7-0} = op{7-0}; +} + // Depending on the instruction mnemonic, certain bits may be or-ed into // the M4 value provided as explicit operand. These are passed as m4or. class InstVRRa op, dag outs, dag ins, string asmstr, list pattern, @@ -1259,6 +1347,67 @@ class InstVRRf op, dag outs, dag ins, string asmstr, list pattern> let Inst{7-0} = op{7-0}; } +class InstVRRg op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = 0; + let Inst{35-32} = V1{3-0}; + let Inst{31-12} = 0; + let Inst{11} = 0; + let Inst{10} = V1{4}; + let Inst{9-8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRRh op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<5> V2; + bits<4> M3; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = 0; + let Inst{35-32} = V1{3-0}; + let Inst{31-28} = V2{3-0}; + let Inst{27-24} = 0; + let Inst{23-20} = M3; + let Inst{19-12} = 0; + let Inst{11} = 0; + let Inst{10} = V1{4}; + let Inst{9} = V2{4}; + let Inst{8} = 0; + let Inst{7-0} = op{7-0}; +} + +class InstVRRi op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<4> R1; + bits<5> V2; + bits<4> M3; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = R1; + let Inst{35-32} = V2{3-0}; + let Inst{31-24} = 0; + let Inst{23-20} = M3; + let Inst{19-12} = 0; + let Inst{11} = 0; + let Inst{10} = V2{4}; + let Inst{9-8} = 0; + let Inst{7-0} = op{7-0}; +} + class InstVRSa op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; @@ -1321,6 +1470,25 @@ class InstVRSc op, dag outs, dag ins, string asmstr, list pattern> let Inst{7-0} = op{7-0}; } +class InstVRSd op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<16> BD2; + bits<4> R3; + + let Inst{47-40} = op{15-8}; + let Inst{39-36} = 0; + let Inst{35-32} = R3; + let Inst{31-16} = BD2; + let Inst{15-12} = V1{3-0}; + let Inst{11-9} = 0; + let Inst{8} = V1{4}; + let Inst{7-0} = op{7-0}; +} + class InstVRV op, dag outs, dag ins, string asmstr, list pattern> : InstSystemZ<6, outs, ins, asmstr, pattern> { field bits<48> Inst; @@ -1358,6 +1526,24 @@ class InstVRX op, dag outs, dag ins, string asmstr, list pattern> let Inst{7-0} = op{7-0}; } +class InstVSI op, dag outs, dag ins, string asmstr, list pattern> + : InstSystemZ<6, outs, ins, asmstr, pattern> { + field bits<48> Inst; + field bits<48> SoftFail = 0; + + bits<5> V1; + bits<16> BD2; + bits<8> I3; + + let Inst{47-40} = op{15-8}; + let Inst{39-32} = I3; + let Inst{31-16} = BD2; + let Inst{15-12} = V1{3-0}; + let Inst{11-9} = 0; + let Inst{8} = V1{4}; + let Inst{7-0} = op{7-0}; +} + //===----------------------------------------------------------------------===// // Instruction classes for .insn directives //===----------------------------------------------------------------------===// @@ -1910,6 +2096,25 @@ class FixedCondBranchRX opcode> let M1 = V.ccmask; } +class CondBranchRXY opcode> + : InstRXYb { + let CCMaskFirst = 1; +} + +class AsmCondBranchRXY opcode> + : InstRXYb; + +class FixedCondBranchRXY opcode, + SDPatternOperator operator = null_frag> + : InstRXYb { + let isAsmParserOnly = V.alternate; + let M1 = V.ccmask; +} + class CmpBranchRIEa opcode, RegisterOperand cls, Immediate imm> : InstRIEa opcode, let AccessBytes = bytes; } +class StoreLengthVRSd opcode, + SDPatternOperator operator, bits<5> bytes> + : InstVRSd { + let mayStore = 1; + let AccessBytes = bytes; +} + +class StoreLengthVSI opcode, + SDPatternOperator operator, bits<5> bytes> + : InstVSI { + let mayStore = 1; + let AccessBytes = bytes; +} + class StoreMultipleRS opcode, RegisterOperand cls, AddressingMode mode = bdaddr12only> : InstRSa opcode, : InstRXa; +class SideEffectBinaryRXY opcode, + RegisterOperand cls> + : InstRXYa; + class SideEffectBinaryRILPC opcode, RegisterOperand cls> : InstRILb opcode> (ins VR128:$V2, imm32zx12:$I3, imm32zx4:$M4, imm32zx4:$M5), mnemonic#"\t$V1, $V2, $I3, $M4, $M5", []>; +class BinaryVRIh opcode> + : InstVRIh; + class BinaryVRRa opcode, SDPatternOperator operator, TypedReg tr1, TypedReg tr2, bits<4> type = 0, bits<4> m4 = 0> : InstVRRa opcode, SDPatternOperator operator, mnemonic#"\t$V1, $R2, $R3", [(set tr.op:$V1, (tr.vt (operator GR64:$R2, GR64:$R3)))]>; +class BinaryVRRi opcode, RegisterOperand cls> + : InstVRRi; + class BinaryVRSa opcode, SDPatternOperator operator, TypedReg tr1, TypedReg tr2, bits<4> type> : InstVRSa opcode> (ins VR128:$V3, shift12only:$BD2, imm32zx4: $M4), mnemonic#"\t$R1, $V3, $BD2, $M4", []>; +class BinaryVRSd opcode, SDPatternOperator operator, + bits<5> bytes> + : InstVRSd { + let mayLoad = 1; + let AccessBytes = bytes; +} + class BinaryVRX opcode, SDPatternOperator operator, TypedReg tr, bits<5> bytes> : InstVRX opcode, RegisterOperand cls> let mayStore = 1; } +class BinaryVSI opcode, SDPatternOperator operator, + bits<5> bytes> + : InstVSI { + let mayLoad = 1; + let AccessBytes = bytes; +} + class StoreBinaryVRV opcode, bits<5> bytes, Immediate index> : InstVRV opcode> let M5 = 0; } +class CompareVRRh opcode> + : InstVRRh { + let isCompare = 1; +} + class TestRXE opcode, SDPatternOperator operator, RegisterOperand cls> : InstRXE opcode> let mayLoad = 1; } +class TestVRRg opcode> + : InstVRRg; + class SideEffectTernarySSc opcode> : InstSSc opcode, SDPatternOperator operator, let M5 = type; } +class TernaryVRIi opcode, RegisterOperand cls> + : InstVRIi; + class TernaryVRRa opcode, SDPatternOperator operator, TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> m4or> : InstVRRa opcode, SDPatternOperator operator, let M6 = 0; } +class TernaryVRRcFloat opcode, + SDPatternOperator operator, TypedReg tr1, TypedReg tr2, + bits<4> type = 0, bits<4> m5 = 0> + : InstVRRc { + let M4 = type; + let M5 = m5; +} + +class TernaryVRRcFloatGeneric opcode> + : InstVRRc; + class TernaryVRRd opcode, SDPatternOperator operator, TypedReg tr1, TypedReg tr2, bits<4> type = 0> : InstVRRd opcode> let DisableEncoding = "$V1src"; } +class QuaternaryVRIf opcode> + : InstVRIf; + +class QuaternaryVRIg opcode> + : InstVRIg; + class QuaternaryVRRd opcode, SDPatternOperator operator, TypedReg tr1, TypedReg tr2, - bits<4> type, SDPatternOperator m6mask, bits<4> m6or> + TypedReg tr3, TypedReg tr4, bits<4> type, + SDPatternOperator m6mask = imm32zx4, bits<4> m6or = 0> : InstVRRd { let M5 = type; } +class QuaternaryVRRdGeneric opcode> + : InstVRRd; + // Declare a pair of instructions, one which sets CC and one which doesn't. // The CC-setting form ends with "S" and sets the low bit of M6. // Also create aliases to make use of M6 operand optional in assembler. @@ -4041,13 +4348,15 @@ multiclass QuaternaryOptVRRdSPair opcode, SDPatternOperator operator_cc, TypedReg tr1, TypedReg tr2, bits<4> type, bits<4> modifier = 0> { - def "" : QuaternaryVRRd; def : InstAlias(NAME) tr1.op:$V1, tr2.op:$V2, tr2.op:$V3, tr2.op:$V4, 0)>; let Defs = [CC] in - def S : QuaternaryVRRd; def : InstAlias(NAME#"S") tr1.op:$V1, tr2.op:$V2, @@ -4055,10 +4364,7 @@ multiclass QuaternaryOptVRRdSPair opcode, } multiclass QuaternaryOptVRRdSPairGeneric opcode> { - def "" : InstVRRd; + def "" : QuaternaryVRRdGeneric; def : InstAlias(NAME) VR128:$V1, VR128:$V2, VR128:$V3, VR128:$V4, imm32zx4:$M5, 0)>; diff --git a/lib/Target/SystemZ/SystemZInstrInfo.cpp b/lib/Target/SystemZ/SystemZInstrInfo.cpp index 66a5ff12be4..eaa694bee5e 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -1434,6 +1434,7 @@ SystemZII::Branch SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const { switch (MI.getOpcode()) { case SystemZ::BR: + case SystemZ::BI: case SystemZ::J: case SystemZ::JG: return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY, diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 4569be7602e..46a71731a90 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -48,6 +48,8 @@ let isBranch = 1, isTerminator = 1, Uses = [CC] in { let isIndirectBranch = 1 in { def BC : CondBranchRX<"b#", 0x47>; def BCR : CondBranchRR<"b#r", 0x07>; + def BIC : CondBranchRXY<"bi#", 0xe347>, + Requires<[FeatureMiscellaneousExtensions2]>; } } @@ -58,6 +60,8 @@ let isBranch = 1, isTerminator = 1, Uses = [CC] in { let isIndirectBranch = 1 in { def BCAsm : AsmCondBranchRX<"bc", 0x47>; def BCRAsm : AsmCondBranchRR<"bcr", 0x07>; + def BICAsm : AsmCondBranchRXY<"bic", 0xe347>, + Requires<[FeatureMiscellaneousExtensions2]>; } // Define AsmParser extended mnemonics for each general condition-code mask @@ -69,6 +73,8 @@ let isBranch = 1, isTerminator = 1, Uses = [CC] in { let isIndirectBranch = 1 in { def BAsm#V : FixedCondBranchRX , "b#", 0x47>; def BRAsm#V : FixedCondBranchRR , "b#r", 0x07>; + def BIAsm#V : FixedCondBranchRXY, "bi#", 0xe347>, + Requires<[FeatureMiscellaneousExtensions2]>; } } } @@ -81,6 +87,8 @@ let isBranch = 1, isTerminator = 1, isBarrier = 1 in { let isIndirectBranch = 1 in { def B : FixedCondBranchRX; def BR : FixedCondBranchRR; + def BI : FixedCondBranchRXY, + Requires<[FeatureMiscellaneousExtensions2]>; } } @@ -921,6 +929,8 @@ let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { // Addition of memory. defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, asextloadi16, 2>; defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>; + def AGH : BinaryRXY<"agh", 0xE338, add, GR64, asextloadi16, 2>, + Requires<[FeatureMiscellaneousExtensions2]>; def AGF : BinaryRXY<"agf", 0xE318, add, GR64, asextloadi32, 4>; def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>; @@ -1006,6 +1016,8 @@ let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0x8 in { // Subtraction of memory. defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, asextloadi16, 2>; defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>; + def SGH : BinaryRXY<"sgh", 0xE339, sub, GR64, asextloadi16, 2>, + Requires<[FeatureMiscellaneousExtensions2]>; def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, asextloadi32, 4>; def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>; } @@ -1207,6 +1219,15 @@ defm : RMWIByte; // Multiplication //===----------------------------------------------------------------------===// +// Multiplication of a register, setting the condition code. We prefer these +// over MS(G)R if available, even though we cannot use the condition code, +// since they are three-operand instructions. +let Predicates = [FeatureMiscellaneousExtensions2], + Defs = [CC], isCommutable = 1 in { + def MSRKC : BinaryRRFa<"msrkc", 0xB9FD, mul, GR32, GR32, GR32>; + def MSGRKC : BinaryRRFa<"msgrkc", 0xB9ED, mul, GR64, GR64, GR64>; +} + // Multiplication of a register. let isCommutable = 1 in { def MSR : BinaryRRE<"msr", 0xB252, mul, GR32, GR32>; @@ -1226,21 +1247,37 @@ def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>; // Multiplication of memory. defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, asextloadi16, 2>; defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>; +def MGH : BinaryRXY<"mgh", 0xE33C, mul, GR64, asextloadi16, 2>, + Requires<[FeatureMiscellaneousExtensions2]>; def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, asextloadi32, 4>; def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>; +// Multiplication of memory, setting the condition code. +let Predicates = [FeatureMiscellaneousExtensions2], Defs = [CC] in { + def MSC : BinaryRXY<"msc", 0xE353, null_frag, GR32, load, 4>; + def MSGC : BinaryRXY<"msgc", 0xE383, null_frag, GR64, load, 8>; +} + // Multiplication of a register, producing two results. -def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; +def MR : BinaryRR <"mr", 0x1C, null_frag, GR128, GR32>; +def MGRK : BinaryRRFa<"mgrk", 0xB9EC, null_frag, GR128, GR64, GR64>, + Requires<[FeatureMiscellaneousExtensions2]>; def MLR : BinaryRRE<"mlr", 0xB996, null_frag, GR128, GR32>; def MLGR : BinaryRRE<"mlgr", 0xB986, null_frag, GR128, GR64>; +def : Pat<(z_smul_lohi GR64:$src1, GR64:$src2), + (MGRK GR64:$src1, GR64:$src2)>; def : Pat<(z_umul_lohi GR64:$src1, GR64:$src2), (MLGR (AEXT128 GR64:$src1), GR64:$src2)>; // Multiplication of memory, producing two results. def M : BinaryRX <"m", 0x5C, null_frag, GR128, load, 4>; def MFY : BinaryRXY<"mfy", 0xE35C, null_frag, GR128, load, 4>; +def MG : BinaryRXY<"mg", 0xE384, null_frag, GR128, load, 8>, + Requires<[FeatureMiscellaneousExtensions2]>; def ML : BinaryRXY<"ml", 0xE396, null_frag, GR128, load, 4>; def MLG : BinaryRXY<"mlg", 0xE386, null_frag, GR128, load, 8>; +def : Pat<(z_smul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), + (MG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; def : Pat<(z_umul_lohi GR64:$src1, (i64 (load bdxaddr20only:$src2))), (MLG (AEXT128 GR64:$src1), bdxaddr20only:$src2)>; @@ -1765,8 +1802,29 @@ let mayLoad = 1, mayStore = 1, Uses = [R0L, R1D], Defs = [CC] in { GR128, GR128, GR128>; def PCC : SideEffectInherentRRE<"pcc", 0xB92C>; } + let Predicates = [FeatureMessageSecurityAssist5] in - def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; + def PPNO : SideEffectBinaryMemMemRRE<"ppno", 0xB93C, GR128, GR128>; + let Predicates = [FeatureMessageSecurityAssist7], isAsmParserOnly = 1 in + def PRNO : SideEffectBinaryMemMemRRE<"prno", 0xB93C, GR128, GR128>; + + let Predicates = [FeatureMessageSecurityAssist8] in + def KMA : SideEffectTernaryMemMemMemRRFb<"kma", 0xB929, + GR128, GR128, GR128>; +} + +//===----------------------------------------------------------------------===// +// Guarded storage +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureGuardedStorage] in { + def LGG : UnaryRXY<"lgg", 0xE34C, null_frag, GR64, 8>; + def LLGFSG : UnaryRXY<"llgfsg", 0xE348, null_frag, GR64, 4>; + + let mayLoad = 1 in + def LGSC : SideEffectBinaryRXY<"lgsc", 0xE34D, GR64>; + let mayStore = 1 in + def STGSC : SideEffectBinaryRXY<"stgsc", 0xE349, GR64>; } //===----------------------------------------------------------------------===// diff --git a/lib/Target/SystemZ/SystemZInstrSystem.td b/lib/Target/SystemZ/SystemZInstrSystem.td index a9803c2d83e..0112ebf1eb1 100644 --- a/lib/Target/SystemZ/SystemZInstrSystem.td +++ b/lib/Target/SystemZ/SystemZInstrSystem.td @@ -126,6 +126,10 @@ let hasSideEffects = 1, Defs = [CC] in let Predicates = [FeatureResetReferenceBitsMultiple], hasSideEffects = 1 in def RRBM : UnaryRRE<"rrbm", 0xB9AE, null_frag, GR64, GR64>; +// Insert reference bits multiple. +let Predicates = [FeatureInsertReferenceBitsMultiple], hasSideEffects = 1 in + def IRBM : UnaryRRE<"irbm", 0xB9AC, null_frag, GR64, GR64>; + // Perform frame management function. let hasSideEffects = 1 in def PFMF : SideEffectBinaryMemRRE<"pfmf", 0xB9AF, GR32, GR64>; diff --git a/lib/Target/SystemZ/SystemZInstrVector.td b/lib/Target/SystemZ/SystemZInstrVector.td index 0158fe6aec0..3d76974cc4f 100644 --- a/lib/Target/SystemZ/SystemZInstrVector.td +++ b/lib/Target/SystemZ/SystemZInstrVector.td @@ -154,6 +154,11 @@ let Predicates = [FeatureVector] in { (VLLEZF bdxaddr12only:$addr)>; def : Pat<(v2f64 (z_vllezf64 bdxaddr12only:$addr)), (VLLEZG bdxaddr12only:$addr)>; + let Predicates = [FeatureVectorEnhancements1] in { + def VLLEZLF : UnaryVRX<"vllezlf", 0xE704, z_vllezli32, v128f, 4, 6>; + def : Pat<(v4f32 (z_vllezlf32 bdxaddr12only:$addr)), + (VLLEZLF bdxaddr12only:$addr)>; + } // Load element. def VLEB : TernaryVRX<"vleb", 0xE700, z_vlei8, v128b, v128b, 1, imm32zx4>; @@ -170,6 +175,13 @@ let Predicates = [FeatureVector] in { def VGEG : TernaryVRV<"vgeg", 0xE712, 8, imm32zx1>; } +let Predicates = [FeatureVectorPackedDecimal] in { + // Load rightmost with length. The number of loaded bytes is only known + // at run time. + def VLRL : BinaryVSI<"vlrl", 0xE635, int_s390_vlrl, 0>; + def VLRLR : BinaryVRSd<"vlrlr", 0xE637, int_s390_vlrl, 0>; +} + // Use replicating loads if we're inserting a single element into an // undefined vector. This avoids a false dependency on the previous // register contents. @@ -227,6 +239,13 @@ let Predicates = [FeatureVector] in { def VSCEG : StoreBinaryVRV<"vsceg", 0xE71A, 8, imm32zx1>; } +let Predicates = [FeatureVectorPackedDecimal] in { + // Store rightmost with length. The number of stored bytes is only known + // at run time. + def VSTRL : StoreLengthVSI<"vstrl", 0xE63D, int_s390_vstrl, 0>; + def VSTRLR : StoreLengthVRSd<"vstrlr", 0xE63F, int_s390_vstrl, 0>; +} + //===----------------------------------------------------------------------===// // Selects and permutes //===----------------------------------------------------------------------===// @@ -256,6 +275,10 @@ let Predicates = [FeatureVector] in { // Permute doubleword immediate. def VPDI : TernaryVRRc<"vpdi", 0xE784, z_permute_dwords, v128g, v128g>; + // Bit Permute. + let Predicates = [FeatureVectorEnhancements1] in + def VBPERM : BinaryVRRc<"vbperm", 0xE785, int_s390_vbperm, v128g, v128b>; + // Replicate. def VREP: BinaryVRIcGeneric<"vrep", 0xE74D>; def VREPB : BinaryVRIc<"vrepb", 0xE74D, z_splat, v128b, v128b, 0>; @@ -424,6 +447,10 @@ let Predicates = [FeatureVector] in { def VCTZF : UnaryVRRa<"vctzf", 0xE752, cttz, v128f, v128f, 2>; def VCTZG : UnaryVRRa<"vctzg", 0xE752, cttz, v128g, v128g, 3>; + // Not exclusive or. + let Predicates = [FeatureVectorEnhancements1] in + def VNX : BinaryVRRc<"vnx", 0xE76C, null_frag, v128any, v128any>; + // Exclusive or. def VX : BinaryVRRc<"vx", 0xE76D, null_frag, v128any, v128any>; @@ -567,6 +594,17 @@ let Predicates = [FeatureVector] in { def VMLOH : BinaryVRRc<"vmloh", 0xE7A5, int_s390_vmloh, v128f, v128h, 1>; def VMLOF : BinaryVRRc<"vmlof", 0xE7A5, int_s390_vmlof, v128g, v128f, 2>; + // Multiply sum logical. + let Predicates = [FeatureVectorEnhancements1] in { + def VMSL : QuaternaryVRRdGeneric<"vmsl", 0xE7B8>; + def VMSLG : QuaternaryVRRd<"vmslg", 0xE7B8, int_s390_vmslg, + v128q, v128g, v128g, v128q, 3>; + } + + // Nand. + let Predicates = [FeatureVectorEnhancements1] in + def VNN : BinaryVRRc<"vnn", 0xE76E, null_frag, v128any, v128any>; + // Nor. def VNO : BinaryVRRc<"vno", 0xE76B, null_frag, v128any, v128any>; def : InstAlias<"vnot\t$V1, $V2", (VNO VR128:$V1, VR128:$V2, VR128:$V2), 0>; @@ -574,9 +612,19 @@ let Predicates = [FeatureVector] in { // Or. def VO : BinaryVRRc<"vo", 0xE76A, null_frag, v128any, v128any>; + // Or with complement. + let Predicates = [FeatureVectorEnhancements1] in + def VOC : BinaryVRRc<"voc", 0xE76F, null_frag, v128any, v128any>; + // Population count. def VPOPCT : UnaryVRRaGeneric<"vpopct", 0xE750>; def : Pat<(v16i8 (z_popcnt VR128:$x)), (VPOPCT VR128:$x, 0)>; + let Predicates = [FeatureVectorEnhancements1] in { + def VPOPCTB : UnaryVRRa<"vpopctb", 0xE750, ctpop, v128b, v128b, 0>; + def VPOPCTH : UnaryVRRa<"vpopcth", 0xE750, ctpop, v128h, v128h, 1>; + def VPOPCTF : UnaryVRRa<"vpopctf", 0xE750, ctpop, v128f, v128f, 2>; + def VPOPCTG : UnaryVRRa<"vpopctg", 0xE750, ctpop, v128g, v128g, 3>; + } // Element rotate left logical (with vector shift amount). def VERLLV : BinaryVRRcGeneric<"verllv", 0xE773>; @@ -724,6 +772,14 @@ multiclass BitwiseVectorOps { (VNO VR128:$x, VR128:$y)>; def : Pat<(type (z_vnot VR128:$x)), (VNO VR128:$x, VR128:$x)>; } + let Predicates = [FeatureVectorEnhancements1] in { + def : Pat<(type (z_vnot (xor VR128:$x, VR128:$y))), + (VNX VR128:$x, VR128:$y)>; + def : Pat<(type (z_vnot (and VR128:$x, VR128:$y))), + (VNN VR128:$x, VR128:$y)>; + def : Pat<(type (or VR128:$x, (z_vnot VR128:$y))), + (VOC VR128:$x, VR128:$y)>; + } } defm : BitwiseVectorOps; @@ -930,6 +986,36 @@ let Predicates = [FeatureVector] in { def : Pat<(v4f32 (z_vround (v2f64 VR128:$src))), (VLEDB VR128:$src, 0, 0)>; def : FPConversion; + // Maximum. + multiclass VectorMax { + def : FPMinMax; + def : FPMinMax; + } + let Predicates = [FeatureVectorEnhancements1] in { + def VFMAX : TernaryVRRcFloatGeneric<"vfmax", 0xE7EF>; + def VFMAXDB : TernaryVRRcFloat<"vfmaxdb", 0xE7EF, int_s390_vfmaxdb, + v128db, v128db, 3, 0>; + def WFMAXDB : TernaryVRRcFloat<"wfmaxdb", 0xE7EF, null_frag, + v64db, v64db, 3, 8>; + defm : VectorMax; + defm : VectorMax; + } + + // Minimum. + multiclass VectorMin { + def : FPMinMax; + def : FPMinMax; + } + let Predicates = [FeatureVectorEnhancements1] in { + def VFMIN : TernaryVRRcFloatGeneric<"vfmin", 0xE7EE>; + def VFMINDB : TernaryVRRcFloat<"vfmindb", 0xE7EE, int_s390_vfmindb, + v128db, v128db, 3, 0>; + def WFMINDB : TernaryVRRcFloat<"wfmindb", 0xE7EE, null_frag, + v64db, v64db, 3, 8>; + defm : VectorMin; + defm : VectorMin; + } + // Multiply. def VFM : BinaryVRRcFloatGeneric<"vfm", 0xE7E7>; def VFMDB : BinaryVRRc<"vfmdb", 0xE7E7, fmul, v128db, v128db, 3, 0>; @@ -945,6 +1031,20 @@ let Predicates = [FeatureVector] in { def VFMSDB : TernaryVRRe<"vfmsdb", 0xE78E, fms, v128db, v128db, 0, 3>; def WFMSDB : TernaryVRRe<"wfmsdb", 0xE78E, fms, v64db, v64db, 8, 3>; + // Negative multiply and add. + let Predicates = [FeatureVectorEnhancements1] in { + def VFNMA : TernaryVRReFloatGeneric<"vfnma", 0xE79F>; + def VFNMADB : TernaryVRRe<"vfnmadb", 0xE79F, fnma, v128db, v128db, 0, 3>; + def WFNMADB : TernaryVRRe<"wfnmadb", 0xE79F, fnma, v64db, v64db, 8, 3>; + } + + // Negative multiply and subtract. + let Predicates = [FeatureVectorEnhancements1] in { + def VFNMS : TernaryVRReFloatGeneric<"vfnms", 0xE79E>; + def VFNMSDB : TernaryVRRe<"vfnmsdb", 0xE79E, fnms, v128db, v128db, 0, 3>; + def WFNMSDB : TernaryVRRe<"wfnmsdb", 0xE79E, fnms, v64db, v64db, 8, 3>; + } + // Perform sign operation. def VFPSO : BinaryVRRaFloatGeneric<"vfpso", 0xE7CC>; def VFPSODB : BinaryVRRa<"vfpsodb", 0xE7CC, null_frag, v128db, v128db, 3, 0>; @@ -1004,6 +1104,14 @@ let Predicates = [FeatureVector] in { defm WFCEDB : BinaryVRRcSPair<"wfcedb", 0xE7E8, null_frag, null_frag, v64g, v64db, 3, 8>; + // Compare and signal equal. + let Predicates = [FeatureVectorEnhancements1] in { + defm VFKEDB : BinaryVRRcSPair<"vfkedb", 0xE7E8, null_frag, null_frag, + v128g, v128db, 3, 4>; + defm WFKEDB : BinaryVRRcSPair<"wfkedb", 0xE7E8, null_frag, null_frag, + v64g, v64db, 3, 12>; + } + // Compare high. def VFCH : BinaryVRRcSPairFloatGeneric<"vfch", 0xE7EB>; defm VFCHDB : BinaryVRRcSPair<"vfchdb", 0xE7EB, z_vfcmph, z_vfcmphs, @@ -1011,12 +1119,28 @@ let Predicates = [FeatureVector] in { defm WFCHDB : BinaryVRRcSPair<"wfchdb", 0xE7EB, null_frag, null_frag, v64g, v64db, 3, 8>; + // Compare and signal high. + let Predicates = [FeatureVectorEnhancements1] in { + defm VFKHDB : BinaryVRRcSPair<"vfkhdb", 0xE7EB, null_frag, null_frag, + v128g, v128db, 3, 4>; + defm WFKHDB : BinaryVRRcSPair<"wfkhdb", 0xE7EB, null_frag, null_frag, + v64g, v64db, 3, 12>; + } + // Compare high or equal. def VFCHE : BinaryVRRcSPairFloatGeneric<"vfche", 0xE7EA>; defm VFCHEDB : BinaryVRRcSPair<"vfchedb", 0xE7EA, z_vfcmphe, z_vfcmphes, v128g, v128db, 3, 0>; defm WFCHEDB : BinaryVRRcSPair<"wfchedb", 0xE7EA, null_frag, null_frag, v64g, v64db, 3, 8>; + + // Compare and signal high or equal. + let Predicates = [FeatureVectorEnhancements1] in { + defm VFKHEDB : BinaryVRRcSPair<"vfkhedb", 0xE7EA, null_frag, null_frag, + v128g, v128db, 3, 4>; + defm WFKHEDB : BinaryVRRcSPair<"wfkhedb", 0xE7EA, null_frag, null_frag, + v64g, v64db, 3, 12>; + } } //===----------------------------------------------------------------------===// @@ -1202,3 +1326,37 @@ let Predicates = [FeatureVector] in { defm VSTRCZF : QuaternaryOptVRRdSPair<"vstrczf", 0xE78A, int_s390_vstrczf, z_vstrcz_cc, v128f, v128f, 2, 2>; } + +//===----------------------------------------------------------------------===// +// Packed-decimal instructions +//===----------------------------------------------------------------------===// + +let Predicates = [FeatureVectorPackedDecimal] in { + def VLIP : BinaryVRIh<"vlip", 0xE649>; + + def VPKZ : BinaryVSI<"vpkz", 0xE634, null_frag, 0>; + def VUPKZ : StoreLengthVSI<"vupkz", 0xE63C, null_frag, 0>; + + let Defs = [CC] in { + def VCVB : BinaryVRRi<"vcvb", 0xE650, GR32>; + def VCVBG : BinaryVRRi<"vcvbg", 0xE652, GR64>; + def VCVD : TernaryVRIi<"vcvd", 0xE658, GR32>; + def VCVDG : TernaryVRIi<"vcvdg", 0xE65A, GR64>; + + def VAP : QuaternaryVRIf<"vap", 0xE671>; + def VSP : QuaternaryVRIf<"vsp", 0xE673>; + + def VMP : QuaternaryVRIf<"vmp", 0xE678>; + def VMSP : QuaternaryVRIf<"vmsp", 0xE679>; + + def VDP : QuaternaryVRIf<"vdp", 0xE67A>; + def VRP : QuaternaryVRIf<"vrp", 0xE67B>; + def VSDP : QuaternaryVRIf<"vsdp", 0xE67E>; + + def VSRP : QuaternaryVRIg<"vsrp", 0xE659>; + def VPSOP : QuaternaryVRIg<"vpsop", 0xE65B>; + + def VTP : TestVRRg<"vtp", 0xE65F>; + def VCP : CompareVRRh<"vcp", 0xE677>; + } +} diff --git a/lib/Target/SystemZ/SystemZOperators.td b/lib/Target/SystemZ/SystemZOperators.td index 9c6d5819f8a..759a8bb0ce1 100644 --- a/lib/Target/SystemZ/SystemZOperators.td +++ b/lib/Target/SystemZ/SystemZOperators.td @@ -181,6 +181,7 @@ def z_select_ccmask : SDNode<"SystemZISD::SELECT_CCMASK", SDT_ZSelectCCMask, [SDNPInGlue]>; def z_adjdynalloc : SDNode<"SystemZISD::ADJDYNALLOC", SDT_ZAdjDynAlloc>; def z_popcnt : SDNode<"SystemZISD::POPCNT", SDTIntUnaryOp>; +def z_smul_lohi : SDNode<"SystemZISD::SMUL_LOHI", SDT_ZGR128Binary>; def z_umul_lohi : SDNode<"SystemZISD::UMUL_LOHI", SDT_ZGR128Binary>; def z_sdivrem : SDNode<"SystemZISD::SDIVREM", SDT_ZGR128Binary>; def z_udivrem : SDNode<"SystemZISD::UDIVREM", SDT_ZGR128Binary>; @@ -549,6 +550,12 @@ def z_fma : PatFrag<(ops node:$src1, node:$src2, node:$src3), def z_fms : PatFrag<(ops node:$src1, node:$src2, node:$src3), (fma node:$src2, node:$src3, (fneg node:$src1))>; +// Negative fused multiply-add and multiply-subtract. +def fnma : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (fneg (fma node:$src1, node:$src2, node:$src3))>; +def fnms : PatFrag<(ops node:$src1, node:$src2, node:$src3), + (fneg (fms node:$src1, node:$src2, node:$src3))>; + // Floating-point negative absolute. def fnabs : PatFrag<(ops node:$ptr), (fneg (fabs node:$ptr))>; @@ -624,6 +631,19 @@ def z_vllezf64 : PatFrag<(ops node:$addr), (scalar_to_vector (f64 (load node:$addr))), (z_vzero))>; +// Similarly for the high element of a zeroed vector. +def z_vllezli32 : z_vllez; +def z_vllezlf32 : PatFrag<(ops node:$addr), + (bitconvert + (z_merge_high + (v2i64 + (bitconvert + (z_merge_high + (v4f32 (scalar_to_vector + (f32 (load node:$addr)))), + (v4f32 (z_vzero))))), + (v2i64 (z_vzero))))>; + // Store one element of a vector. class z_vste : PatFrag<(ops node:$vec, node:$addr, node:$index), diff --git a/lib/Target/SystemZ/SystemZPatterns.td b/lib/Target/SystemZ/SystemZPatterns.td index 16a7ed784d7..152521fb66a 100644 --- a/lib/Target/SystemZ/SystemZPatterns.td +++ b/lib/Target/SystemZ/SystemZPatterns.td @@ -167,3 +167,10 @@ class FPConversion suppress, bits<4> mode> : Pat<(tr1.vt (operator (tr2.vt tr2.op:$vec))), (insn tr2.op:$vec, suppress, mode)>; + +// Use INSN to perform mininum/maximum operation OPERATOR on type TR. +// FUNCTION is the type of minimum/maximum function to perform. +class FPMinMax function> + : Pat<(tr.vt (operator (tr.vt tr.op:$vec1), (tr.vt tr.op:$vec2))), + (insn tr.op:$vec1, tr.op:$vec2, function)>; diff --git a/lib/Target/SystemZ/SystemZProcessors.td b/lib/Target/SystemZ/SystemZProcessors.td index 1cdc0949ff4..0dca4582dc0 100644 --- a/lib/Target/SystemZ/SystemZProcessors.td +++ b/lib/Target/SystemZ/SystemZProcessors.td @@ -33,3 +33,6 @@ def : ProcessorModel<"zEC12", ZEC12Model, Arch10SupportedFeatures.List>; def : ProcessorModel<"arch11", Z13Model, Arch11SupportedFeatures.List>; def : ProcessorModel<"z13", Z13Model, Arch11SupportedFeatures.List>; +def : ProcessorModel<"arch12", Z14Model, Arch12SupportedFeatures.List>; +def : ProcessorModel<"z14", Z14Model, Arch12SupportedFeatures.List>; + diff --git a/lib/Target/SystemZ/SystemZSchedule.td b/lib/Target/SystemZ/SystemZSchedule.td index 1ce0168f95e..8dba89f70a4 100644 --- a/lib/Target/SystemZ/SystemZSchedule.td +++ b/lib/Target/SystemZ/SystemZSchedule.td @@ -59,7 +59,7 @@ def FPU2 : SchedWrite; def DFU : SchedWrite; def DFU2 : SchedWrite; -// Vector sub units (z13) +// Vector sub units (z13 and later) def VecBF : SchedWrite; def VecBF2 : SchedWrite; def VecDF : SchedWrite; @@ -75,6 +75,7 @@ def VecXsPm : SchedWrite; def VBU : SchedWrite; +include "SystemZScheduleZ14.td" include "SystemZScheduleZ13.td" include "SystemZScheduleZEC12.td" include "SystemZScheduleZ196.td" diff --git a/lib/Target/SystemZ/SystemZScheduleZ14.td b/lib/Target/SystemZ/SystemZScheduleZ14.td new file mode 100644 index 00000000000..1cc69fffe16 --- /dev/null +++ b/lib/Target/SystemZ/SystemZScheduleZ14.td @@ -0,0 +1,1573 @@ +//-- SystemZScheduleZ14.td - SystemZ Scheduling Definitions ----*- tblgen -*-=// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines the machine model for Z14 to support instruction +// scheduling and other instruction cost heuristics. +// +//===----------------------------------------------------------------------===// + +def Z14Model : SchedMachineModel { + + let UnsupportedFeatures = Arch12UnsupportedFeatures.List; + + let IssueWidth = 8; + let MicroOpBufferSize = 60; // Issue queues + let LoadLatency = 1; // Optimistic load latency. + + let PostRAScheduler = 1; + + // Extra cycles for a mispredicted branch. + let MispredictPenalty = 20; +} + +let SchedModel = Z14Model in { + +// These definitions could be put in a subtarget common include file, +// but it seems the include system in Tablegen currently rejects +// multiple includes of same file. +def : WriteRes { + let NumMicroOps = 0; + let BeginGroup = 1; + let EndGroup = 1; +} +def : WriteRes { + let NumMicroOps = 0; + let BeginGroup = 1; +} +def : WriteRes { + let NumMicroOps = 0; + let EndGroup = 1; +} +def : WriteRes { let Latency = 2; let NumMicroOps = 0;} +def : WriteRes { let Latency = 3; let NumMicroOps = 0;} +def : WriteRes { let Latency = 4; let NumMicroOps = 0;} +def : WriteRes { let Latency = 5; let NumMicroOps = 0;} +def : WriteRes { let Latency = 6; let NumMicroOps = 0;} +def : WriteRes { let Latency = 7; let NumMicroOps = 0;} +def : WriteRes { let Latency = 8; let NumMicroOps = 0;} +def : WriteRes { let Latency = 9; let NumMicroOps = 0;} +def : WriteRes { let Latency = 10; let NumMicroOps = 0;} +def : WriteRes { let Latency = 11; let NumMicroOps = 0;} +def : WriteRes { let Latency = 12; let NumMicroOps = 0;} +def : WriteRes { let Latency = 15; let NumMicroOps = 0;} +def : WriteRes { let Latency = 20; let NumMicroOps = 0;} +def : WriteRes { let Latency = 30; let NumMicroOps = 0;} + +// Execution units. +def Z14_FXaUnit : ProcResource<2>; +def Z14_FXbUnit : ProcResource<2>; +def Z14_LSUnit : ProcResource<2>; +def Z14_VecUnit : ProcResource<2>; +def Z14_VecFPdUnit : ProcResource<2> { let BufferSize = 1; /* blocking */ } +def Z14_VBUnit : ProcResource<2>; + +// Subtarget specific definitions of scheduling resources. +def : WriteRes { let Latency = 1; } +def : WriteRes { let Latency = 2; } +def : WriteRes { let Latency = 1; } +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 8; } +def : WriteRes { let Latency = 9; } +def : WriteRes { let Latency = 8; } +def : WriteRes { let Latency = 9; } +def : WriteRes { let Latency = 1; } +def : WriteRes { let Latency = 2; } +def : WriteRes + { let Latency = 30; } +def : WriteRes { let Latency = 5; } +def : WriteRes { let Latency = 4; } +def : WriteRes { let Latency = 3; } +def : WriteRes; // Virtual Branching Unit + +// -------------------------- INSTRUCTIONS ---------------------------------- // + +// InstRW constructs have been used in order to preserve the +// readability of the InstrInfo files. + +// For each instruction, as matched by a regexp, provide a list of +// resources that it needs. These will be combined into a SchedClass. + +//===----------------------------------------------------------------------===// +// Stack allocation +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa], (instregex "ADJDYNALLOC$")>; // Pseudo -> LA / LAY + +//===----------------------------------------------------------------------===// +// Branch instructions +//===----------------------------------------------------------------------===// + +// Branch +def : InstRW<[VBU], (instregex "(Call)?BRC(L)?(Asm.*)?$")>; +def : InstRW<[VBU], (instregex "(Call)?J(G)?(Asm.*)?$")>; +def : InstRW<[FXb], (instregex "(Call)?BC(R)?(Asm.*)?$")>; +def : InstRW<[FXb], (instregex "(Call)?B(R)?(Asm.*)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "BI(C)?(Asm.*)?$")>; +def : InstRW<[FXa, EndGroup], (instregex "BRCT(G)?$")>; +def : InstRW<[FXb, FXa, Lat2, GroupAlone], (instregex "BRCTH$")>; +def : InstRW<[FXb, FXa, Lat2, GroupAlone], (instregex "BCT(G)?(R)?$")>; +def : InstRW<[FXa, FXa, FXb, FXb, Lat4, GroupAlone], + (instregex "B(R)?X(H|L).*$")>; + +// Compare and branch +def : InstRW<[FXb], (instregex "C(L)?(G)?(I|R)J(Asm.*)?$")>; +def : InstRW<[FXb, FXb, Lat2, GroupAlone], + (instregex "C(L)?(G)?(I|R)B(Call|Return|Asm.*)?$")>; + +//===----------------------------------------------------------------------===// +// Trap instructions +//===----------------------------------------------------------------------===// + +// Trap +def : InstRW<[VBU], (instregex "(Cond)?Trap$")>; + +// Compare and trap +def : InstRW<[FXb], (instregex "C(G)?(I|R)T(Asm.*)?$")>; +def : InstRW<[FXb], (instregex "CL(G)?RT(Asm.*)?$")>; +def : InstRW<[FXb], (instregex "CL(F|G)IT(Asm.*)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CL(G)?T(Asm.*)?$")>; + +//===----------------------------------------------------------------------===// +// Call and return instructions +//===----------------------------------------------------------------------===// + +// Call +def : InstRW<[VBU, FXa, FXa, Lat3, GroupAlone], (instregex "(Call)?BRAS$")>; +def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "(Call)?BRASL$")>; +def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "(Call)?BAS(R)?$")>; +def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "TLS_(G|L)DCALL$")>; + +// Return +def : InstRW<[FXb, EndGroup], (instregex "Return$")>; +def : InstRW<[FXb], (instregex "CondReturn$")>; + +//===----------------------------------------------------------------------===// +// Select instructions +//===----------------------------------------------------------------------===// + +// Select pseudo +def : InstRW<[FXa], (instregex "Select(32|64|32Mux)$")>; + +// CondStore pseudos +def : InstRW<[FXa], (instregex "CondStore16(Inv)?$")>; +def : InstRW<[FXa], (instregex "CondStore16Mux(Inv)?$")>; +def : InstRW<[FXa], (instregex "CondStore32(Inv)?$")>; +def : InstRW<[FXa], (instregex "CondStore32Mux(Inv)?$")>; +def : InstRW<[FXa], (instregex "CondStore64(Inv)?$")>; +def : InstRW<[FXa], (instregex "CondStore8(Inv)?$")>; +def : InstRW<[FXa], (instregex "CondStore8Mux(Inv)?$")>; + +//===----------------------------------------------------------------------===// +// Move instructions +//===----------------------------------------------------------------------===// + +// Moves +def : InstRW<[FXb, LSU, Lat5], (instregex "MV(G|H)?HI$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "MVI(Y)?$")>; + +// Move character +def : InstRW<[FXb, LSU, LSU, LSU, Lat8, GroupAlone], (instregex "MVC$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVCL(E|U)?$")>; + +// Pseudo -> reg move +def : InstRW<[FXa], (instregex "COPY(_TO_REGCLASS)?$")>; +def : InstRW<[FXa], (instregex "EXTRACT_SUBREG$")>; +def : InstRW<[FXa], (instregex "INSERT_SUBREG$")>; +def : InstRW<[FXa], (instregex "REG_SEQUENCE$")>; +def : InstRW<[FXa], (instregex "SUBREG_TO_REG$")>; + +// Loads +def : InstRW<[LSU], (instregex "L(Y|FH|RL|Mux|CBB)?$")>; +def : InstRW<[LSU], (instregex "LG(RL)?$")>; +def : InstRW<[LSU], (instregex "L128$")>; + +def : InstRW<[FXa], (instregex "LLIH(F|H|L)$")>; +def : InstRW<[FXa], (instregex "LLIL(F|H|L)$")>; + +def : InstRW<[FXa], (instregex "LG(F|H)I$")>; +def : InstRW<[FXa], (instregex "LHI(Mux)?$")>; +def : InstRW<[FXa], (instregex "LR(Mux)?$")>; + +// Load and zero rightmost byte +def : InstRW<[LSU], (instregex "LZR(F|G)$")>; + +// Load and trap +def : InstRW<[FXb, LSU, Lat5], (instregex "L(FH|G)?AT$")>; + +// Load and test +def : InstRW<[FXa, LSU, Lat5], (instregex "LT(G)?$")>; +def : InstRW<[FXa], (instregex "LT(G)?R$")>; + +// Stores +def : InstRW<[FXb, LSU, Lat5], (instregex "STG(RL)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "ST128$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "ST(Y|FH|RL|Mux)?$")>; + +// String moves. +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVST$")>; + +//===----------------------------------------------------------------------===// +// Conditional move instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, Lat2], (instregex "LOCRMux$")>; +def : InstRW<[FXa, Lat2], (instregex "LOC(G|FH)?R(Asm.*)?$")>; +def : InstRW<[FXa, Lat2], (instregex "LOC(G|H)?HI(Mux|(Asm.*))?$")>; +def : InstRW<[FXa, LSU, Lat6], (instregex "LOC(G|FH|Mux)?(Asm.*)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "STOC(G|FH|Mux)?(Asm.*)?$")>; + +//===----------------------------------------------------------------------===// +// Sign extensions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa], (instregex "L(B|H|G)R$")>; +def : InstRW<[FXa], (instregex "LG(B|H|F)R$")>; + +def : InstRW<[FXa, LSU, Lat5], (instregex "LTGF$")>; +def : InstRW<[FXa], (instregex "LTGFR$")>; + +def : InstRW<[FXa, LSU, Lat5], (instregex "LB(H|Mux)?$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "LH(Y)?$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "LH(H|Mux|RL)$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "LG(B|H|F)$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "LG(H|F)RL$")>; + +//===----------------------------------------------------------------------===// +// Zero extensions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa], (instregex "LLCR(Mux)?$")>; +def : InstRW<[FXa], (instregex "LLHR(Mux)?$")>; +def : InstRW<[FXa], (instregex "LLG(C|H|F|T)R$")>; +def : InstRW<[LSU], (instregex "LLC(Mux)?$")>; +def : InstRW<[LSU], (instregex "LLH(Mux)?$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "LL(C|H)H$")>; +def : InstRW<[LSU], (instregex "LLHRL$")>; +def : InstRW<[LSU], (instregex "LLG(C|H|F|T|HRL|FRL)$")>; + +// Load and zero rightmost byte +def : InstRW<[LSU], (instregex "LLZRGF$")>; + +// Load and trap +def : InstRW<[FXb, LSU, Lat5], (instregex "LLG(F|T)?AT$")>; + +//===----------------------------------------------------------------------===// +// Truncations +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat5], (instregex "STC(H|Y|Mux)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "STH(H|Y|RL|Mux)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "STCM(H|Y)?$")>; + +//===----------------------------------------------------------------------===// +// Multi-register moves +//===----------------------------------------------------------------------===// + +// Load multiple (estimated average of 5 ops) +def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone], + (instregex "LM(H|Y|G)?$")>; + +// Load multiple disjoint +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "LMD$")>; + +// Store multiple (estimated average of ceil(5/2) FXb ops) +def : InstRW<[LSU, LSU, FXb, FXb, FXb, Lat10, + GroupAlone], (instregex "STM(G|H|Y)?$")>; + +//===----------------------------------------------------------------------===// +// Byte swaps +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa], (instregex "LRV(G)?R$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "LRV(G|H)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "STRV(G|H)?$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVCIN$")>; + +//===----------------------------------------------------------------------===// +// Load address instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa], (instregex "LA(Y|RL)?$")>; + +// Load the Global Offset Table address ( -> larl ) +def : InstRW<[FXa], (instregex "GOT$")>; + +//===----------------------------------------------------------------------===// +// Absolute and Negation +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa], (instregex "LP(G)?R$")>; +def : InstRW<[FXa, FXa, Lat2, BeginGroup], (instregex "L(N|P)GFR$")>; +def : InstRW<[FXa], (instregex "LN(R|GR)$")>; +def : InstRW<[FXa], (instregex "LC(R|GR)$")>; +def : InstRW<[FXa, FXa, Lat2, BeginGroup], (instregex "LCGFR$")>; + +//===----------------------------------------------------------------------===// +// Insertion +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, LSU, Lat5], (instregex "IC(Y)?$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "IC32(Y)?$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "ICM(H|Y)?$")>; +def : InstRW<[FXa], (instregex "II(F|H|L)Mux$")>; +def : InstRW<[FXa], (instregex "IIHF(64)?$")>; +def : InstRW<[FXa], (instregex "IIHH(64)?$")>; +def : InstRW<[FXa], (instregex "IIHL(64)?$")>; +def : InstRW<[FXa], (instregex "IILF(64)?$")>; +def : InstRW<[FXa], (instregex "IILH(64)?$")>; +def : InstRW<[FXa], (instregex "IILL(64)?$")>; + +//===----------------------------------------------------------------------===// +// Addition +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, LSU, Lat5], (instregex "A(Y)?$")>; +def : InstRW<[FXa, LSU, Lat6], (instregex "AH(Y)?$")>; +def : InstRW<[FXa], (instregex "AIH$")>; +def : InstRW<[FXa], (instregex "AFI(Mux)?$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "AG$")>; +def : InstRW<[FXa], (instregex "AGFI$")>; +def : InstRW<[FXa], (instregex "AGHI(K)?$")>; +def : InstRW<[FXa], (instregex "AGR(K)?$")>; +def : InstRW<[FXa], (instregex "AHI(K)?$")>; +def : InstRW<[FXa], (instregex "AHIMux(K)?$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "AL(Y)?$")>; +def : InstRW<[FXa], (instregex "AL(FI|HSIK)$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "ALG(F)?$")>; +def : InstRW<[FXa], (instregex "ALGHSIK$")>; +def : InstRW<[FXa], (instregex "ALGF(I|R)$")>; +def : InstRW<[FXa], (instregex "ALGR(K)?$")>; +def : InstRW<[FXa], (instregex "ALR(K)?$")>; +def : InstRW<[FXa], (instregex "AR(K)?$")>; +def : InstRW<[FXa], (instregex "A(L)?HHHR$")>; +def : InstRW<[FXa, Lat2], (instregex "A(L)?HHLR$")>; +def : InstRW<[FXa], (instregex "ALSIH(N)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "A(L)?(G)?SI$")>; + +// Logical addition with carry +def : InstRW<[FXa, LSU, Lat6, GroupAlone], (instregex "ALC(G)?$")>; +def : InstRW<[FXa, Lat2, GroupAlone], (instregex "ALC(G)?R$")>; + +// Add with sign extension (16/32 -> 64) +def : InstRW<[FXa, LSU, Lat6], (instregex "AG(F|H)$")>; +def : InstRW<[FXa, Lat2], (instregex "AGFR$")>; + +//===----------------------------------------------------------------------===// +// Subtraction +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, LSU, Lat5], (instregex "S(G|Y)?$")>; +def : InstRW<[FXa, LSU, Lat6], (instregex "SH(Y)?$")>; +def : InstRW<[FXa], (instregex "SGR(K)?$")>; +def : InstRW<[FXa], (instregex "SLFI$")>; +def : InstRW<[FXa, LSU, Lat5], (instregex "SL(G|GF|Y)?$")>; +def : InstRW<[FXa], (instregex "SLGF(I|R)$")>; +def : InstRW<[FXa], (instregex "SLGR(K)?$")>; +def : InstRW<[FXa], (instregex "SLR(K)?$")>; +def : InstRW<[FXa], (instregex "SR(K)?$")>; +def : InstRW<[FXa], (instregex "S(L)?HHHR$")>; +def : InstRW<[FXa, Lat2], (instregex "S(L)?HHLR$")>; + +// Subtraction with borrow +def : InstRW<[FXa, LSU, Lat6, GroupAlone], (instregex "SLB(G)?$")>; +def : InstRW<[FXa, Lat2, GroupAlone], (instregex "SLB(G)?R$")>; + +// Subtraction with sign extension (16/32 -> 64) +def : InstRW<[FXa, LSU, Lat6], (instregex "SG(F|H)$")>; +def : InstRW<[FXa, Lat2], (instregex "SGFR$")>; + +//===----------------------------------------------------------------------===// +// AND +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, LSU, Lat5], (instregex "N(G|Y)?$")>; +def : InstRW<[FXa], (instregex "NGR(K)?$")>; +def : InstRW<[FXa], (instregex "NI(FMux|HMux|LMux)$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "NI(Y)?$")>; +def : InstRW<[FXa], (instregex "NIHF(64)?$")>; +def : InstRW<[FXa], (instregex "NIHH(64)?$")>; +def : InstRW<[FXa], (instregex "NIHL(64)?$")>; +def : InstRW<[FXa], (instregex "NILF(64)?$")>; +def : InstRW<[FXa], (instregex "NILH(64)?$")>; +def : InstRW<[FXa], (instregex "NILL(64)?$")>; +def : InstRW<[FXa], (instregex "NR(K)?$")>; +def : InstRW<[LSU, LSU, FXb, Lat9, BeginGroup], (instregex "NC$")>; + +//===----------------------------------------------------------------------===// +// OR +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, LSU, Lat5], (instregex "O(G|Y)?$")>; +def : InstRW<[FXa], (instregex "OGR(K)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "OI(Y)?$")>; +def : InstRW<[FXa], (instregex "OI(FMux|HMux|LMux)$")>; +def : InstRW<[FXa], (instregex "OIHF(64)?$")>; +def : InstRW<[FXa], (instregex "OIHH(64)?$")>; +def : InstRW<[FXa], (instregex "OIHL(64)?$")>; +def : InstRW<[FXa], (instregex "OILF(64)?$")>; +def : InstRW<[FXa], (instregex "OILH(64)?$")>; +def : InstRW<[FXa], (instregex "OILL(64)?$")>; +def : InstRW<[FXa], (instregex "OR(K)?$")>; +def : InstRW<[LSU, LSU, FXb, Lat9, BeginGroup], (instregex "OC$")>; + +//===----------------------------------------------------------------------===// +// XOR +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, LSU, Lat5], (instregex "X(G|Y)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "XI(Y)?$")>; +def : InstRW<[FXa], (instregex "XIFMux$")>; +def : InstRW<[FXa], (instregex "XGR(K)?$")>; +def : InstRW<[FXa], (instregex "XIHF(64)?$")>; +def : InstRW<[FXa], (instregex "XILF(64)?$")>; +def : InstRW<[FXa], (instregex "XR(K)?$")>; +def : InstRW<[LSU, LSU, FXb, Lat9, BeginGroup], (instregex "XC$")>; + +//===----------------------------------------------------------------------===// +// Multiplication +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, LSU, Lat9], (instregex "MS(GF|Y)?$")>; +def : InstRW<[FXa, Lat5], (instregex "MS(R|FI)$")>; +def : InstRW<[FXa, LSU, Lat11], (instregex "MSG$")>; +def : InstRW<[FXa, Lat7], (instregex "MSGR$")>; +def : InstRW<[FXa, Lat5], (instregex "MSGF(I|R)$")>; +def : InstRW<[FXa2, LSU, Lat12, GroupAlone], (instregex "MLG$")>; +def : InstRW<[FXa2, Lat8, GroupAlone], (instregex "MLGR$")>; +def : InstRW<[FXa, Lat4], (instregex "MGHI$")>; +def : InstRW<[FXa, Lat4], (instregex "MHI$")>; +def : InstRW<[FXa, LSU, Lat8], (instregex "MH(Y)?$")>; +def : InstRW<[FXa2, Lat6, GroupAlone], (instregex "M(L)?R$")>; +def : InstRW<[FXa2, LSU, Lat10, GroupAlone], (instregex "M(FY|L)?$")>; +def : InstRW<[FXa, LSU, Lat8], (instregex "MGH$")>; +def : InstRW<[FXa, LSU, Lat12, GroupAlone], (instregex "MG$")>; +def : InstRW<[FXa, Lat8, GroupAlone], (instregex "MGRK$")>; +def : InstRW<[FXa, LSU, Lat9, GroupAlone], (instregex "MSC$")>; +def : InstRW<[FXa, LSU, Lat11, GroupAlone], (instregex "MSGC$")>; +def : InstRW<[FXa, Lat5], (instregex "MSRKC$")>; +def : InstRW<[FXa, Lat7], (instregex "MSGRKC$")>; + +//===----------------------------------------------------------------------===// +// Division and remainder +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa2, FXa2, Lat20, GroupAlone], (instregex "DR$")>; +def : InstRW<[FXa2, FXa2, LSU, Lat30, GroupAlone], (instregex "D$")>; +def : InstRW<[FXa2, Lat30, GroupAlone], (instregex "DSG(F)?R$")>; +def : InstRW<[LSU, FXa2, Lat30, GroupAlone], (instregex "DSG(F)?$")>; +def : InstRW<[FXa2, FXa2, Lat20, GroupAlone], (instregex "DLR$")>; +def : InstRW<[FXa2, FXa2, Lat30, GroupAlone], (instregex "DLGR$")>; +def : InstRW<[FXa2, FXa2, LSU, Lat30, GroupAlone], (instregex "DL(G)?$")>; + +//===----------------------------------------------------------------------===// +// Shifts +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa], (instregex "SLL(G|K)?$")>; +def : InstRW<[FXa], (instregex "SRL(G|K)?$")>; +def : InstRW<[FXa], (instregex "SRA(G|K)?$")>; +def : InstRW<[FXa], (instregex "SLA(G|K)?$")>; +def : InstRW<[FXa, FXa, FXa, FXa, LSU, Lat8, GroupAlone], + (instregex "S(L|R)D(A|L)$")>; + +// Rotate +def : InstRW<[FXa, LSU, Lat6], (instregex "RLL(G)?$")>; + +// Rotate and insert +def : InstRW<[FXa], (instregex "RISBG(N|32)?$")>; +def : InstRW<[FXa], (instregex "RISBH(G|H|L)$")>; +def : InstRW<[FXa], (instregex "RISBL(G|H|L)$")>; +def : InstRW<[FXa], (instregex "RISBMux$")>; + +// Rotate and Select +def : InstRW<[FXa, FXa, Lat2, BeginGroup], (instregex "R(N|O|X)SBG$")>; + +//===----------------------------------------------------------------------===// +// Comparison +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat5], (instregex "C(G|Y|Mux|RL)?$")>; +def : InstRW<[FXb], (instregex "C(F|H)I(Mux)?$")>; +def : InstRW<[FXb], (instregex "CG(F|H)I$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CG(HSI|RL)$")>; +def : InstRW<[FXb], (instregex "C(G)?R$")>; +def : InstRW<[FXb], (instregex "CIH$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CH(F|SI)$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CL(Y|Mux|FHSI)?$")>; +def : InstRW<[FXb], (instregex "CLFI(Mux)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CLG(HRL|HSI)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CLGF(RL)?$")>; +def : InstRW<[FXb], (instregex "CLGF(I|R)$")>; +def : InstRW<[FXb], (instregex "CLGR$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CLGRL$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CLH(F|RL|HSI)$")>; +def : InstRW<[FXb], (instregex "CLIH$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CLI(Y)?$")>; +def : InstRW<[FXb], (instregex "CLR$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "CLRL$")>; +def : InstRW<[FXb], (instregex "C(L)?HHR$")>; +def : InstRW<[FXb, Lat2], (instregex "C(L)?HLR$")>; + +// Compare halfword +def : InstRW<[FXb, LSU, Lat6], (instregex "CH(Y|RL)?$")>; +def : InstRW<[FXb, LSU, Lat6], (instregex "CGH(RL)?$")>; +def : InstRW<[FXa, FXb, LSU, Lat6, BeginGroup], (instregex "CHHSI$")>; + +// Compare with sign extension (32 -> 64) +def : InstRW<[FXb, LSU, Lat6], (instregex "CGF(RL)?$")>; +def : InstRW<[FXb, Lat2], (instregex "CGFR$")>; + +// Compare logical character +def : InstRW<[FXb, LSU, LSU, Lat9, BeginGroup], (instregex "CLC$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLCL(E|U)?$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CLST$")>; + +// Test under mask +def : InstRW<[FXb, LSU, Lat5], (instregex "TM(Y)?$")>; +def : InstRW<[FXb], (instregex "TM(H|L)Mux$")>; +def : InstRW<[FXb], (instregex "TMHH(64)?$")>; +def : InstRW<[FXb], (instregex "TMHL(64)?$")>; +def : InstRW<[FXb], (instregex "TMLH(64)?$")>; +def : InstRW<[FXb], (instregex "TMLL(64)?$")>; + +// Compare logical characters under mask +def : InstRW<[FXb, LSU, Lat6], (instregex "CLM(H|Y)?$")>; + +//===----------------------------------------------------------------------===// +// Prefetch and execution hint +//===----------------------------------------------------------------------===// + +def : InstRW<[LSU], (instregex "PFD(RL)?$")>; +def : InstRW<[FXb, Lat2], (instregex "BPP$")>; +def : InstRW<[FXb, EndGroup], (instregex "BPRP$")>; +def : InstRW<[FXb], (instregex "NIAI$")>; + +//===----------------------------------------------------------------------===// +// Atomic operations +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, EndGroup], (instregex "Serialize$")>; + +def : InstRW<[FXb, LSU, Lat5], (instregex "LAA(G)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "LAAL(G)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "LAN(G)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "LAO(G)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "LAX(G)?$")>; + +// Test and set +def : InstRW<[FXb, LSU, Lat5, EndGroup], (instregex "TS$")>; + +// Compare and swap +def : InstRW<[FXa, FXb, LSU, Lat6, GroupAlone], (instregex "CS(G|Y)?$")>; + +// Compare double and swap +def : InstRW<[FXa, FXa, FXb, FXb, FXa, LSU, Lat10, GroupAlone], + (instregex "CDS(Y)?$")>; +def : InstRW<[FXa, FXa, FXb, FXb, LSU, FXb, FXb, LSU, LSU, Lat20, GroupAlone], + (instregex "CDSG$")>; + +// Compare and swap and store +def : InstRW<[FXa, LSU, Lat30], (instregex "CSST$")>; + +// Perform locked operation +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "PLO$")>; + +// Load/store pair from/to quadword +def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPQ$")>; +def : InstRW<[FXb, FXb, LSU, Lat6, GroupAlone], (instregex "STPQ$")>; + +// Load pair disjoint +def : InstRW<[LSU, LSU, Lat5, GroupAlone], (instregex "LPD(G)?$")>; + +//===----------------------------------------------------------------------===// +// Translate and convert +//===----------------------------------------------------------------------===// + +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "TR$")>; +def : InstRW<[FXa, FXa, FXa, LSU, LSU, Lat30, GroupAlone], (instregex "TRT$")>; +def : InstRW<[FXa, LSU, Lat30], (instregex "TRTR$")>; +def : InstRW<[FXa, Lat30], (instregex "TR(TR)?(T)?(E|EOpt)?$")>; +def : InstRW<[LSU, Lat30], (instregex "TR(T|O)(T|O)(Opt)?$")>; +def : InstRW<[FXa, Lat30], (instregex "CU(12|14|21|24|41|42)(Opt)?$")>; +def : InstRW<[FXa, Lat30], (instregex "(CUUTF|CUTFU)(Opt)?$")>; + +//===----------------------------------------------------------------------===// +// Message-security assist +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, Lat30], (instregex "KM(C|F|O|CTR|A)?$")>; +def : InstRW<[FXa, Lat30], (instregex "(KIMD|KLMD|KMAC)$")>; +def : InstRW<[FXa, Lat30], (instregex "(PCC|PPNO|PRNO)$")>; + +//===----------------------------------------------------------------------===// +// Guarded storage +//===----------------------------------------------------------------------===// + +def : InstRW<[LSU], (instregex "LGG$")>; +def : InstRW<[LSU, Lat5], (instregex "LLGFSG$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)GSC$")>; + +//===----------------------------------------------------------------------===// +// Decimal arithmetic +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, VecDF, VecDF, LSU, LSU, Lat30, GroupAlone], + (instregex "CVBG$")>; +def : InstRW<[FXb, VecDF, LSU, Lat30, GroupAlone], (instregex "CVB(Y)?$")>; +def : InstRW<[FXb, FXb, FXb, VecDF2, VecDF2, LSU, Lat30, GroupAlone], + (instregex "CVDG$")>; +def : InstRW<[FXb, VecDF, FXb, LSU, Lat30, GroupAlone], (instregex "CVD(Y)?$")>; +def : InstRW<[LSU, Lat10, GroupAlone], (instregex "MVO$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MV(N|Z)$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(PACK|PKA|PKU)$")>; +def : InstRW<[LSU, Lat12, GroupAlone], (instregex "UNPK(A|U)$")>; +def : InstRW<[FXb, LSU, LSU, Lat9, BeginGroup], (instregex "UNPK$")>; + +def : InstRW<[FXb, VecDFX, LSU, LSU, LSU, Lat9, GroupAlone], + (instregex "(A|S|ZA)P$")>; +def : InstRW<[FXb, VecDFX2, VecDFX2, LSU, LSU, LSU, Lat30, GroupAlone], + (instregex "(M|D)P$")>; +def : InstRW<[FXb, VecDFX, VecDFX, LSU, LSU, Lat15, GroupAlone], + (instregex "SRP$")>; +def : InstRW<[VecDFX, LSU, LSU, Lat5, GroupAlone], (instregex "CP$")>; +def : InstRW<[VecDFX, LSU, Lat4, BeginGroup], (instregex "TP$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "ED(MK)?$")>; + +//===----------------------------------------------------------------------===// +// Access registers +//===----------------------------------------------------------------------===// + +// Extract/set/copy access register +def : InstRW<[LSU], (instregex "(EAR|SAR|CPYA)$")>; + +// Load address extended +def : InstRW<[LSU, FXa, Lat5, BeginGroup], (instregex "LAE(Y)?$")>; + +// Load/store access multiple (not modeled precisely) +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "(L|ST)AM(Y)?$")>; + +//===----------------------------------------------------------------------===// +// Program mask and addressing mode +//===----------------------------------------------------------------------===// + +// Insert Program Mask +def : InstRW<[FXa, Lat3, EndGroup], (instregex "IPM$")>; + +// Set Program Mask +def : InstRW<[LSU, EndGroup], (instregex "SPM$")>; + +// Branch and link +def : InstRW<[FXa, FXa, FXb, Lat5, GroupAlone], (instregex "BAL(R)?$")>; + +// Test addressing mode +def : InstRW<[FXb], (instregex "TAM$")>; + +// Set addressing mode +def : InstRW<[FXb, Lat2, EndGroup], (instregex "SAM(24|31|64)$")>; + +// Branch (and save) and set mode. +def : InstRW<[FXa, FXb, Lat2, GroupAlone], (instregex "BSM$")>; +def : InstRW<[FXa, FXa, FXb, Lat3, GroupAlone], (instregex "BASSM$")>; + +//===----------------------------------------------------------------------===// +// Transactional execution +//===----------------------------------------------------------------------===// + +// Transaction begin +def : InstRW<[LSU, LSU, FXb, FXb, FXb, FXb, FXb, Lat15, GroupAlone], + (instregex "TBEGIN(C|_nofloat)?$")>; + +// Transaction end +def : InstRW<[FXb, GroupAlone], (instregex "TEND$")>; + +// Transaction abort +def : InstRW<[LSU, GroupAlone], (instregex "TABORT$")>; + +// Extract Transaction Nesting Depth +def : InstRW<[FXa], (instregex "ETND$")>; + +// Nontransactional store +def : InstRW<[FXb, LSU, Lat5], (instregex "NTSTG$")>; + +//===----------------------------------------------------------------------===// +// Processor assist +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb], (instregex "PPA$")>; + +//===----------------------------------------------------------------------===// +// Miscellaneous Instructions. +//===----------------------------------------------------------------------===// + +// Find leftmost one +def : InstRW<[FXa, FXa, Lat4, GroupAlone], (instregex "FLOGR$")>; + +// Population count +def : InstRW<[FXa, Lat3], (instregex "POPCNT$")>; + +// Extend +def : InstRW<[FXa], (instregex "AEXT128$")>; +def : InstRW<[FXa], (instregex "ZEXT128$")>; + +// String instructions +def : InstRW<[FXa, LSU, Lat30], (instregex "SRST$")>; +def : InstRW<[FXa, Lat30], (instregex "SRSTU$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "CUSE$")>; + +// Various complex instructions +def : InstRW<[LSU, Lat30], (instregex "CFC$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "UPT$")>; +def : InstRW<[LSU, Lat30], (instregex "CKSM$")>; +def : InstRW<[FXa, Lat30], (instregex "CMPSC$")>; + +// Execute +def : InstRW<[FXb, GroupAlone], (instregex "EX(RL)?$")>; + +//===----------------------------------------------------------------------===// +// .insn directive instructions +//===----------------------------------------------------------------------===// + +// An "empty" sched-class will be assigned instead of the "invalid sched-class". +// getNumDecoderSlots() will then return 1 instead of 0. +def : InstRW<[], (instregex "Insn.*")>; + + +// ----------------------------- Floating point ----------------------------- // + +//===----------------------------------------------------------------------===// +// FP: Select instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa], (instregex "SelectF(32|64|128)$")>; +def : InstRW<[FXa], (instregex "CondStoreF32(Inv)?$")>; +def : InstRW<[FXa], (instregex "CondStoreF64(Inv)?$")>; + +//===----------------------------------------------------------------------===// +// FP: Move instructions +//===----------------------------------------------------------------------===// + +// Load zero +def : InstRW<[FXb], (instregex "LZ(DR|ER)$")>; +def : InstRW<[FXb, FXb, Lat2, BeginGroup], (instregex "LZXR$")>; + +// Load +def : InstRW<[VecXsPm], (instregex "LER$")>; +def : InstRW<[FXb], (instregex "LD(R|R32|GR)$")>; +def : InstRW<[FXb, Lat3], (instregex "LGDR$")>; +def : InstRW<[FXb, FXb, Lat2, GroupAlone], (instregex "LXR$")>; + +// Load and Test +def : InstRW<[VecXsPm, Lat4], (instregex "LT(D|E)BR$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "LTEBRCompare(_VecPseudo)?$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "LTDBRCompare(_VecPseudo)?$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXBR$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], + (instregex "LTXBRCompare(_VecPseudo)?$")>; + +// Copy sign +def : InstRW<[VecXsPm], (instregex "CPSDRd(d|s)$")>; +def : InstRW<[VecXsPm], (instregex "CPSDRs(d|s)$")>; + +//===----------------------------------------------------------------------===// +// FP: Load instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[VecXsPm, LSU, Lat7], (instregex "LE(Y)?$")>; +def : InstRW<[LSU], (instregex "LD(Y|E32)?$")>; +def : InstRW<[LSU], (instregex "LX$")>; + +//===----------------------------------------------------------------------===// +// FP: Store instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat7], (instregex "STD(Y)?$")>; +def : InstRW<[FXb, LSU, Lat7], (instregex "STE(Y)?$")>; +def : InstRW<[FXb, LSU, Lat5], (instregex "STX$")>; + +//===----------------------------------------------------------------------===// +// FP: Conversion instructions +//===----------------------------------------------------------------------===// + +// Load rounded +def : InstRW<[VecBF], (instregex "LEDBR(A)?$")>; +def : InstRW<[VecDF, VecDF, Lat20], (instregex "LEXBR(A)?$")>; +def : InstRW<[VecDF, VecDF, Lat20], (instregex "LDXBR(A)?$")>; + +// Load lengthened +def : InstRW<[VecBF, LSU, Lat12], (instregex "LDEB$")>; +def : InstRW<[VecBF], (instregex "LDEBR$")>; +def : InstRW<[VecBF2, VecBF2, LSU, Lat12 , GroupAlone], (instregex "LX(D|E)B$")>; +def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "LX(D|E)BR$")>; + +// Convert from fixed / logical +def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CE(F|G)BR(A)?$")>; +def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CD(F|G)BR(A)?$")>; +def : InstRW<[FXb, VecDF2, VecDF2, Lat12, GroupAlone], (instregex "CX(F|G)BR(A)?$")>; +def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CEL(F|G)BR$")>; +def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CDL(F|G)BR$")>; +def : InstRW<[FXb, VecDF2, VecDF2, Lat12, GroupAlone], (instregex "CXL(F|G)BR$")>; + +// Convert to fixed / logical +def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CF(E|D)BR(A)?$")>; +def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CG(E|D)BR(A)?$")>; +def : InstRW<[FXb, VecDF, VecDF, Lat20, BeginGroup], (instregex "C(F|G)XBR(A)?$")>; +def : InstRW<[FXb, VecBF, Lat11, GroupAlone], (instregex "CLFEBR$")>; +def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CLFDBR$")>; +def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CLG(E|D)BR$")>; +def : InstRW<[FXb, VecDF, VecDF, Lat20, BeginGroup], (instregex "CL(F|G)XBR$")>; + +//===----------------------------------------------------------------------===// +// FP: Unary arithmetic +//===----------------------------------------------------------------------===// + +// Load Complement / Negative / Positive +def : InstRW<[VecXsPm, Lat4], (instregex "L(C|N|P)DBR$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "L(C|N|P)EBR$")>; +def : InstRW<[FXb], (instregex "LCDFR(_32)?$")>; +def : InstRW<[FXb], (instregex "LNDFR(_32)?$")>; +def : InstRW<[FXb], (instregex "LPDFR(_32)?$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "L(C|N|P)XBR$")>; + +// Square root +def : InstRW<[VecFPd, LSU], (instregex "SQ(E|D)B$")>; +def : InstRW<[VecFPd], (instregex "SQ(E|D)BR$")>; +def : InstRW<[VecFPd, VecFPd, GroupAlone], (instregex "SQXBR$")>; + +// Load FP integer +def : InstRW<[VecBF], (instregex "FIEBR(A)?$")>; +def : InstRW<[VecBF], (instregex "FIDBR(A)?$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "FIXBR(A)?$")>; + +//===----------------------------------------------------------------------===// +// FP: Binary arithmetic +//===----------------------------------------------------------------------===// + +// Addition +def : InstRW<[VecBF, LSU, Lat12], (instregex "A(E|D)B$")>; +def : InstRW<[VecBF], (instregex "A(E|D)BR$")>; +def : InstRW<[VecDF2, VecDF2, Lat10, GroupAlone], (instregex "AXBR$")>; + +// Subtraction +def : InstRW<[VecBF, LSU, Lat12], (instregex "S(E|D)B$")>; +def : InstRW<[VecBF], (instregex "S(E|D)BR$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "SXBR$")>; + +// Multiply +def : InstRW<[VecBF, LSU, Lat12], (instregex "M(D|DE|EE)B$")>; +def : InstRW<[VecBF], (instregex "M(D|DE|EE)BR$")>; +def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "MXDB$")>; +def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "MXDBR$")>; +def : InstRW<[VecDF2, VecDF2, Lat20, GroupAlone], (instregex "MXBR$")>; + +// Multiply and add / subtract +def : InstRW<[VecBF2, LSU, Lat12, GroupAlone], (instregex "M(A|S)EB$")>; +def : InstRW<[VecBF, GroupAlone], (instregex "M(A|S)EBR$")>; +def : InstRW<[VecBF2, LSU, Lat12, GroupAlone], (instregex "M(A|S)DB$")>; +def : InstRW<[VecBF], (instregex "M(A|S)DBR$")>; + +// Division +def : InstRW<[VecFPd, LSU], (instregex "D(E|D)B$")>; +def : InstRW<[VecFPd], (instregex "D(E|D)BR$")>; +def : InstRW<[VecFPd, VecFPd, GroupAlone], (instregex "DXBR$")>; + +// Divide to integer +def : InstRW<[VecFPd, Lat30], (instregex "DI(E|D)BR$")>; + +//===----------------------------------------------------------------------===// +// FP: Comparisons +//===----------------------------------------------------------------------===// + +// Compare +def : InstRW<[VecXsPm, LSU, Lat8], (instregex "(K|C)(E|D)B$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "(K|C)(E|D)BR?$")>; +def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "(K|C)XBR$")>; + +// Test Data Class +def : InstRW<[LSU, VecXsPm, Lat9], (instregex "TC(E|D)B$")>; +def : InstRW<[LSU, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "TCXB$")>; + +//===----------------------------------------------------------------------===// +// FP: Floating-point control register instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, LSU, Lat4, GroupAlone], (instregex "EFPC$")>; +def : InstRW<[FXb, LSU, Lat5, GroupAlone], (instregex "STFPC$")>; +def : InstRW<[LSU, Lat3, GroupAlone], (instregex "SFPC$")>; +def : InstRW<[LSU, LSU, Lat6, GroupAlone], (instregex "LFPC$")>; +def : InstRW<[FXa, Lat30], (instregex "SFASR$")>; +def : InstRW<[FXa, LSU, Lat30], (instregex "LFAS$")>; +def : InstRW<[FXb, Lat3, GroupAlone], (instregex "SRNM(B|T)?$")>; + + +// --------------------- Hexadecimal floating point ------------------------- // + +//===----------------------------------------------------------------------===// +// HFP: Move instructions +//===----------------------------------------------------------------------===// + +// Load and Test +def : InstRW<[VecXsPm, Lat4], (instregex "LT(D|E)R$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXR$")>; + +//===----------------------------------------------------------------------===// +// HFP: Conversion instructions +//===----------------------------------------------------------------------===// + +// Load rounded +def : InstRW<[VecBF], (instregex "(LEDR|LRER)$")>; +def : InstRW<[VecBF], (instregex "LEXR$")>; +def : InstRW<[VecDF2], (instregex "(LDXR|LRDR)$")>; + +// Load lengthened +def : InstRW<[LSU], (instregex "LDE$")>; +def : InstRW<[FXb], (instregex "LDER$")>; +def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "LX(D|E)$")>; +def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "LX(D|E)R$")>; + +// Convert from fixed +def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CE(F|G)R$")>; +def : InstRW<[FXb, VecBF, Lat9, BeginGroup], (instregex "CD(F|G)R$")>; +def : InstRW<[FXb, VecDF2, VecDF2, Lat12, GroupAlone], (instregex "CX(F|G)R$")>; + +// Convert to fixed +def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CF(E|D)R$")>; +def : InstRW<[FXb, VecBF, Lat11, BeginGroup], (instregex "CG(E|D)R$")>; +def : InstRW<[FXb, VecDF, VecDF, Lat20, BeginGroup], (instregex "C(F|G)XR$")>; + +// Convert BFP to HFP / HFP to BFP. +def : InstRW<[VecBF], (instregex "THD(E)?R$")>; +def : InstRW<[VecBF], (instregex "TB(E)?DR$")>; + +//===----------------------------------------------------------------------===// +// HFP: Unary arithmetic +//===----------------------------------------------------------------------===// + +// Load Complement / Negative / Positive +def : InstRW<[VecXsPm, Lat4], (instregex "L(C|N|P)DR$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "L(C|N|P)ER$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "L(C|N|P)XR$")>; + +// Halve +def : InstRW<[VecBF], (instregex "H(E|D)R$")>; + +// Square root +def : InstRW<[VecFPd, LSU], (instregex "SQ(E|D)$")>; +def : InstRW<[VecFPd], (instregex "SQ(E|D)R$")>; +def : InstRW<[VecFPd, VecFPd, GroupAlone], (instregex "SQXR$")>; + +// Load FP integer +def : InstRW<[VecBF], (instregex "FIER$")>; +def : InstRW<[VecBF], (instregex "FIDR$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "FIXR$")>; + +//===----------------------------------------------------------------------===// +// HFP: Binary arithmetic +//===----------------------------------------------------------------------===// + +// Addition +def : InstRW<[VecBF, LSU, Lat12], (instregex "A(E|D|U|W)$")>; +def : InstRW<[VecBF], (instregex "A(E|D|U|W)R$")>; +def : InstRW<[VecDF2, VecDF2, Lat10, GroupAlone], (instregex "AXR$")>; + +// Subtraction +def : InstRW<[VecBF, LSU, Lat12], (instregex "S(E|D|U|W)$")>; +def : InstRW<[VecBF], (instregex "S(E|D|U|W)R$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "SXR$")>; + +// Multiply +def : InstRW<[VecBF, LSU, Lat12], (instregex "M(D|DE|E|EE)$")>; +def : InstRW<[VecBF], (instregex "M(D|DE|E|EE)R$")>; +def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "MXD$")>; +def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "MXDR$")>; +def : InstRW<[VecDF2, VecDF2, Lat20, GroupAlone], (instregex "MXR$")>; +def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "MY$")>; +def : InstRW<[VecBF2, LSU, Lat12, GroupAlone], (instregex "MY(H|L)$")>; +def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "MYR$")>; +def : InstRW<[VecBF, GroupAlone], (instregex "MY(H|L)R$")>; + +// Multiply and add / subtract +def : InstRW<[VecBF2, LSU, Lat12, GroupAlone], (instregex "M(A|S)E$")>; +def : InstRW<[VecBF, GroupAlone], (instregex "M(A|S)ER$")>; +def : InstRW<[VecBF2, LSU, Lat12, GroupAlone], (instregex "M(A|S)D$")>; +def : InstRW<[VecBF, GroupAlone], (instregex "M(A|S)DR$")>; +def : InstRW<[VecBF2, LSU, Lat12, GroupAlone], (instregex "MAY(H|L)$")>; +def : InstRW<[VecBF2, VecBF2, LSU, Lat12, GroupAlone], (instregex "MAY$")>; +def : InstRW<[VecBF, GroupAlone], (instregex "MAY(H|L)R$")>; +def : InstRW<[VecBF2, VecBF2, GroupAlone], (instregex "MAYR$")>; + +// Division +def : InstRW<[VecFPd, LSU], (instregex "D(E|D)$")>; +def : InstRW<[VecFPd], (instregex "D(E|D)R$")>; +def : InstRW<[VecFPd, VecFPd, GroupAlone], (instregex "DXR$")>; + +//===----------------------------------------------------------------------===// +// HFP: Comparisons +//===----------------------------------------------------------------------===// + +// Compare +def : InstRW<[VecBF, LSU, Lat12], (instregex "C(E|D)$")>; +def : InstRW<[VecBF], (instregex "C(E|D)R$")>; +def : InstRW<[VecDF, VecDF, Lat20, GroupAlone], (instregex "CXR$")>; + + +// ------------------------ Decimal floating point -------------------------- // + +//===----------------------------------------------------------------------===// +// DFP: Move instructions +//===----------------------------------------------------------------------===// + +// Load and Test +def : InstRW<[VecDF], (instregex "LTDTR$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LTXTR$")>; + +//===----------------------------------------------------------------------===// +// DFP: Conversion instructions +//===----------------------------------------------------------------------===// + +// Load rounded +def : InstRW<[VecDF, Lat15], (instregex "LEDTR$")>; +def : InstRW<[VecDF, VecDF, Lat20], (instregex "LDXTR$")>; + +// Load lengthened +def : InstRW<[VecDF], (instregex "LDETR$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "LXDTR$")>; + +// Convert from fixed / logical +def : InstRW<[FXb, VecDF, Lat30, BeginGroup], (instregex "CD(F|G)TR(A)?$")>; +def : InstRW<[FXb, VecDF2, VecDF2, Lat30, GroupAlone], (instregex "CX(F|G)TR(A)?$")>; +def : InstRW<[FXb, VecDF, Lat30, BeginGroup], (instregex "CDL(F|G)TR$")>; +def : InstRW<[FXb, VecDF2, VecDF2, Lat30, GroupAlone], (instregex "CXL(F|G)TR$")>; + +// Convert to fixed / logical +def : InstRW<[FXb, VecDF, Lat30, BeginGroup], (instregex "C(F|G)DTR(A)?$")>; +def : InstRW<[FXb, VecDF, VecDF, Lat30, BeginGroup], (instregex "C(F|G)XTR(A)?$")>; +def : InstRW<[FXb, VecDF, Lat30, BeginGroup], (instregex "CL(F|G)DTR$")>; +def : InstRW<[FXb, VecDF, VecDF, Lat30, BeginGroup], (instregex "CL(F|G)XTR$")>; + +// Convert from / to signed / unsigned packed +def : InstRW<[FXb, VecDF, Lat9, BeginGroup], (instregex "CD(S|U)TR$")>; +def : InstRW<[FXb, FXb, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "CX(S|U)TR$")>; +def : InstRW<[FXb, VecDF, Lat12, BeginGroup], (instregex "C(S|U)DTR$")>; +def : InstRW<[FXb, FXb, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "C(S|U)XTR$")>; + +// Convert from / to zoned +def : InstRW<[LSU, VecDF, Lat11, BeginGroup], (instregex "CDZT$")>; +def : InstRW<[LSU, LSU, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "CXZT$")>; +def : InstRW<[FXb, LSU, VecDF, Lat11, BeginGroup], (instregex "CZDT$")>; +def : InstRW<[FXb, LSU, VecDF, VecDF, Lat15, GroupAlone], (instregex "CZXT$")>; + +// Convert from / to packed +def : InstRW<[LSU, VecDF, Lat11, BeginGroup], (instregex "CDPT$")>; +def : InstRW<[LSU, LSU, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "CXPT$")>; +def : InstRW<[FXb, LSU, VecDF, Lat11, BeginGroup], (instregex "CPDT$")>; +def : InstRW<[FXb, LSU, VecDF, VecDF, Lat15, GroupAlone], (instregex "CPXT$")>; + +// Perform floating-point operation +def : InstRW<[FXb, Lat30], (instregex "PFPO$")>; + +//===----------------------------------------------------------------------===// +// DFP: Unary arithmetic +//===----------------------------------------------------------------------===// + +// Load FP integer +def : InstRW<[VecDF], (instregex "FIDTR$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "FIXTR$")>; + +// Extract biased exponent +def : InstRW<[FXb, VecDF, Lat12, BeginGroup], (instregex "EEDTR$")>; +def : InstRW<[FXb, VecDF, Lat12, BeginGroup], (instregex "EEXTR$")>; + +// Extract significance +def : InstRW<[FXb, VecDF, Lat12, BeginGroup], (instregex "ESDTR$")>; +def : InstRW<[FXb, VecDF, VecDF, Lat15, BeginGroup], (instregex "ESXTR$")>; + +//===----------------------------------------------------------------------===// +// DFP: Binary arithmetic +//===----------------------------------------------------------------------===// + +// Addition +def : InstRW<[VecDF], (instregex "ADTR(A)?$")>; +def : InstRW<[VecDF2, VecDF2, Lat10, GroupAlone], (instregex "AXTR(A)?$")>; + +// Subtraction +def : InstRW<[VecDF], (instregex "SDTR(A)?$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "SXTR(A)?$")>; + +// Multiply +def : InstRW<[VecDF, Lat30], (instregex "MDTR(A)?$")>; +def : InstRW<[VecDF2, VecDF2, Lat30, GroupAlone], (instregex "MXTR(A)?$")>; + +// Division +def : InstRW<[VecDF, Lat30], (instregex "DDTR(A)?$")>; +def : InstRW<[VecDF2, VecDF2, Lat30, GroupAlone], (instregex "DXTR(A)?$")>; + +// Quantize +def : InstRW<[VecDF], (instregex "QADTR$")>; +def : InstRW<[VecDF2, VecDF2, Lat11, GroupAlone], (instregex "QAXTR$")>; + +// Reround +def : InstRW<[FXb, VecDF, Lat11, BeginGroup], (instregex "RRDTR$")>; +def : InstRW<[FXb, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "RRXTR$")>; + +// Shift significand left/right +def : InstRW<[LSU, VecDF, Lat11, GroupAlone], (instregex "S(L|R)DT$")>; +def : InstRW<[LSU, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "S(L|R)XT$")>; + +// Insert biased exponent +def : InstRW<[FXb, VecDF, Lat11, BeginGroup], (instregex "IEDTR$")>; +def : InstRW<[FXb, VecDF2, VecDF2, Lat15, GroupAlone], (instregex "IEXTR$")>; + +//===----------------------------------------------------------------------===// +// DFP: Comparisons +//===----------------------------------------------------------------------===// + +// Compare +def : InstRW<[VecDF], (instregex "(K|C)DTR$")>; +def : InstRW<[VecDF, VecDF, Lat11, GroupAlone], (instregex "(K|C)XTR$")>; + +// Compare biased exponent +def : InstRW<[VecDF], (instregex "CEDTR$")>; +def : InstRW<[VecDF], (instregex "CEXTR$")>; + +// Test Data Class/Group +def : InstRW<[LSU, VecDF, Lat11], (instregex "TD(C|G)(E|D)T$")>; +def : InstRW<[LSU, VecDF, VecDF, Lat15, GroupAlone], (instregex "TD(C|G)XT$")>; + + +// --------------------------------- Vector --------------------------------- // + +//===----------------------------------------------------------------------===// +// Vector: Move instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb], (instregex "VLR(32|64)?$")>; +def : InstRW<[FXb, Lat4], (instregex "VLGV(B|F|G|H)?$")>; +def : InstRW<[FXb], (instregex "VLVG(B|F|G|H)?$")>; +def : InstRW<[FXb, Lat2], (instregex "VLVGP(32)?$")>; + +//===----------------------------------------------------------------------===// +// Vector: Immediate instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[VecXsPm], (instregex "VZERO$")>; +def : InstRW<[VecXsPm], (instregex "VONE$")>; +def : InstRW<[VecXsPm], (instregex "VGBM$")>; +def : InstRW<[VecXsPm], (instregex "VGM(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VREPI(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VLEI(B|F|G|H)$")>; + +//===----------------------------------------------------------------------===// +// Vector: Loads +//===----------------------------------------------------------------------===// + +def : InstRW<[LSU], (instregex "VL(L|BB)?$")>; +def : InstRW<[LSU], (instregex "VL(32|64)$")>; +def : InstRW<[LSU], (instregex "VLLEZ(B|F|G|H|LF)?$")>; +def : InstRW<[LSU], (instregex "VLREP(B|F|G|H)?$")>; +def : InstRW<[VecXsPm, LSU, Lat7], (instregex "VLE(B|F|G|H)$")>; +def : InstRW<[FXb, LSU, VecXsPm, Lat11, BeginGroup], (instregex "VGE(F|G)$")>; +def : InstRW<[LSU, LSU, LSU, LSU, LSU, Lat10, GroupAlone], + (instregex "VLM$")>; +def : InstRW<[LSU, Lat5], (instregex "VLRL(R)?$")>; + +//===----------------------------------------------------------------------===// +// Vector: Stores +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat8], (instregex "VST(L|32|64)?$")>; +def : InstRW<[FXb, LSU, Lat8], (instregex "VSTE(F|G)$")>; +def : InstRW<[FXb, LSU, VecXsPm, Lat11, BeginGroup], (instregex "VSTE(B|H)$")>; +def : InstRW<[LSU, LSU, FXb, FXb, FXb, FXb, FXb, Lat20, GroupAlone], + (instregex "VSTM$")>; +def : InstRW<[FXb, FXb, LSU, Lat12, BeginGroup], (instregex "VSCE(F|G)$")>; +def : InstRW<[FXb, LSU, Lat8], (instregex "VSTRL(R)?$")>; + +//===----------------------------------------------------------------------===// +// Vector: Selects and permutes +//===----------------------------------------------------------------------===// + +def : InstRW<[VecXsPm], (instregex "VMRH(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VMRL(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VPERM$")>; +def : InstRW<[VecXsPm], (instregex "VPDI$")>; +def : InstRW<[VecXsPm], (instregex "VBPERM$")>; +def : InstRW<[VecXsPm], (instregex "VREP(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VSEL$")>; + +//===----------------------------------------------------------------------===// +// Vector: Widening and narrowing +//===----------------------------------------------------------------------===// + +def : InstRW<[VecXsPm], (instregex "VPK(F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VPKS(F|G|H)?$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "VPKS(F|G|H)S$")>; +def : InstRW<[VecXsPm], (instregex "VPKLS(F|G|H)?$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "VPKLS(F|G|H)S$")>; +def : InstRW<[VecXsPm], (instregex "VSEG(B|F|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VUPH(B|F|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VUPL(B|F)?$")>; +def : InstRW<[VecXsPm], (instregex "VUPLH(B|F|H|W)?$")>; +def : InstRW<[VecXsPm], (instregex "VUPLL(B|F|H)?$")>; + +//===----------------------------------------------------------------------===// +// Vector: Integer arithmetic +//===----------------------------------------------------------------------===// + +def : InstRW<[VecXsPm], (instregex "VA(B|F|G|H|Q|C|CQ)?$")>; +def : InstRW<[VecXsPm], (instregex "VACC(B|F|G|H|Q|C|CQ)?$")>; +def : InstRW<[VecXsPm], (instregex "VAVG(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VAVGL(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VN(C|O|N|X)?$")>; +def : InstRW<[VecXsPm], (instregex "VO(C)?$")>; +def : InstRW<[VecMul], (instregex "VCKSM$")>; +def : InstRW<[VecXsPm], (instregex "VCLZ(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VCTZ(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VX$")>; +def : InstRW<[VecMul], (instregex "VGFM?$")>; +def : InstRW<[VecMul], (instregex "VGFMA(B|F|G|H)?$")>; +def : InstRW<[VecMul], (instregex "VGFM(B|F|G|H)$")>; +def : InstRW<[VecXsPm], (instregex "VLC(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VLP(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VMX(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VMXL(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VMN(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VMNL(B|F|G|H)?$")>; +def : InstRW<[VecMul], (instregex "VMAL(B|F)?$")>; +def : InstRW<[VecMul], (instregex "VMALE(B|F|H)?$")>; +def : InstRW<[VecMul], (instregex "VMALH(B|F|H|W)?$")>; +def : InstRW<[VecMul], (instregex "VMALO(B|F|H)?$")>; +def : InstRW<[VecMul], (instregex "VMAO(B|F|H)?$")>; +def : InstRW<[VecMul], (instregex "VMAE(B|F|H)?$")>; +def : InstRW<[VecMul], (instregex "VMAH(B|F|H)?$")>; +def : InstRW<[VecMul], (instregex "VME(B|F|H)?$")>; +def : InstRW<[VecMul], (instregex "VMH(B|F|H)?$")>; +def : InstRW<[VecMul], (instregex "VML(B|F)?$")>; +def : InstRW<[VecMul], (instregex "VMLE(B|F|H)?$")>; +def : InstRW<[VecMul], (instregex "VMLH(B|F|H|W)?$")>; +def : InstRW<[VecMul], (instregex "VMLO(B|F|H)?$")>; +def : InstRW<[VecMul], (instregex "VMO(B|F|H)?$")>; +def : InstRW<[VecBF2], (instregex "VMSL(G)?$")>; + +def : InstRW<[VecXsPm], (instregex "VPOPCT(B|F|G|H)?$")>; + +def : InstRW<[VecXsPm], (instregex "VERLL(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VERLLV(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VERIM(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VESL(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VESLV(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VESRA(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VESRAV(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VESRL(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VESRLV(B|F|G|H)?$")>; + +def : InstRW<[VecXsPm], (instregex "VSL(DB)?$")>; +def : InstRW<[VecXsPm, VecXsPm, Lat8], (instregex "VSLB$")>; +def : InstRW<[VecXsPm], (instregex "VSR(A|L)$")>; +def : InstRW<[VecXsPm, VecXsPm, Lat8], (instregex "VSR(A|L)B$")>; + +def : InstRW<[VecXsPm], (instregex "VSB(I|IQ|CBI|CBIQ)?$")>; +def : InstRW<[VecXsPm], (instregex "VSCBI(B|F|G|H|Q)?$")>; +def : InstRW<[VecXsPm], (instregex "VS(F|G|H|Q)?$")>; + +def : InstRW<[VecMul], (instregex "VSUM(B|H)?$")>; +def : InstRW<[VecMul], (instregex "VSUMG(F|H)?$")>; +def : InstRW<[VecMul], (instregex "VSUMQ(F|G)?$")>; + +//===----------------------------------------------------------------------===// +// Vector: Integer comparison +//===----------------------------------------------------------------------===// + +def : InstRW<[VecXsPm, Lat4], (instregex "VEC(B|F|G|H)?$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "VECL(B|F|G|H)?$")>; +def : InstRW<[VecXsPm], (instregex "VCEQ(B|F|G|H)?$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "VCEQ(B|F|G|H)S$")>; +def : InstRW<[VecXsPm], (instregex "VCH(B|F|G|H)?$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "VCH(B|F|G|H)S$")>; +def : InstRW<[VecXsPm], (instregex "VCHL(B|F|G|H)?$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "VCHL(B|F|G|H)S$")>; +def : InstRW<[VecStr, Lat5], (instregex "VTM$")>; + +//===----------------------------------------------------------------------===// +// Vector: Floating-point arithmetic +//===----------------------------------------------------------------------===// + +// Conversion and rounding +def : InstRW<[VecBF], (instregex "VCD(L)?G$")>; +def : InstRW<[VecBF], (instregex "VCD(L)?GB$")>; +def : InstRW<[VecBF], (instregex "WCD(L)?GB$")>; +def : InstRW<[VecBF], (instregex "VC(L)?GD$")>; +def : InstRW<[VecBF], (instregex "VC(L)?GDB$")>; +def : InstRW<[VecBF], (instregex "WC(L)?GDB$")>; +def : InstRW<[VecBF], (instregex "VL(DE|ED)$")>; +def : InstRW<[VecBF], (instregex "VL(DE|ED)B$")>; +def : InstRW<[VecBF], (instregex "WL(DE|ED)B$")>; +def : InstRW<[VecBF2], (instregex "VFI$")>; +def : InstRW<[VecBF], (instregex "VFIDB$")>; +def : InstRW<[VecBF], (instregex "WFIDB$")>; + +// Sign operations +def : InstRW<[VecXsPm], (instregex "VFPSO$")>; +def : InstRW<[VecXsPm], (instregex "(V|W)FPSODB$")>; +def : InstRW<[VecXsPm], (instregex "(V|W)FL(C|N|P)DB$")>; + +// Minimum / maximum +def : InstRW<[VecXsPm], (instregex "VF(MAX|MIN)$")>; +def : InstRW<[VecXsPm], (instregex "VF(MAX|MIN)DB$")>; +def : InstRW<[VecXsPm], (instregex "WF(MAX|MIN)DB$")>; + +// Test data class +def : InstRW<[VecXsPm, Lat4], (instregex "VFTCI$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "(V|W)FTCIDB$")>; + +// Add / subtract +def : InstRW<[VecBF2], (instregex "VF(A|S)$")>; +def : InstRW<[VecBF], (instregex "VF(A|S)DB$")>; +def : InstRW<[VecBF], (instregex "WF(A|S)DB$")>; + +// Multiply / multiply-and-add/subtract +def : InstRW<[VecBF2], (instregex "VFM$")>; +def : InstRW<[VecBF], (instregex "VFMDB$")>; +def : InstRW<[VecBF], (instregex "WFMDB$")>; +def : InstRW<[VecBF2], (instregex "VF(N)?M(A|S)$")>; +def : InstRW<[VecBF], (instregex "VF(N)?M(A|S)DB$")>; +def : InstRW<[VecBF], (instregex "WF(N)?M(A|S)DB$")>; + +// Divide / square root +def : InstRW<[VecFPd], (instregex "VFD$")>; +def : InstRW<[VecFPd], (instregex "(V|W)FDDB$")>; +def : InstRW<[VecFPd], (instregex "VFSQ$")>; +def : InstRW<[VecFPd], (instregex "(V|W)FSQDB$")>; + +//===----------------------------------------------------------------------===// +// Vector: Floating-point comparison +//===----------------------------------------------------------------------===// + +def : InstRW<[VecXsPm], (instregex "VF(C|K)(E|H|HE)$")>; +def : InstRW<[VecXsPm], (instregex "VF(C|K)(E|H|HE)DB$")>; +def : InstRW<[VecXsPm], (instregex "WF(C|K)(E|H|HE)DB$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "VF(C|K)(E|H|HE)DBS$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)(E|H|HE)DBS$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)$")>; +def : InstRW<[VecXsPm, Lat4], (instregex "WF(C|K)DB$")>; + +//===----------------------------------------------------------------------===// +// Vector: Floating-point insertion and extraction +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb], (instregex "LEFR$")>; +def : InstRW<[FXb, Lat4], (instregex "LFER$")>; + +//===----------------------------------------------------------------------===// +// Vector: String instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[VecStr], (instregex "VFAE(B)?$")>; +def : InstRW<[VecStr, Lat5], (instregex "VFAEBS$")>; +def : InstRW<[VecStr], (instregex "VFAE(F|H)$")>; +def : InstRW<[VecStr, Lat5], (instregex "VFAE(F|H)S$")>; +def : InstRW<[VecStr], (instregex "VFAEZ(B|F|H)$")>; +def : InstRW<[VecStr, Lat5], (instregex "VFAEZ(B|F|H)S$")>; +def : InstRW<[VecStr], (instregex "VFEE(B|F|H|ZB|ZF|ZH)?$")>; +def : InstRW<[VecStr, Lat5], (instregex "VFEE(B|F|H|ZB|ZF|ZH)S$")>; +def : InstRW<[VecStr], (instregex "VFENE(B|F|H|ZB|ZF|ZH)?$")>; +def : InstRW<[VecStr, Lat5], (instregex "VFENE(B|F|H|ZB|ZF|ZH)S$")>; +def : InstRW<[VecStr], (instregex "VISTR(B|F|H)?$")>; +def : InstRW<[VecStr, Lat5], (instregex "VISTR(B|F|H)S$")>; +def : InstRW<[VecStr], (instregex "VSTRC(B|F|H)?$")>; +def : InstRW<[VecStr, Lat5], (instregex "VSTRC(B|F|H)S$")>; +def : InstRW<[VecStr], (instregex "VSTRCZ(B|F|H)$")>; +def : InstRW<[VecStr, Lat5], (instregex "VSTRCZ(B|F|H)S$")>; + +//===----------------------------------------------------------------------===// +// Vector: Packed-decimal instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[VecDF, VecDF, Lat10, GroupAlone], (instregex "VLIP$")>; +def : InstRW<[VecDFX, LSU, Lat12, GroupAlone], (instregex "VPKZ$")>; +def : InstRW<[VecDFX, FXb, LSU, Lat12, GroupAlone], (instregex "VUPKZ$")>; +def : InstRW<[VecDF, VecDF, FXb, Lat20, GroupAlone], (instregex "VCVB(G)?$")>; +def : InstRW<[VecDF, VecDF, FXb, Lat20, GroupAlone], (instregex "VCVD(G)?$")>; +def : InstRW<[VecDFX], (instregex "V(A|S)P$")>; +def : InstRW<[VecDF, VecDF, Lat30, GroupAlone], (instregex "VM(S)?P$")>; +def : InstRW<[VecDF, VecDF, Lat30, GroupAlone], (instregex "V(D|R)P$")>; +def : InstRW<[VecDFX, Lat30, GroupAlone], (instregex "VSDP$")>; +def : InstRW<[VecDF, VecDF, Lat11], (instregex "VSRP$")>; +def : InstRW<[VecDFX], (instregex "VPSOP$")>; +def : InstRW<[VecDFX], (instregex "V(T|C)P$")>; + + +// -------------------------------- System ---------------------------------- // + +//===----------------------------------------------------------------------===// +// System: Program-Status Word Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "EPSW$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "LPSW(E)?$")>; +def : InstRW<[FXa, Lat3, GroupAlone], (instregex "IPK$")>; +def : InstRW<[LSU, EndGroup], (instregex "SPKA$")>; +def : InstRW<[LSU, EndGroup], (instregex "SSM$")>; +def : InstRW<[FXb, LSU, GroupAlone], (instregex "ST(N|O)SM$")>; +def : InstRW<[FXa, Lat3], (instregex "IAC$")>; +def : InstRW<[LSU, EndGroup], (instregex "SAC(F)?$")>; + +//===----------------------------------------------------------------------===// +// System: Control Register Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "LCTL(G)?$")>; +def : InstRW<[LSU, Lat30], (instregex "STCT(L|G)$")>; +def : InstRW<[LSU], (instregex "E(P|S)A(I)?R$")>; +def : InstRW<[FXb, Lat30], (instregex "SSA(I)?R$")>; +def : InstRW<[FXb, Lat30], (instregex "ESEA$")>; + +//===----------------------------------------------------------------------===// +// System: Prefix-Register Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "SPX$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STPX$")>; + +//===----------------------------------------------------------------------===// +// System: Storage-Key and Real Memory Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "ISKE$")>; +def : InstRW<[FXb, Lat30], (instregex "IVSK$")>; +def : InstRW<[FXb, Lat30], (instregex "SSKE(Opt)?$")>; +def : InstRW<[FXb, Lat30], (instregex "RRB(E|M)$")>; +def : InstRW<[FXb, Lat30], (instregex "IRBM$")>; +def : InstRW<[FXb, Lat30], (instregex "PFMF$")>; +def : InstRW<[FXb, Lat30], (instregex "TB$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "PGIN$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "PGOUT$")>; + +//===----------------------------------------------------------------------===// +// System: Dynamic-Address-Translation Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "IPTE(Opt)?(Opt)?$")>; +def : InstRW<[FXb, Lat30], (instregex "IDTE(Opt)?$")>; +def : InstRW<[FXb, Lat30], (instregex "CRDTE(Opt)?$")>; +def : InstRW<[FXb, Lat30], (instregex "PTLB$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "CSP(G)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "LPTEA$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "LRA(Y|G)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STRAG$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "LURA(G)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STUR(A|G)$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "TPROT$")>; + +//===----------------------------------------------------------------------===// +// System: Memory-move Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXa, FXa, FXb, LSU, Lat8, GroupAlone], (instregex "MVC(K|P|S)$")>; +def : InstRW<[FXa, LSU, Lat6, GroupAlone], (instregex "MVC(S|D)K$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "MVCOS$")>; +def : InstRW<[LSU, Lat30, GroupAlone], (instregex "MVPG$")>; + +//===----------------------------------------------------------------------===// +// System: Address-Space Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "LASP$")>; +def : InstRW<[LSU, GroupAlone], (instregex "PALB$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "PC$")>; +def : InstRW<[FXb, Lat30], (instregex "PR$")>; +def : InstRW<[FXb, Lat30], (instregex "PT(I)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "RP$")>; +def : InstRW<[FXb, Lat30], (instregex "BS(G|A)$")>; +def : InstRW<[FXb, Lat20], (instregex "TAR$")>; + +//===----------------------------------------------------------------------===// +// System: Linkage-Stack Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30, EndGroup], (instregex "BAKR$")>; +def : InstRW<[FXb, Lat30], (instregex "EREG(G)?$")>; +def : InstRW<[FXb, Lat30], (instregex "(E|M)STA$")>; + +//===----------------------------------------------------------------------===// +// System: Time-Related Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "PTFF$")>; +def : InstRW<[FXb, LSU, Lat20], (instregex "SCK$")>; +def : InstRW<[FXb, Lat30], (instregex "SCKPF$")>; +def : InstRW<[FXb, LSU, Lat20], (instregex "SCKC$")>; +def : InstRW<[LSU, LSU, GroupAlone], (instregex "SPT$")>; +def : InstRW<[LSU, LSU, LSU, FXa, FXa, FXb, Lat9, GroupAlone], + (instregex "STCK(F)?$")>; +def : InstRW<[LSU, LSU, LSU, LSU, FXa, FXa, FXb, FXb, Lat11, GroupAlone], + (instregex "STCKE$")>; +def : InstRW<[FXb, LSU, Lat9], (instregex "STCKC$")>; +def : InstRW<[LSU, LSU, FXb, Lat5, BeginGroup], (instregex "STPT$")>; + +//===----------------------------------------------------------------------===// +// System: CPU-Related Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, LSU, Lat30], (instregex "STAP$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STIDP$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STSI$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STFL(E)?$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "ECAG$")>; +def : InstRW<[FXa, LSU, Lat30], (instregex "ECTG$")>; +def : InstRW<[FXb, Lat30], (instregex "PTF$")>; +def : InstRW<[FXb, Lat30], (instregex "PCKMO$")>; + +//===----------------------------------------------------------------------===// +// System: Miscellaneous Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "SVC$")>; +def : InstRW<[FXb, GroupAlone], (instregex "MC$")>; +def : InstRW<[FXb, Lat30], (instregex "DIAG$")>; +def : InstRW<[FXb], (instregex "TRAC(E|G)$")>; +def : InstRW<[FXb, Lat30], (instregex "TRAP(2|4)$")>; +def : InstRW<[FXb, Lat30], (instregex "SIGP$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "SIGA$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "SIE$")>; + +//===----------------------------------------------------------------------===// +// System: CPU-Measurement Facility Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb], (instregex "LPP$")>; +def : InstRW<[FXb, Lat30], (instregex "ECPGA$")>; +def : InstRW<[FXb, Lat30], (instregex "E(C|P)CTR$")>; +def : InstRW<[FXb, Lat30], (instregex "LCCTL$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "L(P|S)CTL$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "Q(S|CTR)I$")>; +def : InstRW<[FXb, Lat30], (instregex "S(C|P)CTR$")>; + +//===----------------------------------------------------------------------===// +// System: I/O Instructions +//===----------------------------------------------------------------------===// + +def : InstRW<[FXb, Lat30], (instregex "(C|H|R|X)SCH$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "(M|S|ST|T)SCH$")>; +def : InstRW<[FXb, Lat30], (instregex "RCHP$")>; +def : InstRW<[FXb, Lat30], (instregex "SCHM$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "STC(PS|RW)$")>; +def : InstRW<[FXb, LSU, Lat30], (instregex "TPI$")>; +def : InstRW<[FXb, Lat30], (instregex "SAL$")>; + +} + diff --git a/lib/Target/SystemZ/SystemZSubtarget.cpp b/lib/Target/SystemZ/SystemZSubtarget.cpp index eb4a0962f7e..9cd09b0f911 100644 --- a/lib/Target/SystemZ/SystemZSubtarget.cpp +++ b/lib/Target/SystemZ/SystemZSubtarget.cpp @@ -47,6 +47,10 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU, HasVector(false), HasLoadStoreOnCond2(false), HasLoadAndZeroRightmostByte(false), HasMessageSecurityAssist5(false), HasDFPPackedConversion(false), + HasMiscellaneousExtensions2(false), HasGuardedStorage(false), + HasMessageSecurityAssist7(false), HasMessageSecurityAssist8(false), + HasVectorEnhancements1(false), HasVectorPackedDecimal(false), + HasInsertReferenceBitsMultiple(false), TargetTriple(TT), InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), TSInfo(), FrameLowering() {} diff --git a/lib/Target/SystemZ/SystemZSubtarget.h b/lib/Target/SystemZ/SystemZSubtarget.h index b05a1bb6caf..4829f73e080 100644 --- a/lib/Target/SystemZ/SystemZSubtarget.h +++ b/lib/Target/SystemZ/SystemZSubtarget.h @@ -56,6 +56,13 @@ protected: bool HasLoadAndZeroRightmostByte; bool HasMessageSecurityAssist5; bool HasDFPPackedConversion; + bool HasMiscellaneousExtensions2; + bool HasGuardedStorage; + bool HasMessageSecurityAssist7; + bool HasMessageSecurityAssist8; + bool HasVectorEnhancements1; + bool HasVectorPackedDecimal; + bool HasInsertReferenceBitsMultiple; private: Triple TargetTriple; @@ -168,6 +175,33 @@ public: // Return true if the target has the vector facility. bool hasVector() const { return HasVector; } + // Return true if the target has the miscellaneous-extensions facility 2. + bool hasMiscellaneousExtensions2() const { + return HasMiscellaneousExtensions2; + } + + // Return true if the target has the guarded-storage facility. + bool hasGuardedStorage() const { return HasGuardedStorage; } + + // Return true if the target has the message-security-assist + // extension facility 7. + bool hasMessageSecurityAssist7() const { return HasMessageSecurityAssist7; } + + // Return true if the target has the message-security-assist + // extension facility 8. + bool hasMessageSecurityAssist8() const { return HasMessageSecurityAssist8; } + + // Return true if the target has the vector-enhancements facility 1. + bool hasVectorEnhancements1() const { return HasVectorEnhancements1; } + + // Return true if the target has the vector-packed-decimal facility. + bool hasVectorPackedDecimal() const { return HasVectorPackedDecimal; } + + // Return true if the target has the insert-reference-bits-multiple facility. + bool hasInsertReferenceBitsMultiple() const { + return HasInsertReferenceBitsMultiple; + } + // Return true if GV can be accessed using LARL for reloc model RM // and code model CM. bool isPC32DBLSymbol(const GlobalValue *GV, CodeModel::Model CM) const; diff --git a/test/CodeGen/SystemZ/branch-11.ll b/test/CodeGen/SystemZ/branch-11.ll new file mode 100644 index 00000000000..ce7b3ef267b --- /dev/null +++ b/test/CodeGen/SystemZ/branch-11.ll @@ -0,0 +1,56 @@ +; Test indirect jumps on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +define i32 @f1(i32 %x, i32 %y, i32 %op) { +; CHECK-LABEL: f1: +; CHECK: ahi %r4, -1 +; CHECK: clibh %r4, 5, 0(%r14) +; CHECK: llgfr [[OP64:%r[0-5]]], %r4 +; CHECK: sllg [[INDEX:%r[1-5]]], [[OP64]], 3 +; CHECK: larl [[BASE:%r[1-5]]] +; CHECK: bi 0([[BASE]],[[INDEX]]) +entry: + switch i32 %op, label %exit [ + i32 1, label %b.add + i32 2, label %b.sub + i32 3, label %b.and + i32 4, label %b.or + i32 5, label %b.xor + i32 6, label %b.mul + ] + +b.add: + %add = add i32 %x, %y + br label %exit + +b.sub: + %sub = sub i32 %x, %y + br label %exit + +b.and: + %and = and i32 %x, %y + br label %exit + +b.or: + %or = or i32 %x, %y + br label %exit + +b.xor: + %xor = xor i32 %x, %y + br label %exit + +b.mul: + %mul = mul i32 %x, %y + br label %exit + +exit: + %res = phi i32 [ %x, %entry ], + [ %add, %b.add ], + [ %sub, %b.sub ], + [ %and, %b.and ], + [ %or, %b.or ], + [ %xor, %b.xor ], + [ %mul, %b.mul ] + ret i32 %res +} diff --git a/test/CodeGen/SystemZ/fp-mul-10.ll b/test/CodeGen/SystemZ/fp-mul-10.ll new file mode 100644 index 00000000000..977e5c60e3a --- /dev/null +++ b/test/CodeGen/SystemZ/fp-mul-10.ll @@ -0,0 +1,23 @@ +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare double @llvm.fma.f64(double %f1, double %f2, double %f3) + +define double @f1(double %f1, double %f2, double %acc) { +; CHECK-LABEL: f1: +; CHECK: wfnmadb %f0, %f0, %f2, %f4 +; CHECK: br %r14 + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %acc) + %negres = fsub double -0.0, %res + ret double %negres +} + +define double @f2(double %f1, double %f2, double %acc) { +; CHECK-LABEL: f2: +; CHECK: wfnmsdb %f0, %f0, %f2, %f4 +; CHECK: br %r14 + %negacc = fsub double -0.0, %acc + %res = call double @llvm.fma.f64 (double %f1, double %f2, double %negacc) + %negres = fsub double -0.0, %res + ret double %negres +} + diff --git a/test/CodeGen/SystemZ/int-add-17.ll b/test/CodeGen/SystemZ/int-add-17.ll new file mode 100644 index 00000000000..fd245871c65 --- /dev/null +++ b/test/CodeGen/SystemZ/int-add-17.ll @@ -0,0 +1,95 @@ +; Test additions between an i64 and a sign-extended i16 on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare i64 @foo() + +; Check AGH with no displacement. +define i64 @f1(i64 %a, i16 *%src) { +; CHECK-LABEL: f1: +; CHECK: agh %r2, 0(%r3) +; CHECK: br %r14 + %b = load i16, i16 *%src + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the high end of the aligned AGH range. +define i64 @f2(i64 %a, i16 *%src) { +; CHECK-LABEL: f2: +; CHECK: agh %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262143 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f3(i64 %a, i16 *%src) { +; CHECK-LABEL: f3: +; CHECK: agfi %r3, 524288 +; CHECK: agh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the high end of the negative aligned AGH range. +define i64 @f4(i64 %a, i16 *%src) { +; CHECK-LABEL: f4: +; CHECK: agh %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -1 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the low end of the AGH range. +define i64 @f5(i64 %a, i16 *%src) { +; CHECK-LABEL: f5: +; CHECK: agh %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 %a, i16 *%src) { +; CHECK-LABEL: f6: +; CHECK: agfi %r3, -524290 +; CHECK: agh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + +; Check that AGH allows an index. +define i64 @f7(i64 %a, i64 %src, i64 %index) { +; CHECK-LABEL: f7: +; CHECK: agh %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i16 * + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %add = add i64 %a, %bext + ret i64 %add +} + diff --git a/test/CodeGen/SystemZ/int-mul-09.ll b/test/CodeGen/SystemZ/int-mul-09.ll new file mode 100644 index 00000000000..3e384e72db5 --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-09.ll @@ -0,0 +1,95 @@ +; Test multiplications between an i64 and a sign-extended i16 on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare i64 @foo() + +; Check MGH with no displacement. +define i64 @f1(i64 %a, i16 *%src) { +; CHECK-LABEL: f1: +; CHECK: mgh %r2, 0(%r3) +; CHECK: br %r14 + %b = load i16, i16 *%src + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the high end of the aligned MGH range. +define i64 @f2(i64 %a, i16 *%src) { +; CHECK-LABEL: f2: +; CHECK: mgh %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262143 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f3(i64 %a, i16 *%src) { +; CHECK-LABEL: f3: +; CHECK: agfi %r3, 524288 +; CHECK: mgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the high end of the negative aligned MGH range. +define i64 @f4(i64 %a, i16 *%src) { +; CHECK-LABEL: f4: +; CHECK: mgh %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -1 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the low end of the MGH range. +define i64 @f5(i64 %a, i16 *%src) { +; CHECK-LABEL: f5: +; CHECK: mgh %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 %a, i16 *%src) { +; CHECK-LABEL: f6: +; CHECK: agfi %r3, -524290 +; CHECK: mgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + +; Check that MGH allows an index. +define i64 @f7(i64 %a, i64 %src, i64 %index) { +; CHECK-LABEL: f7: +; CHECK: mgh %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i16 * + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + diff --git a/test/CodeGen/SystemZ/int-mul-10.ll b/test/CodeGen/SystemZ/int-mul-10.ll new file mode 100644 index 00000000000..a4d80af36a3 --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-10.ll @@ -0,0 +1,165 @@ +; Test signed high-part i64->i128 multiplications on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare i64 @foo() + +; Check sign-extended multiplication in which only the high part is used. +define i64 @f1(i64 %dummy, i64 %a, i64 %b) { +; CHECK-LABEL: f1: +; CHECK-NOT: {{%r[234]}} +; CHECK: mgrk %r2, %r3, %r4 +; CHECK: br %r14 + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check sign-extended multiplication in which only part of the high half +; is used. +define i64 @f2(i64 %dummy, i64 %a, i64 %b) { +; CHECK-LABEL: f2: +; CHECK-NOT: {{%r[234]}} +; CHECK: mgrk [[REG:%r[0-9]+]], %r3, %r4 +; CHECK: srlg %r2, [[REG]], 3 +; CHECK: br %r14 + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 67 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check sign-extended multiplication in which the result is split into +; high and low halves. +define i64 @f3(i64 %dummy, i64 %a, i64 %b) { +; CHECK-LABEL: f3: +; CHECK-NOT: {{%r[234]}} +; CHECK: mgrk %r2, %r3, %r4 +; CHECK: ogr %r2, %r3 +; CHECK: br %r14 + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + %low = trunc i128 %mulx to i64 + %or = or i64 %high, %low + ret i64 %or +} + +; Check MG with no displacement. +define i64 @f4(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f4: +; CHECK-NOT: {{%r[234]}} +; CHECK: mg %r2, 0(%r4) +; CHECK: br %r14 + %b = load i64 , i64 *%src + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the high end of the aligned MG range. +define i64 @f5(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f5: +; CHECK: mg %r2, 524280(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 65535 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the next doubleword up, which requires separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f6: +; CHECK: agfi %r4, 524288 +; CHECK: mg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 65536 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the high end of the negative aligned MG range. +define i64 @f7(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f7: +; CHECK: mg %r2, -8(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 -1 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the low end of the MG range. +define i64 @f8(i64 %dummy, i64 %a, i64 *%src) { +; CHECK-LABEL: f8: +; CHECK: mg %r2, -524288(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 -65536 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check the next doubleword down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f9(i64 *%dest, i64 %a, i64 *%src) { +; CHECK-LABEL: f9: +; CHECK: agfi %r4, -524296 +; CHECK: mg %r2, 0(%r4) +; CHECK: br %r14 + %ptr = getelementptr i64, i64 *%src, i64 -65537 + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + +; Check that MG allows an index. +define i64 @f10(i64 *%dest, i64 %a, i64 %src, i64 %index) { +; CHECK-LABEL: f10: +; CHECK: mg %r2, 524287(%r5,%r4) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524287 + %ptr = inttoptr i64 %add2 to i64 * + %b = load i64 , i64 *%ptr + %ax = sext i64 %a to i128 + %bx = sext i64 %b to i128 + %mulx = mul i128 %ax, %bx + %highx = lshr i128 %mulx, 64 + %high = trunc i128 %highx to i64 + ret i64 %high +} + diff --git a/test/CodeGen/SystemZ/int-mul-11.ll b/test/CodeGen/SystemZ/int-mul-11.ll new file mode 100644 index 00000000000..f2625198251 --- /dev/null +++ b/test/CodeGen/SystemZ/int-mul-11.ll @@ -0,0 +1,32 @@ +; Test three-operand multiplication instructions on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Check MSRKC. +define i32 @f1(i32 %dummy, i32 %a, i32 %b) { +; CHECK-LABEL: f1: +; CHECK: msrkc %r2, %r3, %r4 +; CHECK: br %r14 + %mul = mul i32 %a, %b + ret i32 %mul +} + +; Check MSGRKC. +define i64 @f2(i64 %dummy, i64 %a, i64 %b) { +; CHECK-LABEL: f2: +; CHECK: msgrkc %r2, %r3, %r4 +; CHECK: br %r14 + %mul = mul i64 %a, %b + ret i64 %mul +} + +; Verify that we still use MSGFR for i32->i64 multiplies. +define i64 @f3(i64 %a, i32 %b) { +; CHECK-LABEL: f3: +; CHECK: msgfr %r2, %r3 +; CHECK: br %r14 + %bext = sext i32 %b to i64 + %mul = mul i64 %a, %bext + ret i64 %mul +} + diff --git a/test/CodeGen/SystemZ/int-sub-10.ll b/test/CodeGen/SystemZ/int-sub-10.ll new file mode 100644 index 00000000000..bf6638575e5 --- /dev/null +++ b/test/CodeGen/SystemZ/int-sub-10.ll @@ -0,0 +1,95 @@ +; Test subtractions of a sign-extended i16 from an i64 on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare i64 @foo() + +; Check SGH with no displacement. +define i64 @f1(i64 %a, i16 *%src) { +; CHECK-LABEL: f1: +; CHECK: sgh %r2, 0(%r3) +; CHECK: br %r14 + %b = load i16, i16 *%src + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the high end of the aligned SGH range. +define i64 @f2(i64 %a, i16 *%src) { +; CHECK-LABEL: f2: +; CHECK: sgh %r2, 524286(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262143 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the next word up, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f3(i64 %a, i16 *%src) { +; CHECK-LABEL: f3: +; CHECK: agfi %r3, 524288 +; CHECK: sgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the high end of the negative aligned SGH range. +define i64 @f4(i64 %a, i16 *%src) { +; CHECK-LABEL: f4: +; CHECK: sgh %r2, -2(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -1 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the low end of the SGH range. +define i64 @f5(i64 %a, i16 *%src) { +; CHECK-LABEL: f5: +; CHECK: sgh %r2, -524288(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262144 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check the next word down, which needs separate address logic. +; Other sequences besides this one would be OK. +define i64 @f6(i64 %a, i16 *%src) { +; CHECK-LABEL: f6: +; CHECK: agfi %r3, -524290 +; CHECK: sgh %r2, 0(%r3) +; CHECK: br %r14 + %ptr = getelementptr i16, i16 *%src, i64 -262145 + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + +; Check that SGH allows an index. +define i64 @f7(i64 %a, i64 %src, i64 %index) { +; CHECK-LABEL: f7: +; CHECK: sgh %r2, 524284({{%r4,%r3|%r3,%r4}}) +; CHECK: br %r14 + %add1 = add i64 %src, %index + %add2 = add i64 %add1, 524284 + %ptr = inttoptr i64 %add2 to i16 * + %b = load i16, i16 *%ptr + %bext = sext i16 %b to i64 + %sub = sub i64 %a, %bext + ret i64 %sub +} + diff --git a/test/CodeGen/SystemZ/vec-and-04.ll b/test/CodeGen/SystemZ/vec-and-04.ll new file mode 100644 index 00000000000..e9355beb429 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-and-04.ll @@ -0,0 +1,47 @@ +; Test vector NAND on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Test a v16i8 NAND. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vnn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <16 x i8> %val1, %val2 + %not = xor <16 x i8> %ret, + ret <16 x i8> %not +} + +; Test a v8i16 NAND. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vnn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <8 x i16> %val1, %val2 + %not = xor <8 x i16> %ret, + ret <8 x i16> %not +} + +; Test a v4i32 NAND. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vnn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <4 x i32> %val1, %val2 + %not = xor <4 x i32> %ret, + ret <4 x i32> %not +} + +; Test a v2i64 NAND. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vnn %v24, %v26, %v28 +; CHECK: br %r14 + %ret = and <2 x i64> %val1, %val2 + %not = xor <2 x i64> %ret, + ret <2 x i64> %not +} diff --git a/test/CodeGen/SystemZ/vec-ctpop-02.ll b/test/CodeGen/SystemZ/vec-ctpop-02.ll new file mode 100644 index 00000000000..ee50e88d043 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-ctpop-02.ll @@ -0,0 +1,45 @@ +; Test vector population-count instruction on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a) +declare <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %a) +declare <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a) +declare <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a) + +define <16 x i8> @f1(<16 x i8> %a) { +; CHECK-LABEL: f1: +; CHECK: vpopctb %v24, %v24 +; CHECK: br %r14 + + %popcnt = call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %a) + ret <16 x i8> %popcnt +} + +define <8 x i16> @f2(<8 x i16> %a) { +; CHECK-LABEL: f2: +; CHECK: vpopcth %v24, %v24 +; CHECK: br %r14 + + %popcnt = call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %a) + ret <8 x i16> %popcnt +} + +define <4 x i32> @f3(<4 x i32> %a) { +; CHECK-LABEL: f3: +; CHECK: vpopctf %v24, %v24 +; CHECK: br %r14 + + %popcnt = call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %a) + ret <4 x i32> %popcnt +} + +define <2 x i64> @f4(<2 x i64> %a) { +; CHECK-LABEL: f4: +; CHECK: vpopctg %v24, %v24 +; CHECK: br %r14 + + %popcnt = call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %a) + ret <2 x i64> %popcnt +} + diff --git a/test/CodeGen/SystemZ/vec-intrinsics.ll b/test/CodeGen/SystemZ/vec-intrinsics-01.ll similarity index 100% rename from test/CodeGen/SystemZ/vec-intrinsics.ll rename to test/CodeGen/SystemZ/vec-intrinsics-01.ll diff --git a/test/CodeGen/SystemZ/vec-intrinsics-02.ll b/test/CodeGen/SystemZ/vec-intrinsics-02.ll new file mode 100644 index 00000000000..27ee83fc774 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-intrinsics-02.ll @@ -0,0 +1,212 @@ +; Test vector intrinsics added with z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare <2 x i64> @llvm.s390.vbperm(<16 x i8>, <16 x i8>) +declare <16 x i8> @llvm.s390.vmslg(<2 x i64>, <2 x i64>, <16 x i8>, i32) +declare <16 x i8> @llvm.s390.vlrl(i32, i8 *) +declare void @llvm.s390.vstrl(<16 x i8>, i32, i8 *) +declare <2 x double> @llvm.s390.vfmaxdb(<2 x double>, <2 x double>, i32) +declare <2 x double> @llvm.s390.vfmindb(<2 x double>, <2 x double>, i32) + +; VBPERM. +define <2 x i64> @test_vbperm(<16 x i8> %a, <16 x i8> %b) { +; CHECK-LABEL: test_vbperm: +; CHECK: vbperm %v24, %v24, %v26 +; CHECK: br %r14 + %res = call <2 x i64> @llvm.s390.vbperm(<16 x i8> %a, <16 x i8> %b) + ret <2 x i64> %res +} + +; VMSLG with no shifts. +define <16 x i8> @test_vmslg1(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vmslg1: +; CHECK: vmslg %v24, %v24, %v26, %v28, 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c, i32 0) + ret <16 x i8> %res +} + +; VMSLG with both shifts. +define <16 x i8> @test_vmslg2(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c) { +; CHECK-LABEL: test_vmslg2: +; CHECK: vmslg %v24, %v24, %v26, %v28, 12 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vmslg(<2 x i64> %a, <2 x i64> %b, <16 x i8> %c, i32 12) + ret <16 x i8> %res +} + +; VLRLR with the lowest in-range displacement. +define <16 x i8> @test_vlrlr1(i8 *%ptr, i32 %length) { +; CHECK-LABEL: test_vlrlr1: +; CHECK: vlrlr %v24, %r3, 0(%r2) +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRLR with the highest in-range displacement. +define <16 x i8> @test_vlrlr2(i8 *%base, i32 %length) { +; CHECK-LABEL: test_vlrlr2: +; CHECK: vlrlr %v24, %r3, 4095(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRLR with an out-of-range displacement. +define <16 x i8> @test_vlrlr3(i8 *%base, i32 %length) { +; CHECK-LABEL: test_vlrlr3: +; CHECK: vlrlr %v24, %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; Check that VLRLR doesn't allow an index. +define <16 x i8> @test_vlrlr4(i8 *%base, i64 %index, i32 %length) { +; CHECK-LABEL: test_vlrlr4: +; CHECK: vlrlr %v24, %r4, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + %res = call <16 x i8> @llvm.s390.vlrl(i32 %length, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRL with the lowest in-range displacement. +define <16 x i8> @test_vlrl1(i8 *%ptr) { +; CHECK-LABEL: test_vlrl1: +; CHECK: vlrl %v24, 0(%r2), 0 +; CHECK: br %r14 + %res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRL with the highest in-range displacement. +define <16 x i8> @test_vlrl2(i8 *%base) { +; CHECK-LABEL: test_vlrl2: +; CHECK: vlrl %v24, 4095(%r2), 0 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + %res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr) + ret <16 x i8> %res +} + +; VLRL with an out-of-range displacement. +define <16 x i8> @test_vlrl3(i8 *%base) { +; CHECK-LABEL: test_vlrl3: +; CHECK: vlrl %v24, 0({{%r[1-5]}}), 0 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + %res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr) + ret <16 x i8> %res +} + +; Check that VLRL doesn't allow an index. +define <16 x i8> @test_vlrl4(i8 *%base, i64 %index) { +; CHECK-LABEL: test_vlrl4: +; CHECK: vlrl %v24, 0({{%r[1-5]}}), 0 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + %res = call <16 x i8> @llvm.s390.vlrl(i32 0, i8 *%ptr) + ret <16 x i8> %res +} + +; VSTRLR with the lowest in-range displacement. +define void @test_vstrlr1(<16 x i8> %vec, i8 *%ptr, i32 %length) { +; CHECK-LABEL: test_vstrlr1: +; CHECK: vstrlr %v24, %r3, 0(%r2) +; CHECK: br %r14 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; VSTRLR with the highest in-range displacement. +define void @test_vstrlr2(<16 x i8> %vec, i8 *%base, i32 %length) { +; CHECK-LABEL: test_vstrlr2: +; CHECK: vstrlr %v24, %r3, 4095(%r2) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; VSTRLR with an out-of-range displacement. +define void @test_vstrlr3(<16 x i8> %vec, i8 *%base, i32 %length) { +; CHECK-LABEL: test_vstrlr3: +; CHECK: vstrlr %v24, %r3, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; Check that VSTRLR doesn't allow an index. +define void @test_vstrlr4(<16 x i8> %vec, i8 *%base, i64 %index, i32 %length) { +; CHECK-LABEL: test_vstrlr4: +; CHECK: vstrlr %v24, %r4, 0({{%r[1-5]}}) +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 %length, i8 *%ptr) + ret void +} + +; VSTRL with the lowest in-range displacement. +define void @test_vstrl1(<16 x i8> %vec, i8 *%ptr) { +; CHECK-LABEL: test_vstrl1: +; CHECK: vstrl %v24, 0(%r2), 8 +; CHECK: br %r14 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr) + ret void +} + +; VSTRL with the highest in-range displacement. +define void @test_vstrl2(<16 x i8> %vec, i8 *%base) { +; CHECK-LABEL: test_vstrl2: +; CHECK: vstrl %v24, 4095(%r2), 8 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4095 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr) + ret void +} + +; VSTRL with an out-of-range displacement. +define void @test_vstrl3(<16 x i8> %vec, i8 *%base) { +; CHECK-LABEL: test_vstrl3: +; CHECK: vstrl %v24, 0({{%r[1-5]}}), 8 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 4096 + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr) + ret void +} + +; Check that VSTRL doesn't allow an index. +define void @test_vstrl4(<16 x i8> %vec, i8 *%base, i64 %index) { +; CHECK-LABEL: test_vstrl4: +; CHECK: vstrl %v24, 0({{%r[1-5]}}), 8 +; CHECK: br %r14 + %ptr = getelementptr i8, i8 *%base, i64 %index + call void @llvm.s390.vstrl(<16 x i8> %vec, i32 8, i8 *%ptr) + ret void +} + +; VFMAXDB. +define <2 x double> @test_vfmaxdb(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfmaxdb: +; CHECK: vfmaxdb %v24, %v24, %v26, 4 +; CHECK: br %r14 + %res = call <2 x double> @llvm.s390.vfmaxdb(<2 x double> %a, <2 x double> %b, i32 4) + ret <2 x double> %res +} + +; VFMINDB. +define <2 x double> @test_vfmindb(<2 x double> %a, <2 x double> %b) { +; CHECK-LABEL: test_vfmindb: +; CHECK: vfmindb %v24, %v24, %v26, 4 +; CHECK: br %r14 + %res = call <2 x double> @llvm.s390.vfmindb(<2 x double> %a, <2 x double> %b, i32 4) + ret <2 x double> %res +} + diff --git a/test/CodeGen/SystemZ/vec-max-05.ll b/test/CodeGen/SystemZ/vec-max-05.ll new file mode 100644 index 00000000000..44efac76423 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-max-05.ll @@ -0,0 +1,58 @@ +; Test vector maximum on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare double @fmax(double, double) +declare double @llvm.maxnum.f64(double, double) +declare <2 x double> @llvm.maxnum.v2f64(<2 x double>, <2 x double>) + +; Test the fmax library function. +define double @f1(double %dummy, double %val1, double %val2) { +; CHECK-LABEL: f1: +; CHECK: wfmaxdb %f0, %f2, %f4, 4 +; CHECK: br %r14 + %ret = call double @fmax(double %val1, double %val2) readnone + ret double %ret +} + +; Test the f64 maxnum intrinsic. +define double @f2(double %dummy, double %val1, double %val2) { +; CHECK-LABEL: f2: +; CHECK: wfmaxdb %f0, %f2, %f4, 4 +; CHECK: br %r14 + %ret = call double @llvm.maxnum.f64(double %val1, double %val2) + ret double %ret +} + +; Test a f64 constant compare/select resulting in maxnum. +define double @f3(double %dummy, double %val) { +; CHECK-LABEL: f3: +; CHECK: lzdr [[REG:%f[0-9]+]] +; CHECK: wfmaxdb %f0, %f2, [[REG]], 4 +; CHECK: br %r14 + %cmp = fcmp ogt double %val, 0.0 + %ret = select i1 %cmp, double %val, double 0.0 + ret double %ret +} + +; Test a f64 constant compare/select resulting in maxnan. +define double @f4(double %dummy, double %val) { +; CHECK-LABEL: f4: +; CHECK: lzdr [[REG:%f[0-9]+]] +; CHECK: wfmaxdb %f0, %f2, [[REG]], 1 +; CHECK: br %r14 + %cmp = fcmp ugt double %val, 0.0 + %ret = select i1 %cmp, double %val, double 0.0 + ret double %ret +} + +; Test the v2f64 maxnum intrinsic. +define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f5: +; CHECK: vfmaxdb %v24, %v26, %v28, 4 +; CHECK: br %r14 + %ret = call <2 x double> @llvm.maxnum.v2f64(<2 x double> %val1, <2 x double> %val2) + ret <2 x double> %ret +} + diff --git a/test/CodeGen/SystemZ/vec-min-05.ll b/test/CodeGen/SystemZ/vec-min-05.ll new file mode 100644 index 00000000000..c2d8726addf --- /dev/null +++ b/test/CodeGen/SystemZ/vec-min-05.ll @@ -0,0 +1,58 @@ +; Test vector minimum on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare double @fmin(double, double) +declare double @llvm.minnum.f64(double, double) +declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>) + +; Test the fmin library function. +define double @f1(double %dummy, double %val1, double %val2) { +; CHECK-LABEL: f1: +; CHECK: wfmindb %f0, %f2, %f4, 4 +; CHECK: br %r14 + %ret = call double @fmin(double %val1, double %val2) readnone + ret double %ret +} + +; Test the f64 minnum intrinsic. +define double @f2(double %dummy, double %val1, double %val2) { +; CHECK-LABEL: f2: +; CHECK: wfmindb %f0, %f2, %f4, 4 +; CHECK: br %r14 + %ret = call double @llvm.minnum.f64(double %val1, double %val2) + ret double %ret +} + +; Test a f64 constant compare/select resulting in minnum. +define double @f3(double %dummy, double %val) { +; CHECK-LABEL: f3: +; CHECK: lzdr [[REG:%f[0-9]+]] +; CHECK: wfmindb %f0, %f2, [[REG]], 4 +; CHECK: br %r14 + %cmp = fcmp olt double %val, 0.0 + %ret = select i1 %cmp, double %val, double 0.0 + ret double %ret +} + +; Test a f64 constant compare/select resulting in minnan. +define double @f4(double %dummy, double %val) { +; CHECK-LABEL: f4: +; CHECK: lzdr [[REG:%f[0-9]+]] +; CHECK: wfmindb %f0, %f2, [[REG]], 1 +; CHECK: br %r14 + %cmp = fcmp ult double %val, 0.0 + %ret = select i1 %cmp, double %val, double 0.0 + ret double %ret +} + +; Test the v2f64 minnum intrinsic. +define <2 x double> @f5(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2) { +; CHECK-LABEL: f5: +; CHECK: vfmindb %v24, %v26, %v28, 4 +; CHECK: br %r14 + %ret = call <2 x double> @llvm.minnum.v2f64(<2 x double> %val1, <2 x double> %val2) + ret <2 x double> %ret +} + diff --git a/test/CodeGen/SystemZ/vec-move-18.ll b/test/CodeGen/SystemZ/vec-move-18.ll new file mode 100644 index 00000000000..5d3d09d83ef --- /dev/null +++ b/test/CodeGen/SystemZ/vec-move-18.ll @@ -0,0 +1,24 @@ +; Test insertions of memory values into 0 on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Test VLLEZLF. +define <4 x i32> @f1(i32 *%ptr) { +; CHECK-LABEL: f1: +; CHECK: vllezlf %v24, 0(%r2) +; CHECK: br %r14 + %val = load i32, i32 *%ptr + %ret = insertelement <4 x i32> zeroinitializer, i32 %val, i32 0 + ret <4 x i32> %ret +} + +; Test VLLEZLF with a float. +define <4 x float> @f2(float *%ptr) { +; CHECK-LABEL: f2: +; CHECK: vllezlf %v24, 0(%r2) +; CHECK: br %r14 + %val = load float, float *%ptr + %ret = insertelement <4 x float> zeroinitializer, float %val, i32 0 + ret <4 x float> %ret +} + diff --git a/test/CodeGen/SystemZ/vec-mul-05.ll b/test/CodeGen/SystemZ/vec-mul-05.ll new file mode 100644 index 00000000000..c05437d4923 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-mul-05.ll @@ -0,0 +1,32 @@ +; Test vector negative multiply-and-add on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +declare <2 x double> @llvm.fma.v2f64(<2 x double>, <2 x double>, <2 x double>) + +; Test a v2f64 negative multiply-and-add. +define <2 x double> @f1(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2, <2 x double> %val3) { +; CHECK-LABEL: f1: +; CHECK: vfnmadb %v24, %v26, %v28, %v30 +; CHECK: br %r14 + %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1, + <2 x double> %val2, + <2 x double> %val3) + %negret = fsub <2 x double> , %ret + ret <2 x double> %negret +} + +; Test a v2f64 negative multiply-and-subtract. +define <2 x double> @f2(<2 x double> %dummy, <2 x double> %val1, + <2 x double> %val2, <2 x double> %val3) { +; CHECK-LABEL: f2: +; CHECK: vfnmsdb %v24, %v26, %v28, %v30 +; CHECK: br %r14 + %negval3 = fsub <2 x double> , %val3 + %ret = call <2 x double> @llvm.fma.v2f64 (<2 x double> %val1, + <2 x double> %val2, + <2 x double> %negval3) + %negret = fsub <2 x double> , %ret + ret <2 x double> %negret +} diff --git a/test/CodeGen/SystemZ/vec-or-03.ll b/test/CodeGen/SystemZ/vec-or-03.ll new file mode 100644 index 00000000000..010629d880d --- /dev/null +++ b/test/CodeGen/SystemZ/vec-or-03.ll @@ -0,0 +1,91 @@ +; Test vector OR-NOT on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Test a v16i8 OR-NOT. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: voc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <16 x i8> %val2, + %ret = or <16 x i8> %val1, %not + ret <16 x i8> %ret +} + +; ...and again with the reverse. +define <16 x i8> @f2(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f2: +; CHECK: voc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <16 x i8> %val1, + %ret = or <16 x i8> %not, %val2 + ret <16 x i8> %ret +} + +; Test a v8i16 OR-NOT. +define <8 x i16> @f3(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f3: +; CHECK: voc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <8 x i16> %val2, + %ret = or <8 x i16> %val1, %not + ret <8 x i16> %ret +} + +; ...and again with the reverse. +define <8 x i16> @f4(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f4: +; CHECK: voc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <8 x i16> %val1, + %ret = or <8 x i16> %not, %val2 + ret <8 x i16> %ret +} + +; Test a v4i32 OR-NOT. +define <4 x i32> @f5(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f5: +; CHECK: voc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <4 x i32> %val2, + %ret = or <4 x i32> %val1, %not + ret <4 x i32> %ret +} + +; ...and again with the reverse. +define <4 x i32> @f6(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f6: +; CHECK: voc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <4 x i32> %val1, + %ret = or <4 x i32> %not, %val2 + ret <4 x i32> %ret +} + +; Test a v2i64 OR-NOT. +define <2 x i64> @f7(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f7: +; CHECK: voc %v24, %v26, %v28 +; CHECK: br %r14 + %not = xor <2 x i64> %val2, + %ret = or <2 x i64> %val1, %not + ret <2 x i64> %ret +} + +; ...and again with the reverse. +define <2 x i64> @f8(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f8: +; CHECK: voc %v24, %v28, %v26 +; CHECK: br %r14 + %not = xor <2 x i64> %val1, + %ret = or <2 x i64> %not, %val2 + ret <2 x i64> %ret +} diff --git a/test/CodeGen/SystemZ/vec-xor-02.ll b/test/CodeGen/SystemZ/vec-xor-02.ll new file mode 100644 index 00000000000..b4b5a96ba25 --- /dev/null +++ b/test/CodeGen/SystemZ/vec-xor-02.ll @@ -0,0 +1,47 @@ +; Test vector NOT-XOR on z14. +; +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s + +; Test a v16i8 NOT-XOR. +define <16 x i8> @f1(<16 x i8> %dummy, <16 x i8> %val1, <16 x i8> %val2) { +; CHECK-LABEL: f1: +; CHECK: vnx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <16 x i8> %val1, %val2 + %not = xor <16 x i8> %ret, + ret <16 x i8> %not +} + +; Test a v8i16 NOT-XOR. +define <8 x i16> @f2(<8 x i16> %dummy, <8 x i16> %val1, <8 x i16> %val2) { +; CHECK-LABEL: f2: +; CHECK: vnx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <8 x i16> %val1, %val2 + %not = xor <8 x i16> %ret, + ret <8 x i16> %not +} + +; Test a v4i32 NOT-XOR. +define <4 x i32> @f3(<4 x i32> %dummy, <4 x i32> %val1, <4 x i32> %val2) { +; CHECK-LABEL: f3: +; CHECK: vnx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <4 x i32> %val1, %val2 + %not = xor <4 x i32> %ret, + ret <4 x i32> %not +} + +; Test a v2i64 NOT-XOR. +define <2 x i64> @f4(<2 x i64> %dummy, <2 x i64> %val1, <2 x i64> %val2) { +; CHECK-LABEL: f4: +; CHECK: vnx %v24, %v26, %v28 +; CHECK: br %r14 + %ret = xor <2 x i64> %val1, %val2 + %not = xor <2 x i64> %ret, + ret <2 x i64> %not +} diff --git a/test/MC/Disassembler/SystemZ/insns-z14.txt b/test/MC/Disassembler/SystemZ/insns-z14.txt new file mode 100644 index 00000000000..07d2f233f20 --- /dev/null +++ b/test/MC/Disassembler/SystemZ/insns-z14.txt @@ -0,0 +1,1594 @@ +# Test z14 instructions that don't have PC-relative operands. +# RUN: llvm-mc --disassemble %s -triple=s390x-linux-gnu -mcpu=z14 \ +# RUN: | FileCheck %s + +# CHECK: agh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x38 + +# CHECK: agh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x38 + +# CHECK: agh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x38 + +# CHECK: agh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x38 + +# CHECK: agh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x38 + +# CHECK: agh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x38 + +# CHECK: agh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x38 + +# CHECK: agh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x38 + +# CHECK: agh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x38 + +# CHECK: agh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x38 + +# CHECK: bi -524288 +0xe3 0xf0 0x00 0x00 0x80 0x47 + +# CHECK: bi -1 +0xe3 0xf0 0x0f 0xff 0xff 0x47 + +# CHECK: bi 0 +0xe3 0xf0 0x00 0x00 0x00 0x47 + +# CHECK: bi 1 +0xe3 0xf0 0x00 0x01 0x00 0x47 + +# CHECK: bi 524287 +0xe3 0xf0 0x0f 0xff 0x7f 0x47 + +# CHECK: bi 0(%r1) +0xe3 0xf0 0x10 0x00 0x00 0x47 + +# CHECK: bi 0(%r15) +0xe3 0xf0 0xf0 0x00 0x00 0x47 + +# CHECK: bi 524287(%r1,%r15) +0xe3 0xf1 0xff 0xff 0x7f 0x47 + +# CHECK: bi 524287(%r15,%r1) +0xe3 0xff 0x1f 0xff 0x7f 0x47 + +# CHECK: bic 0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x47 + +# CHECK: bic 0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x47 + +# CHECK: bic 0, 0 +0xe3 0x00 0x00 0x00 0x00 0x47 + +# CHECK: bic 0, 1 +0xe3 0x00 0x00 0x01 0x00 0x47 + +# CHECK: bic 0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x47 + +# CHECK: bic 0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x47 + +# CHECK: bic 0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x47 + +# CHECK: bic 0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x47 + +# CHECK: bic 0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x47 + +# CHECK: bio 0(%r15) +0xe3 0x10 0xf0 0x00 0x00 0x47 + +# CHECK: bih 0(%r15) +0xe3 0x20 0xf0 0x00 0x00 0x47 + +# CHECK: binle 0(%r15) +0xe3 0x30 0xf0 0x00 0x00 0x47 + +# CHECK: bil 0(%r15) +0xe3 0x40 0xf0 0x00 0x00 0x47 + +# CHECK: binhe 0(%r15) +0xe3 0x50 0xf0 0x00 0x00 0x47 + +# CHECK: bilh 0(%r15) +0xe3 0x60 0xf0 0x00 0x00 0x47 + +# CHECK: bine 0(%r15) +0xe3 0x70 0xf0 0x00 0x00 0x47 + +# CHECK: bie 0(%r15) +0xe3 0x80 0xf0 0x00 0x00 0x47 + +# CHECK: binlh 0(%r15) +0xe3 0x90 0xf0 0x00 0x00 0x47 + +# CHECK: bihe 0(%r15) +0xe3 0xa0 0xf0 0x00 0x00 0x47 + +# CHECK: binl 0(%r15) +0xe3 0xb0 0xf0 0x00 0x00 0x47 + +# CHECK: bile 0(%r15) +0xe3 0xc0 0xf0 0x00 0x00 0x47 + +# CHECK: binh 0(%r15) +0xe3 0xd0 0xf0 0x00 0x00 0x47 + +# CHECK: bino 0(%r15) +0xe3 0xe0 0xf0 0x00 0x00 0x47 + +# CHECK: irbm %r0, %r0 +0xb9 0xac 0x00 0x00 + +# CHECK: irbm %r0, %r15 +0xb9 0xac 0x00 0x0f + +# CHECK: irbm %r15, %r0 +0xb9 0xac 0x00 0xf0 + +# CHECK: irbm %r7, %r8 +0xb9 0xac 0x00 0x78 + +# CHECK: irbm %r15, %r15 +0xb9 0xac 0x00 0xff + +# CHECK: kma %r2, %r2, %r2 +0xb9 0x29 0x20 0x22 + +# CHECK: kma %r2, %r8, %r14 +0xb9 0x29 0x80 0x2e + +# CHECK: kma %r14, %r8, %r2 +0xb9 0x29 0x80 0xe2 + +# CHECK: kma %r6, %r8, %r10 +0xb9 0x29 0x80 0x6a + +# CHECK: lgg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x4c + +# CHECK: lgg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x4c + +# CHECK: lgg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x4c + +# CHECK: lgg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x4c + +# CHECK: lgg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x4c + +# CHECK: lgg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x4c + +# CHECK: lgg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x4c + +# CHECK: lgg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x4c + +# CHECK: lgg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x4c + +# CHECK: lgg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x4c + +# CHECK: lgsc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x4d + +# CHECK: lgsc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x4d + +# CHECK: lgsc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x4d + +# CHECK: lgsc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x4d + +# CHECK: lgsc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x4d + +# CHECK: lgsc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x4d + +# CHECK: lgsc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x4d + +# CHECK: lgsc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x4d + +# CHECK: lgsc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x4d + +# CHECK: llgfsg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x48 + +# CHECK: llgfsg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x48 + +# CHECK: llgfsg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x48 + +# CHECK: llgfsg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x48 + +# CHECK: llgfsg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x48 + +# CHECK: llgfsg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x48 + +# CHECK: llgfsg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x48 + +# CHECK: llgfsg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x48 + +# CHECK: llgfsg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x48 + +# CHECK: llgfsg %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x48 + +# CHECK: mg %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x84 + +# CHECK: mg %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x84 + +# CHECK: mg %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x84 + +# CHECK: mg %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x84 + +# CHECK: mg %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x84 + +# CHECK: mg %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x84 + +# CHECK: mg %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x84 + +# CHECK: mg %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x84 + +# CHECK: mg %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x84 + +# CHECK: mg %r14, 0 +0xe3 0xe0 0x00 0x00 0x00 0x84 + +# CHECK: mgh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x3c + +# CHECK: mgh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x3c + +# CHECK: mgh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x3c + +# CHECK: mgh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x3c + +# CHECK: mgh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x3c + +# CHECK: mgh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x3c + +# CHECK: mgh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x3c + +# CHECK: mgh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x3c + +# CHECK: mgh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x3c + +# CHECK: mgh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x3c + +# CHECK: mgrk %r0, %r0, %r0 +0xb9 0xec 0x00 0x00 + +# CHECK: mgrk %r0, %r0, %r15 +0xb9 0xec 0xf0 0x00 + +# CHECK: mgrk %r0, %r15, %r0 +0xb9 0xec 0x00 0x0f + +# CHECK: mgrk %r14, %r0, %r0 +0xb9 0xec 0x00 0xe0 + +# CHECK: mgrk %r6, %r8, %r9 +0xb9 0xec 0x90 0x68 + +# CHECK: msc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x53 + +# CHECK: msc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x53 + +# CHECK: msc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x53 + +# CHECK: msc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x53 + +# CHECK: msc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x53 + +# CHECK: msc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x53 + +# CHECK: msc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x53 + +# CHECK: msc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x53 + +# CHECK: msc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x53 + +# CHECK: msc %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x53 + +# CHECK: msgc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x83 + +# CHECK: msgc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x83 + +# CHECK: msgc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x83 + +# CHECK: msgc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x83 + +# CHECK: msgc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x83 + +# CHECK: msgc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x83 + +# CHECK: msgc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x83 + +# CHECK: msgc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x83 + +# CHECK: msgc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x83 + +# CHECK: msgc %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x83 + +# CHECK: msrkc %r0, %r0, %r0 +0xb9 0xfd 0x00 0x00 + +# CHECK: msrkc %r0, %r0, %r15 +0xb9 0xfd 0xf0 0x00 + +# CHECK: msrkc %r0, %r15, %r0 +0xb9 0xfd 0x00 0x0f + +# CHECK: msrkc %r15, %r0, %r0 +0xb9 0xfd 0x00 0xf0 + +# CHECK: msrkc %r7, %r8, %r9 +0xb9 0xfd 0x90 0x78 + +# CHECK: msgrkc %r0, %r0, %r0 +0xb9 0xed 0x00 0x00 + +# CHECK: msgrkc %r0, %r0, %r15 +0xb9 0xed 0xf0 0x00 + +# CHECK: msgrkc %r0, %r15, %r0 +0xb9 0xed 0x00 0x0f + +# CHECK: msgrkc %r15, %r0, %r0 +0xb9 0xed 0x00 0xf0 + +# CHECK: msgrkc %r7, %r8, %r9 +0xb9 0xed 0x90 0x78 + +# CHECK: sgh %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x39 + +# CHECK: sgh %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x39 + +# CHECK: sgh %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x39 + +# CHECK: sgh %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x39 + +# CHECK: sgh %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x39 + +# CHECK: sgh %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x39 + +# CHECK: sgh %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x39 + +# CHECK: sgh %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x39 + +# CHECK: sgh %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x39 + +# CHECK: sgh %r15, 0 +0xe3 0xf0 0x00 0x00 0x00 0x39 + +# CHECK: stgsc %r0, -524288 +0xe3 0x00 0x00 0x00 0x80 0x49 + +# CHECK: stgsc %r0, -1 +0xe3 0x00 0x0f 0xff 0xff 0x49 + +# CHECK: stgsc %r0, 0 +0xe3 0x00 0x00 0x00 0x00 0x49 + +# CHECK: stgsc %r0, 1 +0xe3 0x00 0x00 0x01 0x00 0x49 + +# CHECK: stgsc %r0, 524287 +0xe3 0x00 0x0f 0xff 0x7f 0x49 + +# CHECK: stgsc %r0, 0(%r1) +0xe3 0x00 0x10 0x00 0x00 0x49 + +# CHECK: stgsc %r0, 0(%r15) +0xe3 0x00 0xf0 0x00 0x00 0x49 + +# CHECK: stgsc %r0, 524287(%r1,%r15) +0xe3 0x01 0xff 0xff 0x7f 0x49 + +# CHECK: stgsc %r0, 524287(%r15,%r1) +0xe3 0x0f 0x1f 0xff 0x7f 0x49 + +# CHECK: vap %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x71 + +# CHECK: vap %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x71 + +# CHECK: vap %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x71 + +# CHECK: vap %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x71 + +# CHECK: vap %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x71 + +# CHECK: vap %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x71 + +# CHECK: vap %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x71 + +# CHECK: vbperm %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x85 + +# CHECK: vbperm %v0, %v0, %v15 +0xe7 0x00 0xf0 0x00 0x00 0x85 + +# CHECK: vbperm %v0, %v0, %v31 +0xe7 0x00 0xf0 0x00 0x02 0x85 + +# CHECK: vbperm %v0, %v15, %v0 +0xe7 0x0f 0x00 0x00 0x00 0x85 + +# CHECK: vbperm %v0, %v31, %v0 +0xe7 0x0f 0x00 0x00 0x04 0x85 + +# CHECK: vbperm %v15, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x00 0x85 + +# CHECK: vbperm %v31, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x85 + +# CHECK: vbperm %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x85 + +# CHECK: vcp %v0, %v0, 0 +0xe6 0x00 0x00 0x00 0x00 0x77 + +# CHECK: vcp %v0, %v0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x77 + +# CHECK: vcp %v15, %v0, 0 +0xe6 0x0f 0x00 0x00 0x00 0x77 + +# CHECK: vcp %v31, %v0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x77 + +# CHECK: vcp %v0, %v15, 0 +0xe6 0x00 0xf0 0x00 0x00 0x77 + +# CHECK: vcp %v0, %v31, 0 +0xe6 0x00 0xf0 0x00 0x02 0x77 + +# CHECK: vcp %v3, %v18, 4 +0xe6 0x03 0x20 0x40 0x02 0x77 + +# CHECK: vcvb %r0, %v0, 0 +0xe6 0x00 0x00 0x00 0x00 0x50 + +# CHECK: vcvb %r0, %v0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x50 + +# CHECK: vcvb %r15, %v0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x50 + +# CHECK: vcvb %r0, %v15, 0 +0xe6 0x0f 0x00 0x00 0x00 0x50 + +# CHECK: vcvb %r0, %v31, 0 +0xe6 0x0f 0x00 0x00 0x04 0x50 + +# CHECK: vcvb %r3, %v18, 4 +0xe6 0x32 0x00 0x40 0x04 0x50 + +# CHECK: vcvbg %r0, %v0, 0 +0xe6 0x00 0x00 0x00 0x00 0x52 + +# CHECK: vcvbg %r0, %v0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x52 + +# CHECK: vcvbg %r15, %v0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x52 + +# CHECK: vcvbg %r0, %v15, 0 +0xe6 0x0f 0x00 0x00 0x00 0x52 + +# CHECK: vcvbg %r0, %v31, 0 +0xe6 0x0f 0x00 0x00 0x04 0x52 + +# CHECK: vcvbg %r3, %v18, 4 +0xe6 0x32 0x00 0x40 0x04 0x52 + +# CHECK: vcvd %v0, %r0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x58 + +# CHECK: vcvd %v0, %r0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x58 + +# CHECK: vcvd %v0, %r0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x58 + +# CHECK: vcvd %v0, %r15, 0, 0 +0xe6 0x0f 0x00 0x00 0x00 0x58 + +# CHECK: vcvd %v15, %r0, 0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x58 + +# CHECK: vcvd %v31, %r0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x58 + +# CHECK: vcvd %v18, %r9, 52, 11 +0xe6 0x29 0x00 0xb3 0x48 0x58 + +# CHECK: vcvdg %v0, %r0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x5a + +# CHECK: vcvdg %v0, %r0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x5a + +# CHECK: vcvdg %v0, %r0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x5a + +# CHECK: vcvdg %v0, %r15, 0, 0 +0xe6 0x0f 0x00 0x00 0x00 0x5a + +# CHECK: vcvdg %v15, %r0, 0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x5a + +# CHECK: vcvdg %v31, %r0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x5a + +# CHECK: vcvdg %v18, %r9, 52, 11 +0xe6 0x29 0x00 0xb3 0x48 0x5a + +# CHECK: vdp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x7a + +# CHECK: vdp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x7a + +# CHECK: vdp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x7a + +# CHECK: vdp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x7a + +# CHECK: vdp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x7a + +# CHECK: vdp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x7a + +# CHECK: vdp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x7a + +# CHECK: vfkedb %v0, %v0, %v0 +0xe7 0x00 0x00 0x04 0x30 0xe8 + +# CHECK: vfkedb %v0, %v0, %v31 +0xe7 0x00 0xf0 0x04 0x32 0xe8 + +# CHECK: vfkedb %v0, %v31, %v0 +0xe7 0x0f 0x00 0x04 0x34 0xe8 + +# CHECK: vfkedb %v31, %v0, %v0 +0xe7 0xf0 0x00 0x04 0x38 0xe8 + +# CHECK: vfkedb %v18, %v3, %v20 +0xe7 0x23 0x40 0x04 0x3a 0xe8 + +# CHECK: vfkedbs %v0, %v0, %v0 +0xe7 0x00 0x00 0x14 0x30 0xe8 + +# CHECK: vfkedbs %v0, %v0, %v31 +0xe7 0x00 0xf0 0x14 0x32 0xe8 + +# CHECK: vfkedbs %v0, %v31, %v0 +0xe7 0x0f 0x00 0x14 0x34 0xe8 + +# CHECK: vfkedbs %v31, %v0, %v0 +0xe7 0xf0 0x00 0x14 0x38 0xe8 + +# CHECK: vfkedbs %v18, %v3, %v20 +0xe7 0x23 0x40 0x14 0x3a 0xe8 + +# CHECK: vfkhdb %v0, %v0, %v0 +0xe7 0x00 0x00 0x04 0x30 0xeb + +# CHECK: vfkhdb %v0, %v0, %v31 +0xe7 0x00 0xf0 0x04 0x32 0xeb + +# CHECK: vfkhdb %v0, %v31, %v0 +0xe7 0x0f 0x00 0x04 0x34 0xeb + +# CHECK: vfkhdb %v31, %v0, %v0 +0xe7 0xf0 0x00 0x04 0x38 0xeb + +# CHECK: vfkhdb %v18, %v3, %v20 +0xe7 0x23 0x40 0x04 0x3a 0xeb + +# CHECK: vfkhdbs %v0, %v0, %v0 +0xe7 0x00 0x00 0x14 0x30 0xeb + +# CHECK: vfkhdbs %v0, %v0, %v31 +0xe7 0x00 0xf0 0x14 0x32 0xeb + +# CHECK: vfkhdbs %v0, %v31, %v0 +0xe7 0x0f 0x00 0x14 0x34 0xeb + +# CHECK: vfkhdbs %v31, %v0, %v0 +0xe7 0xf0 0x00 0x14 0x38 0xeb + +# CHECK: vfkhdbs %v18, %v3, %v20 +0xe7 0x23 0x40 0x14 0x3a 0xeb + +# CHECK: vfkhedb %v0, %v0, %v0 +0xe7 0x00 0x00 0x04 0x30 0xea + +# CHECK: vfkhedb %v0, %v0, %v31 +0xe7 0x00 0xf0 0x04 0x32 0xea + +# CHECK: vfkhedb %v0, %v31, %v0 +0xe7 0x0f 0x00 0x04 0x34 0xea + +# CHECK: vfkhedb %v31, %v0, %v0 +0xe7 0xf0 0x00 0x04 0x38 0xea + +# CHECK: vfkhedb %v18, %v3, %v20 +0xe7 0x23 0x40 0x04 0x3a 0xea + +# CHECK: vfkhedbs %v0, %v0, %v0 +0xe7 0x00 0x00 0x14 0x30 0xea + +# CHECK: vfkhedbs %v0, %v0, %v31 +0xe7 0x00 0xf0 0x14 0x32 0xea + +# CHECK: vfkhedbs %v0, %v31, %v0 +0xe7 0x0f 0x00 0x14 0x34 0xea + +# CHECK: vfkhedbs %v31, %v0, %v0 +0xe7 0xf0 0x00 0x14 0x38 0xea + +# CHECK: vfkhedbs %v18, %v3, %v20 +0xe7 0x23 0x40 0x14 0x3a 0xea + +# CHECK: vfmax %v0, %v0, %v0, 0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0xef + +# CHECK: vfmax %v0, %v0, %v0, 15, 0, 0 +0xe7 0x00 0x00 0x00 0xf0 0xef + +# CHECK: vfmax %v0, %v0, %v0, 0, 15, 0 +0xe7 0x00 0x00 0x0f 0x00 0xef + +# CHECK: vfmax %v0, %v0, %v0, 0, 0, 4 +0xe7 0x00 0x00 0x40 0x00 0xef + +# CHECK: vfmax %v0, %v0, %v31, 0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0xef + +# CHECK: vfmax %v0, %v31, %v0, 0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0xef + +# CHECK: vfmax %v31, %v0, %v0, 0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0xef + +# CHECK: vfmax %v18, %v3, %v20, 11, 9, 12 +0xe7 0x23 0x40 0xc9 0xba 0xef + +# CHECK: vfmaxdb %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0xef + +# CHECK: vfmaxdb %v0, %v0, %v0, 4 +0xe7 0x00 0x00 0x40 0x30 0xef + +# CHECK: vfmaxdb %v0, %v0, %v31, 0 +0xe7 0x00 0xf0 0x00 0x32 0xef + +# CHECK: vfmaxdb %v0, %v31, %v0, 0 +0xe7 0x0f 0x00 0x00 0x34 0xef + +# CHECK: vfmaxdb %v31, %v0, %v0, 0 +0xe7 0xf0 0x00 0x00 0x38 0xef + +# CHECK: vfmaxdb %v18, %v3, %v20, 12 +0xe7 0x23 0x40 0xc0 0x3a 0xef + +# CHECK: vfmin %v0, %v0, %v0, 0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0xee + +# CHECK: vfmin %v0, %v0, %v0, 15, 0, 0 +0xe7 0x00 0x00 0x00 0xf0 0xee + +# CHECK: vfmin %v0, %v0, %v0, 0, 15, 0 +0xe7 0x00 0x00 0x0f 0x00 0xee + +# CHECK: vfmin %v0, %v0, %v0, 0, 0, 4 +0xe7 0x00 0x00 0x40 0x00 0xee + +# CHECK: vfmin %v0, %v0, %v31, 0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0xee + +# CHECK: vfmin %v0, %v31, %v0, 0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0xee + +# CHECK: vfmin %v31, %v0, %v0, 0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0xee + +# CHECK: vfmin %v18, %v3, %v20, 11, 9, 12 +0xe7 0x23 0x40 0xc9 0xba 0xee + +# CHECK: vfmindb %v0, %v0, %v0, 0 +0xe7 0x00 0x00 0x00 0x30 0xee + +# CHECK: vfmindb %v0, %v0, %v0, 4 +0xe7 0x00 0x00 0x40 0x30 0xee + +# CHECK: vfmindb %v0, %v0, %v31, 0 +0xe7 0x00 0xf0 0x00 0x32 0xee + +# CHECK: vfmindb %v0, %v31, %v0, 0 +0xe7 0x0f 0x00 0x00 0x34 0xee + +# CHECK: vfmindb %v31, %v0, %v0, 0 +0xe7 0xf0 0x00 0x00 0x38 0xee + +# CHECK: vfmindb %v18, %v3, %v20, 12 +0xe7 0x23 0x40 0xc0 0x3a 0xee + +# CHECK: vfnma %v0, %v0, %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x9f + +# CHECK: vfnma %v0, %v0, %v0, %v0, 0, 15 +0xe7 0x00 0x0f 0x00 0x00 0x9f + +# CHECK: vfnma %v0, %v0, %v0, %v0, 15, 0 +0xe7 0x00 0x00 0x0f 0x00 0x9f + +# CHECK: vfnma %v0, %v0, %v0, %v31, 0, 0 +0xe7 0x00 0x00 0x00 0xf1 0x9f + +# CHECK: vfnma %v0, %v0, %v31, %v0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0x9f + +# CHECK: vfnma %v0, %v31, %v0, %v0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0x9f + +# CHECK: vfnma %v31, %v0, %v0, %v0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0x9f + +# CHECK: vfnma %v13, %v17, %v21, %v25, 9, 11 +0xe7 0xd1 0x5b 0x09 0x97 0x9f + +# CHECK: vfnmadb %v0, %v0, %v0, %v0 +0xe7 0x00 0x03 0x00 0x00 0x9f + +# CHECK: vfnmadb %v0, %v0, %v0, %v31 +0xe7 0x00 0x03 0x00 0xf1 0x9f + +# CHECK: vfnmadb %v0, %v0, %v31, %v0 +0xe7 0x00 0xf3 0x00 0x02 0x9f + +# CHECK: vfnmadb %v0, %v31, %v0, %v0 +0xe7 0x0f 0x03 0x00 0x04 0x9f + +# CHECK: vfnmadb %v31, %v0, %v0, %v0 +0xe7 0xf0 0x03 0x00 0x08 0x9f + +# CHECK: vfnmadb %v13, %v17, %v21, %v25 +0xe7 0xd1 0x53 0x00 0x97 0x9f + +# CHECK: vfnms %v0, %v0, %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0x9e + +# CHECK: vfnms %v0, %v0, %v0, %v0, 0, 15 +0xe7 0x00 0x0f 0x00 0x00 0x9e + +# CHECK: vfnms %v0, %v0, %v0, %v0, 15, 0 +0xe7 0x00 0x00 0x0f 0x00 0x9e + +# CHECK: vfnms %v0, %v0, %v0, %v31, 0, 0 +0xe7 0x00 0x00 0x00 0xf1 0x9e + +# CHECK: vfnms %v0, %v0, %v31, %v0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0x9e + +# CHECK: vfnms %v0, %v31, %v0, %v0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0x9e + +# CHECK: vfnms %v31, %v0, %v0, %v0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0x9e + +# CHECK: vfnms %v13, %v17, %v21, %v25, 9, 11 +0xe7 0xd1 0x5b 0x09 0x97 0x9e + +# CHECK: vfnmsdb %v0, %v0, %v0, %v0 +0xe7 0x00 0x03 0x00 0x00 0x9e + +# CHECK: vfnmsdb %v0, %v0, %v0, %v31 +0xe7 0x00 0x03 0x00 0xf1 0x9e + +# CHECK: vfnmsdb %v0, %v0, %v31, %v0 +0xe7 0x00 0xf3 0x00 0x02 0x9e + +# CHECK: vfnmsdb %v0, %v31, %v0, %v0 +0xe7 0x0f 0x03 0x00 0x04 0x9e + +# CHECK: vfnmsdb %v31, %v0, %v0, %v0 +0xe7 0xf0 0x03 0x00 0x08 0x9e + +# CHECK: vfnmsdb %v13, %v17, %v21, %v25 +0xe7 0xd1 0x53 0x00 0x97 0x9e + +# CHECK: vlip %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x49 + +# CHECK: vlip %v0, 0, 15 +0xe6 0x00 0x00 0x00 0xf0 0x49 + +# CHECK: vlip %v0, 65535, 0 +0xe6 0x00 0xff 0xff 0x00 0x49 + +# CHECK: vlip %v15, 0, 0 +0xe6 0xf0 0x00 0x00 0x00 0x49 + +# CHECK: vlip %v31, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x49 + +# CHECK: vlip %v17, 4660, 7 +0xe6 0x10 0x12 0x34 0x78 0x49 + +# CHECK: vllezlf %v0, 0 +0xe7 0x00 0x00 0x00 0x60 0x04 + +# CHECK: vllezlf %v0, 4095 +0xe7 0x00 0x0f 0xff 0x60 0x04 + +# CHECK: vllezlf %v0, 0(%r15) +0xe7 0x00 0xf0 0x00 0x60 0x04 + +# CHECK: vllezlf %v0, 0(%r15,%r1) +0xe7 0x0f 0x10 0x00 0x60 0x04 + +# CHECK: vllezlf %v15, 0 +0xe7 0xf0 0x00 0x00 0x60 0x04 + +# CHECK: vllezlf %v31, 0 +0xe7 0xf0 0x00 0x00 0x68 0x04 + +# CHECK: vllezlf %v18, 1383(%r3,%r4) +0xe7 0x23 0x45 0x67 0x68 0x04 + +# CHECK: vlrl %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x35 + +# CHECK: vlrl %v0, 4095, 0 +0xe6 0x00 0x0f 0xff 0x00 0x35 + +# CHECK: vlrl %v0, 0(%r15), 0 +0xe6 0x00 0xf0 0x00 0x00 0x35 + +# CHECK: vlrl %v0, 0, 255 +0xe6 0xff 0x00 0x00 0x00 0x35 + +# CHECK: vlrl %v15, 0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x35 + +# CHECK: vlrl %v31, 0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x35 + +# CHECK: vlrl %v18, 1383(%r4), 3 +0xe6 0x03 0x45 0x67 0x21 0x35 + +# CHECK: vlrlr %v0, %r0, 0 +0xe6 0x00 0x00 0x00 0x00 0x37 + +# CHECK: vlrlr %v0, %r0, 4095 +0xe6 0x00 0x0f 0xff 0x00 0x37 + +# CHECK: vlrlr %v0, %r0, 0(%r15) +0xe6 0x00 0xf0 0x00 0x00 0x37 + +# CHECK: vlrlr %v0, %r15, 0 +0xe6 0x0f 0x00 0x00 0x00 0x37 + +# CHECK: vlrlr %v15, %r0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x37 + +# CHECK: vlrlr %v31, %r0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x37 + +# CHECK: vlrlr %v18, %r3, 1383(%r4) +0xe6 0x03 0x45 0x67 0x21 0x37 + +# CHECK: vmsl %v0, %v0, %v0, %v0, 0, 0 +0xe7 0x00 0x00 0x00 0x00 0xb8 + +# CHECK: vmsl %v0, %v0, %v0, %v0, 15, 0 +0xe7 0x00 0x0f 0x00 0x00 0xb8 + +# CHECK: vmsl %v0, %v0, %v0, %v0, 0, 12 +0xe7 0x00 0x00 0xc0 0x00 0xb8 + +# CHECK: vmsl %v0, %v0, %v0, %v15, 0, 0 +0xe7 0x00 0x00 0x00 0xf0 0xb8 + +# CHECK: vmsl %v0, %v0, %v0, %v31, 0, 0 +0xe7 0x00 0x00 0x00 0xf1 0xb8 + +# CHECK: vmsl %v0, %v0, %v15, %v0, 0, 0 +0xe7 0x00 0xf0 0x00 0x00 0xb8 + +# CHECK: vmsl %v0, %v0, %v31, %v0, 0, 0 +0xe7 0x00 0xf0 0x00 0x02 0xb8 + +# CHECK: vmsl %v0, %v15, %v0, %v0, 0, 0 +0xe7 0x0f 0x00 0x00 0x00 0xb8 + +# CHECK: vmsl %v0, %v31, %v0, %v0, 0, 0 +0xe7 0x0f 0x00 0x00 0x04 0xb8 + +# CHECK: vmsl %v15, %v0, %v0, %v0, 0, 0 +0xe7 0xf0 0x00 0x00 0x00 0xb8 + +# CHECK: vmsl %v31, %v0, %v0, %v0, 0, 0 +0xe7 0xf0 0x00 0x00 0x08 0xb8 + +# CHECK: vmsl %v18, %v3, %v20, %v5, 0, 4 +0xe7 0x23 0x40 0x40 0x5a 0xb8 + +# CHECK: vmsl %v18, %v3, %v20, %v5, 11, 8 +0xe7 0x23 0x4b 0x80 0x5a 0xb8 + +# CHECK: vmslg %v0, %v0, %v0, %v0, 0 +0xe7 0x00 0x03 0x00 0x00 0xb8 + +# CHECK: vmslg %v0, %v0, %v0, %v0, 12 +0xe7 0x00 0x03 0xc0 0x00 0xb8 + +# CHECK: vmslg %v0, %v0, %v0, %v15, 0 +0xe7 0x00 0x03 0x00 0xf0 0xb8 + +# CHECK: vmslg %v0, %v0, %v0, %v31, 0 +0xe7 0x00 0x03 0x00 0xf1 0xb8 + +# CHECK: vmslg %v0, %v0, %v15, %v0, 0 +0xe7 0x00 0xf3 0x00 0x00 0xb8 + +# CHECK: vmslg %v0, %v0, %v31, %v0, 0 +0xe7 0x00 0xf3 0x00 0x02 0xb8 + +# CHECK: vmslg %v0, %v15, %v0, %v0, 0 +0xe7 0x0f 0x03 0x00 0x00 0xb8 + +# CHECK: vmslg %v0, %v31, %v0, %v0, 0 +0xe7 0x0f 0x03 0x00 0x04 0xb8 + +# CHECK: vmslg %v15, %v0, %v0, %v0, 0 +0xe7 0xf0 0x03 0x00 0x00 0xb8 + +# CHECK: vmslg %v31, %v0, %v0, %v0, 0 +0xe7 0xf0 0x03 0x00 0x08 0xb8 + +# CHECK: vmslg %v18, %v3, %v20, %v5, 4 +0xe7 0x23 0x43 0x40 0x5a 0xb8 + +# CHECK: vmslg %v18, %v3, %v20, %v5, 8 +0xe7 0x23 0x43 0x80 0x5a 0xb8 + +# CHECK: vmp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x78 + +# CHECK: vmp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x78 + +# CHECK: vmp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x78 + +# CHECK: vmp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x78 + +# CHECK: vmp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x78 + +# CHECK: vmp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x78 + +# CHECK: vmp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x78 + +# CHECK: vmsp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x79 + +# CHECK: vmsp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x79 + +# CHECK: vmsp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x79 + +# CHECK: vmsp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x79 + +# CHECK: vmsp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x79 + +# CHECK: vmsp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x79 + +# CHECK: vmsp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x79 + +# CHECK: vnn %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x6e + +# CHECK: vnn %v0, %v0, %v31 +0xe7 0x00 0xf0 0x00 0x02 0x6e + +# CHECK: vnn %v0, %v31, %v0 +0xe7 0x0f 0x00 0x00 0x04 0x6e + +# CHECK: vnn %v31, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x6e + +# CHECK: vnn %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x6e + +# CHECK: vnx %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x6c + +# CHECK: vnx %v0, %v0, %v31 +0xe7 0x00 0xf0 0x00 0x02 0x6c + +# CHECK: vnx %v0, %v31, %v0 +0xe7 0x0f 0x00 0x00 0x04 0x6c + +# CHECK: vnx %v31, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x6c + +# CHECK: vnx %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x6c + +# CHECK: voc %v0, %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x6f + +# CHECK: voc %v0, %v0, %v31 +0xe7 0x00 0xf0 0x00 0x02 0x6f + +# CHECK: voc %v0, %v31, %v0 +0xe7 0x0f 0x00 0x00 0x04 0x6f + +# CHECK: voc %v31, %v0, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x6f + +# CHECK: voc %v18, %v3, %v20 +0xe7 0x23 0x40 0x00 0x0a 0x6f + +# CHECK: vpkz %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x34 + +# CHECK: vpkz %v0, 4095, 0 +0xe6 0x00 0x0f 0xff 0x00 0x34 + +# CHECK: vpkz %v0, 0(%r15), 0 +0xe6 0x00 0xf0 0x00 0x00 0x34 + +# CHECK: vpkz %v0, 0, 255 +0xe6 0xff 0x00 0x00 0x00 0x34 + +# CHECK: vpkz %v15, 0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x34 + +# CHECK: vpkz %v31, 0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x34 + +# CHECK: vpkz %v18, 1383(%r4), 3 +0xe6 0x03 0x45 0x67 0x21 0x34 + +# CHECK: vpopctb %v0, %v0 +0xe7 0x00 0x00 0x00 0x00 0x50 + +# CHECK: vpopctb %v0, %v15 +0xe7 0x0f 0x00 0x00 0x00 0x50 + +# CHECK: vpopctb %v0, %v31 +0xe7 0x0f 0x00 0x00 0x04 0x50 + +# CHECK: vpopctb %v15, %v0 +0xe7 0xf0 0x00 0x00 0x00 0x50 + +# CHECK: vpopctb %v31, %v0 +0xe7 0xf0 0x00 0x00 0x08 0x50 + +# CHECK: vpopctb %v14, %v17 +0xe7 0xe1 0x00 0x00 0x04 0x50 + +# CHECK: vpopctf %v0, %v0 +0xe7 0x00 0x00 0x00 0x20 0x50 + +# CHECK: vpopctf %v0, %v15 +0xe7 0x0f 0x00 0x00 0x20 0x50 + +# CHECK: vpopctf %v0, %v31 +0xe7 0x0f 0x00 0x00 0x24 0x50 + +# CHECK: vpopctf %v15, %v0 +0xe7 0xf0 0x00 0x00 0x20 0x50 + +# CHECK: vpopctf %v31, %v0 +0xe7 0xf0 0x00 0x00 0x28 0x50 + +# CHECK: vpopctf %v14, %v17 +0xe7 0xe1 0x00 0x00 0x24 0x50 + +# CHECK: vpopctg %v0, %v0 +0xe7 0x00 0x00 0x00 0x30 0x50 + +# CHECK: vpopctg %v0, %v15 +0xe7 0x0f 0x00 0x00 0x30 0x50 + +# CHECK: vpopctg %v0, %v31 +0xe7 0x0f 0x00 0x00 0x34 0x50 + +# CHECK: vpopctg %v15, %v0 +0xe7 0xf0 0x00 0x00 0x30 0x50 + +# CHECK: vpopctg %v31, %v0 +0xe7 0xf0 0x00 0x00 0x38 0x50 + +# CHECK: vpopctg %v14, %v17 +0xe7 0xe1 0x00 0x00 0x34 0x50 + +# CHECK: vpopcth %v0, %v0 +0xe7 0x00 0x00 0x00 0x10 0x50 + +# CHECK: vpopcth %v0, %v15 +0xe7 0x0f 0x00 0x00 0x10 0x50 + +# CHECK: vpopcth %v0, %v31 +0xe7 0x0f 0x00 0x00 0x14 0x50 + +# CHECK: vpopcth %v15, %v0 +0xe7 0xf0 0x00 0x00 0x10 0x50 + +# CHECK: vpopcth %v31, %v0 +0xe7 0xf0 0x00 0x00 0x18 0x50 + +# CHECK: vpopcth %v14, %v17 +0xe7 0xe1 0x00 0x00 0x14 0x50 + +# CHECK: vpsop %v0, %v0, 0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x5b + +# CHECK: vpsop %v0, %v0, 0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x5b + +# CHECK: vpsop %v0, %v0, 0, 255, 0 +0xe6 0x00 0xff 0x00 0x00 0x5b + +# CHECK: vpsop %v0, %v0, 255, 0, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x5b + +# CHECK: vpsop %v0, %v31, 0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x5b + +# CHECK: vpsop %v31, %v0, 0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x5b + +# CHECK: vpsop %v13, %v17, 52, 121, 11 +0xe6 0xd1 0x79 0xb3 0x44 0x5b + +# CHECK: vrp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x7b + +# CHECK: vrp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x7b + +# CHECK: vrp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x7b + +# CHECK: vrp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x7b + +# CHECK: vrp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x7b + +# CHECK: vrp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x7b + +# CHECK: vrp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x7b + +# CHECK: vsdp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x7e + +# CHECK: vsdp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x7e + +# CHECK: vsdp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x7e + +# CHECK: vsdp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x7e + +# CHECK: vsdp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x7e + +# CHECK: vsdp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x7e + +# CHECK: vsdp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x7e + +# CHECK: vsp %v0, %v0, %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x73 + +# CHECK: vsp %v0, %v0, %v0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x73 + +# CHECK: vsp %v0, %v0, %v0, 255, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x73 + +# CHECK: vsp %v0, %v0, %v31, 0, 0 +0xe6 0x00 0xf0 0x00 0x02 0x73 + +# CHECK: vsp %v0, %v31, %v0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x73 + +# CHECK: vsp %v31, %v0, %v0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x73 + +# CHECK: vsp %v13, %v17, %v21, 121, 11 +0xe6 0xd1 0x50 0xb7 0x96 0x73 + +# CHECK: vsrp %v0, %v0, 0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x59 + +# CHECK: vsrp %v0, %v0, 0, 0, 15 +0xe6 0x00 0x00 0xf0 0x00 0x59 + +# CHECK: vsrp %v0, %v0, 0, 255, 0 +0xe6 0x00 0xff 0x00 0x00 0x59 + +# CHECK: vsrp %v0, %v0, 255, 0, 0 +0xe6 0x00 0x00 0x0f 0xf0 0x59 + +# CHECK: vsrp %v0, %v31, 0, 0, 0 +0xe6 0x0f 0x00 0x00 0x04 0x59 + +# CHECK: vsrp %v31, %v0, 0, 0, 0 +0xe6 0xf0 0x00 0x00 0x08 0x59 + +# CHECK: vsrp %v13, %v17, 52, 121, 11 +0xe6 0xd1 0x79 0xb3 0x44 0x59 + +# CHECK: vstrl %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x3d + +# CHECK: vstrl %v0, 4095, 0 +0xe6 0x00 0x0f 0xff 0x00 0x3d + +# CHECK: vstrl %v0, 0(%r15), 0 +0xe6 0x00 0xf0 0x00 0x00 0x3d + +# CHECK: vstrl %v0, 0, 255 +0xe6 0xff 0x00 0x00 0x00 0x3d + +# CHECK: vstrl %v15, 0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x3d + +# CHECK: vstrl %v31, 0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x3d + +# CHECK: vstrl %v18, 1383(%r4), 3 +0xe6 0x03 0x45 0x67 0x21 0x3d + +# CHECK: vstrlr %v0, %r0, 0 +0xe6 0x00 0x00 0x00 0x00 0x3f + +# CHECK: vstrlr %v0, %r0, 4095 +0xe6 0x00 0x0f 0xff 0x00 0x3f + +# CHECK: vstrlr %v0, %r0, 0(%r15) +0xe6 0x00 0xf0 0x00 0x00 0x3f + +# CHECK: vstrlr %v0, %r15, 0 +0xe6 0x0f 0x00 0x00 0x00 0x3f + +# CHECK: vstrlr %v15, %r0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x3f + +# CHECK: vstrlr %v31, %r0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x3f + +# CHECK: vstrlr %v18, %r3, 1383(%r4) +0xe6 0x03 0x45 0x67 0x21 0x3f + +# CHECK: vtp %v0 +0xe6 0x00 0x00 0x00 0x00 0x5f + +# CHECK: vtp %v15 +0xe6 0x0f 0x00 0x00 0x00 0x5f + +# CHECK: vtp %v31 +0xe6 0x0f 0x00 0x00 0x04 0x5f + +# CHECK: vupkz %v0, 0, 0 +0xe6 0x00 0x00 0x00 0x00 0x3c + +# CHECK: vupkz %v0, 4095, 0 +0xe6 0x00 0x0f 0xff 0x00 0x3c + +# CHECK: vupkz %v0, 0(%r15), 0 +0xe6 0x00 0xf0 0x00 0x00 0x3c + +# CHECK: vupkz %v0, 0, 255 +0xe6 0xff 0x00 0x00 0x00 0x3c + +# CHECK: vupkz %v15, 0, 0 +0xe6 0x00 0x00 0x00 0xf0 0x3c + +# CHECK: vupkz %v31, 0, 0 +0xe6 0x00 0x00 0x00 0xf1 0x3c + +# CHECK: vupkz %v18, 1383(%r4), 3 +0xe6 0x03 0x45 0x67 0x21 0x3c + +# CHECK: wfkedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xe8 + +# CHECK: wfkedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xe8 + +# CHECK: wfkedb %f0, %f0, %v31 +0xe7 0x00 0xf0 0x0c 0x32 0xe8 + +# CHECK: wfkedb %f0, %v31, %f0 +0xe7 0x0f 0x00 0x0c 0x34 0xe8 + +# CHECK: wfkedb %v31, %f0, %f0 +0xe7 0xf0 0x00 0x0c 0x38 0xe8 + +# CHECK: wfkedb %v18, %f3, %v20 +0xe7 0x23 0x40 0x0c 0x3a 0xe8 + +# CHECK: wfkedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xe8 + +# CHECK: wfkedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xe8 + +# CHECK: wfkedbs %f0, %f0, %v31 +0xe7 0x00 0xf0 0x1c 0x32 0xe8 + +# CHECK: wfkedbs %f0, %v31, %f0 +0xe7 0x0f 0x00 0x1c 0x34 0xe8 + +# CHECK: wfkedbs %v31, %f0, %f0 +0xe7 0xf0 0x00 0x1c 0x38 0xe8 + +# CHECK: wfkedbs %v18, %f3, %v20 +0xe7 0x23 0x40 0x1c 0x3a 0xe8 + +# CHECK: wfkhdb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xeb + +# CHECK: wfkhdb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xeb + +# CHECK: wfkhdb %f0, %f0, %v31 +0xe7 0x00 0xf0 0x0c 0x32 0xeb + +# CHECK: wfkhdb %f0, %v31, %f0 +0xe7 0x0f 0x00 0x0c 0x34 0xeb + +# CHECK: wfkhdb %v31, %f0, %f0 +0xe7 0xf0 0x00 0x0c 0x38 0xeb + +# CHECK: wfkhdb %v18, %f3, %v20 +0xe7 0x23 0x40 0x0c 0x3a 0xeb + +# CHECK: wfkhdbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xeb + +# CHECK: wfkhdbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xeb + +# CHECK: wfkhdbs %f0, %f0, %v31 +0xe7 0x00 0xf0 0x1c 0x32 0xeb + +# CHECK: wfkhdbs %f0, %v31, %f0 +0xe7 0x0f 0x00 0x1c 0x34 0xeb + +# CHECK: wfkhdbs %v31, %f0, %f0 +0xe7 0xf0 0x00 0x1c 0x38 0xeb + +# CHECK: wfkhdbs %v18, %f3, %v20 +0xe7 0x23 0x40 0x1c 0x3a 0xeb + +# CHECK: wfkhedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xea + +# CHECK: wfkhedb %f0, %f0, %f0 +0xe7 0x00 0x00 0x0c 0x30 0xea + +# CHECK: wfkhedb %f0, %f0, %v31 +0xe7 0x00 0xf0 0x0c 0x32 0xea + +# CHECK: wfkhedb %f0, %v31, %f0 +0xe7 0x0f 0x00 0x0c 0x34 0xea + +# CHECK: wfkhedb %v31, %f0, %f0 +0xe7 0xf0 0x00 0x0c 0x38 0xea + +# CHECK: wfkhedb %v18, %f3, %v20 +0xe7 0x23 0x40 0x0c 0x3a 0xea + +# CHECK: wfkhedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xea + +# CHECK: wfkhedbs %f0, %f0, %f0 +0xe7 0x00 0x00 0x1c 0x30 0xea + +# CHECK: wfkhedbs %f0, %f0, %v31 +0xe7 0x00 0xf0 0x1c 0x32 0xea + +# CHECK: wfkhedbs %f0, %v31, %f0 +0xe7 0x0f 0x00 0x1c 0x34 0xea + +# CHECK: wfkhedbs %v31, %f0, %f0 +0xe7 0xf0 0x00 0x1c 0x38 0xea + +# CHECK: wfkhedbs %v18, %f3, %v20 +0xe7 0x23 0x40 0x1c 0x3a 0xea + +# CHECK: wfmaxdb %f0, %f0, %f0, 0 +0xe7 0x00 0x00 0x08 0x30 0xef + +# CHECK: wfmaxdb %f0, %f0, %f0, 0 +0xe7 0x00 0x00 0x08 0x30 0xef + +# CHECK: wfmaxdb %f0, %f0, %f0, 4 +0xe7 0x00 0x00 0x48 0x30 0xef + +# CHECK: wfmaxdb %f0, %f0, %v31, 0 +0xe7 0x00 0xf0 0x08 0x32 0xef + +# CHECK: wfmaxdb %f0, %v31, %f0, 0 +0xe7 0x0f 0x00 0x08 0x34 0xef + +# CHECK: wfmaxdb %v31, %f0, %f0, 0 +0xe7 0xf0 0x00 0x08 0x38 0xef + +# CHECK: wfmaxdb %v18, %f3, %v20, 11 +0xe7 0x23 0x40 0xb8 0x3a 0xef + +# CHECK: wfmindb %f0, %f0, %f0, 0 +0xe7 0x00 0x00 0x08 0x30 0xee + +# CHECK: wfmindb %f0, %f0, %f0, 0 +0xe7 0x00 0x00 0x08 0x30 0xee + +# CHECK: wfmindb %f0, %f0, %f0, 4 +0xe7 0x00 0x00 0x48 0x30 0xee + +# CHECK: wfmindb %f0, %f0, %v31, 0 +0xe7 0x00 0xf0 0x08 0x32 0xee + +# CHECK: wfmindb %f0, %v31, %f0, 0 +0xe7 0x0f 0x00 0x08 0x34 0xee + +# CHECK: wfmindb %v31, %f0, %f0, 0 +0xe7 0xf0 0x00 0x08 0x38 0xee + +# CHECK: wfmindb %v18, %f3, %v20, 11 +0xe7 0x23 0x40 0xb8 0x3a 0xee + +# CHECK: wfnmadb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x9f + +# CHECK: wfnmadb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x9f + +# CHECK: wfnmadb %f0, %f0, %f0, %v31 +0xe7 0x00 0x03 0x08 0xf1 0x9f + +# CHECK: wfnmadb %f0, %f0, %v31, %f0 +0xe7 0x00 0xf3 0x08 0x02 0x9f + +# CHECK: wfnmadb %f0, %v31, %f0, %f0 +0xe7 0x0f 0x03 0x08 0x04 0x9f + +# CHECK: wfnmadb %v31, %f0, %f0, %f0 +0xe7 0xf0 0x03 0x08 0x08 0x9f + +# CHECK: wfnmadb %f13, %v17, %v21, %v25 +0xe7 0xd1 0x53 0x08 0x97 0x9f + +# CHECK: wfnmsdb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x9e + +# CHECK: wfnmsdb %f0, %f0, %f0, %f0 +0xe7 0x00 0x03 0x08 0x00 0x9e + +# CHECK: wfnmsdb %f0, %f0, %f0, %v31 +0xe7 0x00 0x03 0x08 0xf1 0x9e + +# CHECK: wfnmsdb %f0, %f0, %v31, %f0 +0xe7 0x00 0xf3 0x08 0x02 0x9e + +# CHECK: wfnmsdb %f0, %v31, %f0, %f0 +0xe7 0x0f 0x03 0x08 0x04 0x9e + +# CHECK: wfnmsdb %v31, %f0, %f0, %f0 +0xe7 0xf0 0x03 0x08 0x08 0x9e + +# CHECK: wfnmsdb %f13, %v17, %v21, %v25 +0xe7 0xd1 0x53 0x08 0x97 0x9e + diff --git a/test/MC/SystemZ/insn-bad-z13.s b/test/MC/SystemZ/insn-bad-z13.s index e9fac44aa88..7bf5b5303dd 100644 --- a/test/MC/SystemZ/insn-bad-z13.s +++ b/test/MC/SystemZ/insn-bad-z13.s @@ -4,6 +4,19 @@ # RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch11 < %s 2> %t # RUN: FileCheck < %t %s +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: agh %r0, 0 + + agh %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: bi 0 +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: bic 0, 0 + + bi 0 + bic 0, 0 + #CHECK: error: invalid operand #CHECK: cdpt %f0, 0(1), -1 #CHECK: error: invalid operand @@ -150,6 +163,16 @@ cxpt %f0, 0(-), 0 cxpt %f15, 0(1), 0 +#CHECK: error: instruction requires: insert-reference-bits-multiple +#CHECK: irbm %r0, %r0 + + irbm %r0, %r0 + +#CHECK: error: instruction requires: message-security-assist-extension8 +#CHECK: kma %r2, %r4, %r6 + + kma %r2, %r4, %r6 + #CHECK: error: invalid operand #CHECK: lcbb %r0, 0, -1 #CHECK: error: invalid operand @@ -167,6 +190,21 @@ lcbb %r0, 4096, 0 lcbb %r0, 0(%v1,%r2), 0 +#CHECK: error: instruction requires: guarded-storage +#CHECK: lgg %r0, 0 + + lgg %r0, 0 + +#CHECK: error: instruction requires: guarded-storage +#CHECK: lgsc %r0, 0 + + lgsc %r0, 0 + +#CHECK: error: instruction requires: guarded-storage +#CHECK: llgfsg %r0, 0 + + llgfsg %r0, 0 + #CHECK: error: invalid operand #CHECK: llzrgf %r0, -524289 #CHECK: error: invalid operand @@ -249,6 +287,41 @@ lzrg %r0, -524289 lzrg %r0, 524288 +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: mg %r0, 0 + + mg %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: mgh %r0, 0 + + mgh %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: mgrk %r0, %r0, %r0 + + mgrk %r0, %r0, %r0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: msc %r0, 0 + + msc %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: msgc %r0, 0 + + msgc %r0, 0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: msrkc %r0, %r0, %r0 + + msrkc %r0, %r0, %r0 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: msgrkc %r0, %r0, %r0 + + msgrkc %r0, %r0, %r0 + #CHECK: error: invalid register pair #CHECK: ppno %r1, %r2 #CHECK: error: invalid register pair @@ -257,6 +330,21 @@ ppno %r1, %r2 ppno %r2, %r1 +#CHECK: error: instruction requires: message-security-assist-extension7 +#CHECK: prno %r2, %r4 + + prno %r2, %r4 + +#CHECK: error: instruction requires: miscellaneous-extensions-2 +#CHECK: sgh %r0, 0 + + sgh %r0, 0 + +#CHECK: error: instruction requires: guarded-storage +#CHECK: stgsc %r0, 0 + + stgsc %r0, 0 + #CHECK: error: invalid operand #CHECK: stocfh %r0, 0, -1 #CHECK: error: invalid operand @@ -274,6 +362,16 @@ stocfh %r0, 524288, 1 stocfh %r0, 0(%r1,%r2), 1 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vap %v0, %v0, %v0, 0, 0 + + vap %v0, %v0, %v0, 0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vbperm %v0, %v0, %v0 + + vbperm %v0, %v0, %v0 + #CHECK: error: invalid operand #CHECK: vcdg %v0, %v0, 0, 0, -1 #CHECK: error: invalid operand @@ -410,6 +508,35 @@ vclgdb %v0, %v0, -1, 0 vclgdb %v0, %v0, 16, 0 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vcp %v0, %v0, 0 + + vcp %v0, %v0, 0 + +#CHECK: vcvb %r0, %v0, 0 + + vcvb %r0, %v0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vcvbg %r0, %v0, 0 + + vcvbg %r0, %v0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vcvd %v0, %r0, 0, 0 + + vcvd %v0, %r0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vcvdg %v0, %r0, 0, 0 + + vcvdg %v0, %r0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vdp %v0, %v0, %v0, 0, 0 + + vdp %v0, %v0, %v0, 0, 0 + #CHECK: error: invalid operand #CHECK: verim %v0, %v0, %v0, 0, -1 #CHECK: error: invalid operand @@ -1130,6 +1257,62 @@ vfidb %v0, %v0, -1, 0 vfidb %v0, %v0, 16, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkedb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkedbs %v0, %v0, %v0 + + vfkedb %v0, %v0, %v0 + vfkedbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkhdb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkhdbs %v0, %v0, %v0 + + vfkhdb %v0, %v0, %v0 + vfkhdbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkhedb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfkhedbs %v0, %v0, %v0 + + vfkhedb %v0, %v0, %v0 + vfkhedbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfmax %v0, %v0, %v0, 0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfmaxdb %v0, %v0, %v0, 0 + + vfmax %v0, %v0, %v0, 0, 0, 0 + vfmaxdb %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfmin %v0, %v0, %v0, 0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfmindb %v0, %v0, %v0, 0 + + vfmin %v0, %v0, %v0, 0, 0, 0 + vfmindb %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfnmadb %v0, %v0, %v0, %v0 + + vfnma %v0, %v0, %v0, %v0, 0, 0 + vfnmadb %v0, %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vfnmsdb %v0, %v0, %v0, %v0 + + vfnms %v0, %v0, %v0, %v0, 0, 0 + vfnmsdb %v0, %v0, %v0, %v0 + #CHECK: error: invalid operand #CHECK: vftci %v0, %v0, 0, 0, -1 #CHECK: error: invalid operand @@ -1615,6 +1798,11 @@ vlgvh %r0, %v0, 4096 vlgvh %r0, %v0, 0(%r0) +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vlip %v0, 0, 0 + + vlip %v0, 0, 0 + #CHECK: error: invalid operand #CHECK: vll %v0, %r0, -1 #CHECK: error: invalid operand @@ -1687,6 +1875,11 @@ vllezh %v0, 4096 vllezh %v0, 0(%v1,%r2) +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vllezlf %v0, 0 + + vllezlf %v0, 0 + #CHECK: error: invalid operand #CHECK: vlm %v0, %v0, -1 #CHECK: error: invalid operand @@ -1756,6 +1949,16 @@ vlreph %v0, 4096 vlreph %v0, 0(%v1,%r2) +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vlrl %v0, 0, 0 + + vlrl %v0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vlrlr %v0, %r0, 0 + + vlrlr %v0, %r0, 0 + #CHECK: error: invalid operand #CHECK: vlvg %v0, %r0, 0, -1 #CHECK: error: invalid operand @@ -1817,6 +2020,39 @@ vlvgh %v0, %r0, 4096 vlvgh %v0, %r0, 0(%r0) +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vmp %v0, %v0, %v0, 0, 0 + + vmp %v0, %v0, %v0, 0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vmslg %v0, %v0, %v0, %v0, 0 + + vmsl %v0, %v0, %v0, %v0, 0, 0 + vmslg %v0, %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vmsp %v0, %v0, %v0, 0, 0 + + vmsp %v0, %v0, %v0, 0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vnn %v0, %v0, %v0 + + vnn %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vnx %v0, %v0, %v0 + + vnx %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: voc %v0, %v0, %v0 + + voc %v0, %v0, %v0 + #CHECK: error: invalid operand #CHECK: vpdi %v0, %v0, %v0, -1 #CHECK: error: invalid operand @@ -1825,6 +2061,30 @@ vpdi %v0, %v0, %v0, -1 vpdi %v0, %v0, %v0, 16 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vpkz %v0, 0, 0 + + vpkz %v0, 0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vpopctb %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vpopctf %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vpopctg %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: vpopcth %v0, %v0 + + vpopctb %v0, %v0 + vpopctf %v0, %v0 + vpopctg %v0, %v0 + vpopcth %v0, %v0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vpsop %v0, %v0, 0, 0, 0 + + vpsop %v0, %v0, 0, 0, 0 + #CHECK: error: invalid operand #CHECK: vrep %v0, %v0, 0, -1 #CHECK: error: invalid operand @@ -1917,6 +2177,11 @@ vrepih %v0, -32769 vrepih %v0, 32768 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vrp %v0, %v0, %v0, 0, 0 + + vrp %v0, %v0, %v0, 0, 0 + #CHECK: error: vector index required #CHECK: vscef %v0, 0(%r1), 0 #CHECK: error: vector index required @@ -1957,6 +2222,11 @@ vsceg %v0, -1(%v0,%r1), 0 vsceg %v0, 4096(%v0,%r1), 0 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vsdp %v0, %v0, %v0, 0, 0 + + vsdp %v0, %v0, %v0, 0, 0 + #CHECK: error: invalid operand #CHECK: vsldb %v0, %v0, %v0, -1 #CHECK: error: invalid operand @@ -1965,6 +2235,16 @@ vsldb %v0, %v0, %v0, -1 vsldb %v0, %v0, %v0, 256 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vsp %v0, %v0, %v0, 0, 0 + + vsp %v0, %v0, %v0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vsrp %v0, %v0, 0, 0, 0 + + vsrp %v0, %v0, 0, 0, 0 + #CHECK: error: invalid operand #CHECK: vst %v0, -1 #CHECK: error: invalid operand @@ -2251,6 +2531,26 @@ vstrczhs %v0, %v0, %v0 vstrczhs %v0, %v0, %v0, %v0, 0, 0 +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vstrl %v0, 0, 0 + + vstrl %v0, 0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vstrlr %v0, %r0, 0 + + vstrlr %v0, %r0, 0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vtp %v0 + + vtp %v0 + +#CHECK: error: instruction requires: vector-packed-decimal +#CHECK: vupkz %v0, 0, 0 + + vupkz %v0, 0, 0 + #CHECK: error: invalid operand #CHECK: wcdgb %v0, %v0, 0, -1 #CHECK: error: invalid operand @@ -2321,6 +2621,50 @@ wfidb %v0, %v0, -1, 0 wfidb %v0, %v0, 16, 0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkedb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkedbs %v0, %v0, %v0 + + wfkedb %v0, %v0, %v0 + wfkedbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkhdb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkhdbs %v0, %v0, %v0 + + wfkhdb %v0, %v0, %v0 + wfkhdbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkhedb %v0, %v0, %v0 +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfkhedbs %v0, %v0, %v0 + + wfkhedb %v0, %v0, %v0 + wfkhedbs %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfmaxdb %v0, %v0, %v0, 0 + + wfmaxdb %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfmindb %v0, %v0, %v0, 0 + + wfmindb %v0, %v0, %v0, 0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfnmadb %v0, %v0, %v0, %v0 + + wfnmadb %v0, %v0, %v0, %v0 + +#CHECK: error: instruction requires: vector-enhancements-1 +#CHECK: wfnmsdb %v0, %v0, %v0, %v0 + + wfnmsdb %v0, %v0, %v0, %v0 + #CHECK: error: invalid operand #CHECK: wftcidb %v0, %v0, -1 #CHECK: error: invalid operand diff --git a/test/MC/SystemZ/insn-bad-z14.s b/test/MC/SystemZ/insn-bad-z14.s new file mode 100644 index 00000000000..4e0a250810a --- /dev/null +++ b/test/MC/SystemZ/insn-bad-z14.s @@ -0,0 +1,562 @@ +# For z14 only. +# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=z14 < %s 2> %t +# RUN: FileCheck < %t %s +# RUN: not llvm-mc -triple s390x-linux-gnu -mcpu=arch12 < %s 2> %t +# RUN: FileCheck < %t %s + +#CHECK: error: invalid operand +#CHECK: bi -524289 +#CHECK: error: invalid operand +#CHECK: bi 524288 + + bi -524289 + bi 524288 + +#CHECK: error: invalid operand +#CHECK: bic -1, 0(%r1) +#CHECK: error: invalid operand +#CHECK: bic 16, 0(%r1) +#CHECK: error: invalid operand +#CHECK: bic 0, -524289 +#CHECK: error: invalid operand +#CHECK: bic 0, 524288 + + bic -1, 0(%r1) + bic 16, 0(%r1) + bic 0, -524289 + bic 0, 524288 + +#CHECK: error: invalid operand +#CHECK: agh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: agh %r0, 524288 + + agh %r0, -524289 + agh %r0, 524288 + +#CHECK: error: invalid register pair +#CHECK: kma %r1, %r2, %r4 +#CHECK: error: invalid register pair +#CHECK: kma %r2, %r1, %r4 +#CHECK: error: invalid register pair +#CHECK: kma %r2, %r4, %r1 + + kma %r1, %r2, %r4 + kma %r2, %r1, %r4 + kma %r2, %r4, %r1 + +#CHECK: error: invalid operand +#CHECK: lgg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lgg %r0, 524288 + + lgg %r0, -524289 + lgg %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: lgsc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: lgsc %r0, 524288 + + lgsc %r0, -524289 + lgsc %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: llgfsg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: llgfsg %r0, 524288 + + llgfsg %r0, -524289 + llgfsg %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: mg %r0, -524289 +#CHECK: error: invalid operand +#CHECK: mg %r0, 524288 +#CHECK: error: invalid register pair +#CHECK: mg %r1, 0 + + mg %r0, -524289 + mg %r0, 524288 + mg %r1, 0 + +#CHECK: error: invalid operand +#CHECK: mgh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: mgh %r0, 524288 + + mgh %r0, -524289 + mgh %r0, 524288 + +#CHECK: error: invalid register pair +#CHECK: mgrk %r1, %r0, %r0 + + mgrk %r1, %r0, %r0 + +#CHECK: error: invalid operand +#CHECK: msc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: msc %r0, 524288 + + msc %r0, -524289 + msc %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: msgc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: msgc %r0, 524288 + + msgc %r0, -524289 + msgc %r0, 524288 + +#CHECK: error: invalid register pair +#CHECK: prno %r1, %r2 +#CHECK: error: invalid register pair +#CHECK: prno %r2, %r1 + + prno %r1, %r2 + prno %r2, %r1 + +#CHECK: error: invalid operand +#CHECK: sgh %r0, -524289 +#CHECK: error: invalid operand +#CHECK: sgh %r0, 524288 + + sgh %r0, -524289 + sgh %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: stgsc %r0, -524289 +#CHECK: error: invalid operand +#CHECK: stgsc %r0, 524288 + + stgsc %r0, -524289 + stgsc %r0, 524288 + +#CHECK: error: invalid operand +#CHECK: vap %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vap %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vap %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vap %v0, %v0, %v0, 256, 0 + + vap %v0, %v0, %v0, 0, -1 + vap %v0, %v0, %v0, 0, 16 + vap %v0, %v0, %v0, -1, 0 + vap %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vcp %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vcp %v0, %v0, 16 + + vcp %v0, %v0, -1 + vcp %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vcvb %r0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vcvb %r0, %v0, 16 + + vcvb %r0, %v0, -1 + vcvb %r0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vcvbg %r0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vcvbg %r0, %v0, 16 + + vcvbg %r0, %v0, -1 + vcvbg %r0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vcvd %r0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vcvd %r0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vcvd %r0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vcvd %r0, %v0, 256, 0 + + vcvd %r0, %v0, 0, -1 + vcvd %r0, %v0, 0, 16 + vcvd %r0, %v0, -1, 0 + vcvd %r0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vcvdg %r0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vcvdg %r0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vcvdg %r0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vcvdg %r0, %v0, 256, 0 + + vcvdg %r0, %v0, 0, -1 + vcvdg %r0, %v0, 0, 16 + vcvdg %r0, %v0, -1, 0 + vcvdg %r0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vdp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vdp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vdp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vdp %v0, %v0, %v0, 256, 0 + + vdp %v0, %v0, %v0, 0, -1 + vdp %v0, %v0, %v0, 0, 16 + vdp %v0, %v0, %v0, -1, 0 + vdp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 0, 16, 0 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: vfmax %v0, %v0, %v0, 16, 0, 0 + + vfmax %v0, %v0, %v0, 0, 0, -1 + vfmax %v0, %v0, %v0, 0, 0, 16 + vfmax %v0, %v0, %v0, 0, -1, 0 + vfmax %v0, %v0, %v0, 0, 16, 0 + vfmax %v0, %v0, %v0, -1, 0, 0 + vfmax %v0, %v0, %v0, 16, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfmaxdb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfmaxdb %v0, %v0, %v0, 16 + + vfmaxdb %v0, %v0, %v0, -1 + vfmaxdb %v0, %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 0, 16, 0 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: vfmin %v0, %v0, %v0, 16, 0, 0 + + vfmin %v0, %v0, %v0, 0, 0, -1 + vfmin %v0, %v0, %v0, 0, 0, 16 + vfmin %v0, %v0, %v0, 0, -1, 0 + vfmin %v0, %v0, %v0, 0, 16, 0 + vfmin %v0, %v0, %v0, -1, 0, 0 + vfmin %v0, %v0, %v0, 16, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vfmindb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vfmindb %v0, %v0, %v0, 16 + + vfmindb %v0, %v0, %v0, -1 + vfmindb %v0, %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vfnma %v0, %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vfnma %v0, %v0, %v0, %v0, 16, 0 + + vfnma %v0, %v0, %v0, %v0, 0, -1 + vfnma %v0, %v0, %v0, %v0, 0, 16 + vfnma %v0, %v0, %v0, %v0, -1, 0 + vfnma %v0, %v0, %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vfnms %v0, %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vfnms %v0, %v0, %v0, %v0, 16, 0 + + vfnms %v0, %v0, %v0, %v0, 0, -1 + vfnms %v0, %v0, %v0, %v0, 0, 16 + vfnms %v0, %v0, %v0, %v0, -1, 0 + vfnms %v0, %v0, %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vlip %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vlip %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vlip %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vlip %v0, 65536, 0 + + vlip %v0, 0, -1 + vlip %v0, 0, 16 + vlip %v0, -1, 0 + vlip %v0, 65536, 0 + +#CHECK: error: invalid operand +#CHECK: vllezlf %v0, -1 +#CHECK: error: invalid operand +#CHECK: vllezlf %v0, 4096 +#CHECK: error: invalid use of vector addressing +#CHECK: vllezlf %v0, 0(%v1,%r2) + + vllezlf %v0, -1 + vllezlf %v0, 4096 + vllezlf %v0, 0(%v1,%r2) + +#CHECK: error: invalid operand +#CHECK: vlrl %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vlrl %v0, 0, 256 +#CHECK: error: invalid operand +#CHECK: vlrl %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vlrl %v0, 4096, 0 +#CHECK: error: %r0 used in an address +#CHECK: vlrl %v0, 0(%r0), 0 + + vlrl %v0, 0, -1 + vlrl %v0, 0, 256 + vlrl %v0, -1, 0 + vlrl %v0, 4096, 0 + vlrl %v0, 0(%r0), 0 + +#CHECK: error: invalid operand +#CHECK: vlrlr %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vlrlr %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vlrlr %v0, %r0, 0(%r0) + + vlrlr %v0, %r0, -1 + vlrlr %v0, %r0, 4096 + vlrlr %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vmp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vmp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vmp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vmp %v0, %v0, %v0, 256, 0 + + vmp %v0, %v0, %v0, 0, -1 + vmp %v0, %v0, %v0, 0, 16 + vmp %v0, %v0, %v0, -1, 0 + vmp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vmsp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vmsp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vmsp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vmsp %v0, %v0, %v0, 256, 0 + + vmsp %v0, %v0, %v0, 0, -1 + vmsp %v0, %v0, %v0, 0, 16 + vmsp %v0, %v0, %v0, -1, 0 + vmsp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vmsl %v0, %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vmsl %v0, %v0, %v0, %v0, 16, 0 + + vmsl %v0, %v0, %v0, %v0, 0, -1 + vmsl %v0, %v0, %v0, %v0, 0, 16 + vmsl %v0, %v0, %v0, %v0, -1, 0 + vmsl %v0, %v0, %v0, %v0, 16, 0 + +#CHECK: error: invalid operand +#CHECK: vmslg %v0, %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: vmslg %v0, %v0, %v0, %v0, 16 + + vmslg %v0, %v0, %v0, %v0, -1 + vmslg %v0, %v0, %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: vpkz %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vpkz %v0, 0, 256 +#CHECK: error: invalid operand +#CHECK: vpkz %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vpkz %v0, 4096, 0 +#CHECK: error: %r0 used in an address +#CHECK: vpkz %v0, 0(%r0), 0 + + vpkz %v0, 0, -1 + vpkz %v0, 0, 256 + vpkz %v0, -1, 0 + vpkz %v0, 4096, 0 + vpkz %v0, 0(%r0), 0 + +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 0, 256, 0 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: vpsop %v0, %v0, 256, 0, 0 + + vpsop %v0, %v0, 0, 0, -1 + vpsop %v0, %v0, 0, 0, 16 + vpsop %v0, %v0, 0, -1, 0 + vpsop %v0, %v0, 0, 256, 0 + vpsop %v0, %v0, -1, 0, 0 + vpsop %v0, %v0, 256, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vrp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vrp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vrp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vrp %v0, %v0, %v0, 256, 0 + + vrp %v0, %v0, %v0, 0, -1 + vrp %v0, %v0, %v0, 0, 16 + vrp %v0, %v0, %v0, -1, 0 + vrp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vsdp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vsdp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vsdp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vsdp %v0, %v0, %v0, 256, 0 + + vsdp %v0, %v0, %v0, 0, -1 + vsdp %v0, %v0, %v0, 0, 16 + vsdp %v0, %v0, %v0, -1, 0 + vsdp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vsp %v0, %v0, %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vsp %v0, %v0, %v0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vsp %v0, %v0, %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vsp %v0, %v0, %v0, 256, 0 + + vsp %v0, %v0, %v0, 0, -1 + vsp %v0, %v0, %v0, 0, 16 + vsp %v0, %v0, %v0, -1, 0 + vsp %v0, %v0, %v0, 256, 0 + +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 0, 0, 16 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 0, 256, 0 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, -1, 0, 0 +#CHECK: error: invalid operand +#CHECK: vsrp %v0, %v0, 256, 0, 0 + + vsrp %v0, %v0, 0, 0, -1 + vsrp %v0, %v0, 0, 0, 16 + vsrp %v0, %v0, 0, -1, 0 + vsrp %v0, %v0, 0, 256, 0 + vsrp %v0, %v0, -1, 0, 0 + vsrp %v0, %v0, 256, 0, 0 + +#CHECK: error: invalid operand +#CHECK: vstrl %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vstrl %v0, 0, 256 +#CHECK: error: invalid operand +#CHECK: vstrl %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vstrl %v0, 4096, 0 +#CHECK: error: %r0 used in an address +#CHECK: vstrl %v0, 0(%r0), 0 + + vstrl %v0, 0, -1 + vstrl %v0, 0, 256 + vstrl %v0, -1, 0 + vstrl %v0, 4096, 0 + vstrl %v0, 0(%r0), 0 + +#CHECK: error: invalid operand +#CHECK: vstrlr %v0, %r0, -1 +#CHECK: error: invalid operand +#CHECK: vstrlr %v0, %r0, 4096 +#CHECK: error: %r0 used in an address +#CHECK: vstrlr %v0, %r0, 0(%r0) + + vstrlr %v0, %r0, -1 + vstrlr %v0, %r0, 4096 + vstrlr %v0, %r0, 0(%r0) + +#CHECK: error: invalid operand +#CHECK: vupkz %v0, 0, -1 +#CHECK: error: invalid operand +#CHECK: vupkz %v0, 0, 256 +#CHECK: error: invalid operand +#CHECK: vupkz %v0, -1, 0 +#CHECK: error: invalid operand +#CHECK: vupkz %v0, 4096, 0 +#CHECK: error: %r0 used in an address +#CHECK: vupkz %v0, 0(%r0), 0 + + vupkz %v0, 0, -1 + vupkz %v0, 0, 256 + vupkz %v0, -1, 0 + vupkz %v0, 4096, 0 + vupkz %v0, 0(%r0), 0 + +#CHECK: error: invalid operand +#CHECK: wfmaxdb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: wfmaxdb %v0, %v0, %v0, 16 + + wfmaxdb %v0, %v0, %v0, -1 + wfmaxdb %v0, %v0, %v0, 16 + +#CHECK: error: invalid operand +#CHECK: wfmindb %v0, %v0, %v0, -1 +#CHECK: error: invalid operand +#CHECK: wfmindb %v0, %v0, %v0, 16 + + wfmindb %v0, %v0, %v0, -1 + wfmindb %v0, %v0, %v0, 16 + diff --git a/test/MC/SystemZ/insn-good-z14.s b/test/MC/SystemZ/insn-good-z14.s new file mode 100644 index 00000000000..c247f252659 --- /dev/null +++ b/test/MC/SystemZ/insn-good-z14.s @@ -0,0 +1,1282 @@ +# For z14 and above. +# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=z14 -show-encoding %s \ +# RUN: | FileCheck %s +# RUN: llvm-mc -triple s390x-linux-gnu -mcpu=arch12 -show-encoding %s \ +# RUN: | FileCheck %s + +#CHECK: agh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x38] +#CHECK: agh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x38] +#CHECK: agh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x38] +#CHECK: agh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x38] +#CHECK: agh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x38] +#CHECK: agh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x38] +#CHECK: agh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x38] +#CHECK: agh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x38] +#CHECK: agh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x38] +#CHECK: agh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x38] + + agh %r0, -524288 + agh %r0, -1 + agh %r0, 0 + agh %r0, 1 + agh %r0, 524287 + agh %r0, 0(%r1) + agh %r0, 0(%r15) + agh %r0, 524287(%r1,%r15) + agh %r0, 524287(%r15,%r1) + agh %r15, 0 + +#CHECK: bi -524288 # encoding: [0xe3,0xf0,0x00,0x00,0x80,0x47] +#CHECK: bi -1 # encoding: [0xe3,0xf0,0x0f,0xff,0xff,0x47] +#CHECK: bi 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x47] +#CHECK: bi 1 # encoding: [0xe3,0xf0,0x00,0x01,0x00,0x47] +#CHECK: bi 524287 # encoding: [0xe3,0xf0,0x0f,0xff,0x7f,0x47] +#CHECK: bi 0(%r1) # encoding: [0xe3,0xf0,0x10,0x00,0x00,0x47] +#CHECK: bi 0(%r15) # encoding: [0xe3,0xf0,0xf0,0x00,0x00,0x47] +#CHECK: bi 524287(%r1,%r15) # encoding: [0xe3,0xf1,0xff,0xff,0x7f,0x47] +#CHECK: bi 524287(%r15,%r1) # encoding: [0xe3,0xff,0x1f,0xff,0x7f,0x47] + + bi -524288 + bi -1 + bi 0 + bi 1 + bi 524287 + bi 0(%r1) + bi 0(%r15) + bi 524287(%r1,%r15) + bi 524287(%r15,%r1) + +#CHECK: bic 0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x47] +#CHECK: bic 0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x47] +#CHECK: bic 0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x47] +#CHECK: bic 0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x47] +#CHECK: bic 0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x47] +#CHECK: bic 0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x47] +#CHECK: bic 0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x47] +#CHECK: bic 0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x47] +#CHECK: bic 0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x47] +#CHECK: bic 15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x47] + + bic 0, -524288 + bic 0, -1 + bic 0, 0 + bic 0, 1 + bic 0, 524287 + bic 0, 0(%r1) + bic 0, 0(%r15) + bic 0, 524287(%r1,%r15) + bic 0, 524287(%r15,%r1) + bic 15, 0 + +#CHECK: bic 1, 0(%r7) # encoding: [0xe3,0x10,0x70,0x00,0x00,0x47] +#CHECK: bio 0(%r15) # encoding: [0xe3,0x10,0xf0,0x00,0x00,0x47] + + bic 1, 0(%r7) + bio 0(%r15) + +#CHECK: bic 2, 0(%r7) # encoding: [0xe3,0x20,0x70,0x00,0x00,0x47] +#CHECK: bih 0(%r15) # encoding: [0xe3,0x20,0xf0,0x00,0x00,0x47] + + bic 2, 0(%r7) + bih 0(%r15) + +#CHECK: bic 3, 0(%r7) # encoding: [0xe3,0x30,0x70,0x00,0x00,0x47] +#CHECK: binle 0(%r15) # encoding: [0xe3,0x30,0xf0,0x00,0x00,0x47] + + bic 3, 0(%r7) + binle 0(%r15) + +#CHECK: bic 4, 0(%r7) # encoding: [0xe3,0x40,0x70,0x00,0x00,0x47] +#CHECK: bil 0(%r15) # encoding: [0xe3,0x40,0xf0,0x00,0x00,0x47] + + bic 4, 0(%r7) + bil 0(%r15) + +#CHECK: bic 5, 0(%r7) # encoding: [0xe3,0x50,0x70,0x00,0x00,0x47] +#CHECK: binhe 0(%r15) # encoding: [0xe3,0x50,0xf0,0x00,0x00,0x47] + + bic 5, 0(%r7) + binhe 0(%r15) + +#CHECK: bic 6, 0(%r7) # encoding: [0xe3,0x60,0x70,0x00,0x00,0x47] +#CHECK: bilh 0(%r15) # encoding: [0xe3,0x60,0xf0,0x00,0x00,0x47] + + bic 6, 0(%r7) + bilh 0(%r15) + +#CHECK: bic 7, 0(%r7) # encoding: [0xe3,0x70,0x70,0x00,0x00,0x47] +#CHECK: bine 0(%r15) # encoding: [0xe3,0x70,0xf0,0x00,0x00,0x47] + + bic 7, 0(%r7) + bine 0(%r15) + +#CHECK: bic 8, 0(%r7) # encoding: [0xe3,0x80,0x70,0x00,0x00,0x47] +#CHECK: bie 0(%r15) # encoding: [0xe3,0x80,0xf0,0x00,0x00,0x47] + + bic 8, 0(%r7) + bie 0(%r15) + +#CHECK: bic 9, 0(%r7) # encoding: [0xe3,0x90,0x70,0x00,0x00,0x47] +#CHECK: binlh 0(%r15) # encoding: [0xe3,0x90,0xf0,0x00,0x00,0x47] + + bic 9, 0(%r7) + binlh 0(%r15) + +#CHECK: bic 10, 0(%r7) # encoding: [0xe3,0xa0,0x70,0x00,0x00,0x47] +#CHECK: bihe 0(%r15) # encoding: [0xe3,0xa0,0xf0,0x00,0x00,0x47] + + bic 10, 0(%r7) + bihe 0(%r15) + +#CHECK: bic 11, 0(%r7) # encoding: [0xe3,0xb0,0x70,0x00,0x00,0x47] +#CHECK: binl 0(%r15) # encoding: [0xe3,0xb0,0xf0,0x00,0x00,0x47] + + bic 11, 0(%r7) + binl 0(%r15) + +#CHECK: bic 12, 0(%r7) # encoding: [0xe3,0xc0,0x70,0x00,0x00,0x47] +#CHECK: bile 0(%r15) # encoding: [0xe3,0xc0,0xf0,0x00,0x00,0x47] + + bic 12, 0(%r7) + bile 0(%r15) + +#CHECK: bic 13, 0(%r7) # encoding: [0xe3,0xd0,0x70,0x00,0x00,0x47] +#CHECK: binh 0(%r15) # encoding: [0xe3,0xd0,0xf0,0x00,0x00,0x47] + + bic 13, 0(%r7) + binh 0(%r15) + +#CHECK: bic 14, 0(%r7) # encoding: [0xe3,0xe0,0x70,0x00,0x00,0x47] +#CHECK: bino 0(%r15) # encoding: [0xe3,0xe0,0xf0,0x00,0x00,0x47] + + bic 14, 0(%r7) + bino 0(%r15) + +#CHECK: irbm %r0, %r0 # encoding: [0xb9,0xac,0x00,0x00] +#CHECK: irbm %r0, %r15 # encoding: [0xb9,0xac,0x00,0x0f] +#CHECK: irbm %r15, %r0 # encoding: [0xb9,0xac,0x00,0xf0] +#CHECK: irbm %r7, %r8 # encoding: [0xb9,0xac,0x00,0x78] +#CHECK: irbm %r15, %r15 # encoding: [0xb9,0xac,0x00,0xff] + + irbm %r0,%r0 + irbm %r0,%r15 + irbm %r15,%r0 + irbm %r7,%r8 + irbm %r15,%r15 + +#CHECK: kma %r2, %r2, %r2 # encoding: [0xb9,0x29,0x20,0x22] +#CHECK: kma %r2, %r8, %r14 # encoding: [0xb9,0x29,0x80,0x2e] +#CHECK: kma %r14, %r8, %r2 # encoding: [0xb9,0x29,0x80,0xe2] +#CHECK: kma %r6, %r8, %r10 # encoding: [0xb9,0x29,0x80,0x6a] + + kma %r2, %r2, %r2 + kma %r2, %r8, %r14 + kma %r14, %r8, %r2 + kma %r6, %r8, %r10 + +#CHECK: lgg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x4c] +#CHECK: lgg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x4c] +#CHECK: lgg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x4c] +#CHECK: lgg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x4c] +#CHECK: lgg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x4c] +#CHECK: lgg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x4c] +#CHECK: lgg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x4c] +#CHECK: lgg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x4c] +#CHECK: lgg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x4c] +#CHECK: lgg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x4c] + + lgg %r0, -524288 + lgg %r0, -1 + lgg %r0, 0 + lgg %r0, 1 + lgg %r0, 524287 + lgg %r0, 0(%r1) + lgg %r0, 0(%r15) + lgg %r0, 524287(%r1,%r15) + lgg %r0, 524287(%r15,%r1) + lgg %r15, 0 + +#CHECK: lgsc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x4d] +#CHECK: lgsc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x4d] +#CHECK: lgsc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x4d] +#CHECK: lgsc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x4d] +#CHECK: lgsc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x4d] +#CHECK: lgsc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x4d] +#CHECK: lgsc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x4d] +#CHECK: lgsc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x4d] +#CHECK: lgsc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x4d] + + lgsc %r0, -524288 + lgsc %r0, -1 + lgsc %r0, 0 + lgsc %r0, 1 + lgsc %r0, 524287 + lgsc %r0, 0(%r1) + lgsc %r0, 0(%r15) + lgsc %r0, 524287(%r1,%r15) + lgsc %r0, 524287(%r15,%r1) + +#CHECK: llgfsg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x48] +#CHECK: llgfsg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x48] +#CHECK: llgfsg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x48] +#CHECK: llgfsg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x48] +#CHECK: llgfsg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x48] +#CHECK: llgfsg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x48] +#CHECK: llgfsg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x48] +#CHECK: llgfsg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x48] +#CHECK: llgfsg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x48] +#CHECK: llgfsg %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x48] + + llgfsg %r0, -524288 + llgfsg %r0, -1 + llgfsg %r0, 0 + llgfsg %r0, 1 + llgfsg %r0, 524287 + llgfsg %r0, 0(%r1) + llgfsg %r0, 0(%r15) + llgfsg %r0, 524287(%r1,%r15) + llgfsg %r0, 524287(%r15,%r1) + llgfsg %r15, 0 + +#CHECK: mg %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x84] +#CHECK: mg %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x84] +#CHECK: mg %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x84] +#CHECK: mg %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x84] +#CHECK: mg %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x84] +#CHECK: mg %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x84] +#CHECK: mg %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x84] +#CHECK: mg %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x84] +#CHECK: mg %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x84] +#CHECK: mg %r14, 0 # encoding: [0xe3,0xe0,0x00,0x00,0x00,0x84] + + mg %r0, -524288 + mg %r0, -1 + mg %r0, 0 + mg %r0, 1 + mg %r0, 524287 + mg %r0, 0(%r1) + mg %r0, 0(%r15) + mg %r0, 524287(%r1,%r15) + mg %r0, 524287(%r15,%r1) + mg %r14, 0 + +#CHECK: mgh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x3c] +#CHECK: mgh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x3c] +#CHECK: mgh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x3c] +#CHECK: mgh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x3c] +#CHECK: mgh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x3c] +#CHECK: mgh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x3c] +#CHECK: mgh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x3c] +#CHECK: mgh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x3c] +#CHECK: mgh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x3c] +#CHECK: mgh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x3c] + + mgh %r0, -524288 + mgh %r0, -1 + mgh %r0, 0 + mgh %r0, 1 + mgh %r0, 524287 + mgh %r0, 0(%r1) + mgh %r0, 0(%r15) + mgh %r0, 524287(%r1,%r15) + mgh %r0, 524287(%r15,%r1) + mgh %r15, 0 + +#CHECK: mgrk %r0, %r0, %r0 # encoding: [0xb9,0xec,0x00,0x00] +#CHECK: mgrk %r0, %r0, %r15 # encoding: [0xb9,0xec,0xf0,0x00] +#CHECK: mgrk %r0, %r15, %r0 # encoding: [0xb9,0xec,0x00,0x0f] +#CHECK: mgrk %r14, %r0, %r0 # encoding: [0xb9,0xec,0x00,0xe0] +#CHECK: mgrk %r6, %r8, %r9 # encoding: [0xb9,0xec,0x90,0x68] + + mgrk %r0,%r0,%r0 + mgrk %r0,%r0,%r15 + mgrk %r0,%r15,%r0 + mgrk %r14,%r0,%r0 + mgrk %r6,%r8,%r9 + +#CHECK: msc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x53] +#CHECK: msc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x53] +#CHECK: msc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x53] +#CHECK: msc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x53] +#CHECK: msc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x53] +#CHECK: msc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x53] +#CHECK: msc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x53] +#CHECK: msc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x53] +#CHECK: msc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x53] +#CHECK: msc %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x53] + + msc %r0, -524288 + msc %r0, -1 + msc %r0, 0 + msc %r0, 1 + msc %r0, 524287 + msc %r0, 0(%r1) + msc %r0, 0(%r15) + msc %r0, 524287(%r1,%r15) + msc %r0, 524287(%r15,%r1) + msc %r15, 0 + +#CHECK: msgc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x83] +#CHECK: msgc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x83] +#CHECK: msgc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x83] +#CHECK: msgc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x83] +#CHECK: msgc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x83] +#CHECK: msgc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x83] +#CHECK: msgc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x83] +#CHECK: msgc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x83] +#CHECK: msgc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x83] +#CHECK: msgc %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x83] + + msgc %r0, -524288 + msgc %r0, -1 + msgc %r0, 0 + msgc %r0, 1 + msgc %r0, 524287 + msgc %r0, 0(%r1) + msgc %r0, 0(%r15) + msgc %r0, 524287(%r1,%r15) + msgc %r0, 524287(%r15,%r1) + msgc %r15, 0 + +#CHECK: msrkc %r0, %r0, %r0 # encoding: [0xb9,0xfd,0x00,0x00] +#CHECK: msrkc %r0, %r0, %r15 # encoding: [0xb9,0xfd,0xf0,0x00] +#CHECK: msrkc %r0, %r15, %r0 # encoding: [0xb9,0xfd,0x00,0x0f] +#CHECK: msrkc %r15, %r0, %r0 # encoding: [0xb9,0xfd,0x00,0xf0] +#CHECK: msrkc %r7, %r8, %r9 # encoding: [0xb9,0xfd,0x90,0x78] + + msrkc %r0,%r0,%r0 + msrkc %r0,%r0,%r15 + msrkc %r0,%r15,%r0 + msrkc %r15,%r0,%r0 + msrkc %r7,%r8,%r9 + +#CHECK: msgrkc %r0, %r0, %r0 # encoding: [0xb9,0xed,0x00,0x00] +#CHECK: msgrkc %r0, %r0, %r15 # encoding: [0xb9,0xed,0xf0,0x00] +#CHECK: msgrkc %r0, %r15, %r0 # encoding: [0xb9,0xed,0x00,0x0f] +#CHECK: msgrkc %r15, %r0, %r0 # encoding: [0xb9,0xed,0x00,0xf0] +#CHECK: msgrkc %r7, %r8, %r9 # encoding: [0xb9,0xed,0x90,0x78] + + msgrkc %r0,%r0,%r0 + msgrkc %r0,%r0,%r15 + msgrkc %r0,%r15,%r0 + msgrkc %r15,%r0,%r0 + msgrkc %r7,%r8,%r9 + +#CHECK: prno %r2, %r2 # encoding: [0xb9,0x3c,0x00,0x22] +#CHECK: prno %r2, %r14 # encoding: [0xb9,0x3c,0x00,0x2e] +#CHECK: prno %r14, %r2 # encoding: [0xb9,0x3c,0x00,0xe2] +#CHECK: prno %r6, %r10 # encoding: [0xb9,0x3c,0x00,0x6a] + + prno %r2, %r2 + prno %r2, %r14 + prno %r14, %r2 + prno %r6, %r10 + +#CHECK: sgh %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x39] +#CHECK: sgh %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x39] +#CHECK: sgh %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x39] +#CHECK: sgh %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x39] +#CHECK: sgh %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x39] +#CHECK: sgh %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x39] +#CHECK: sgh %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x39] +#CHECK: sgh %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x39] +#CHECK: sgh %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x39] +#CHECK: sgh %r15, 0 # encoding: [0xe3,0xf0,0x00,0x00,0x00,0x39] + + sgh %r0, -524288 + sgh %r0, -1 + sgh %r0, 0 + sgh %r0, 1 + sgh %r0, 524287 + sgh %r0, 0(%r1) + sgh %r0, 0(%r15) + sgh %r0, 524287(%r1,%r15) + sgh %r0, 524287(%r15,%r1) + sgh %r15, 0 + +#CHECK: stgsc %r0, -524288 # encoding: [0xe3,0x00,0x00,0x00,0x80,0x49] +#CHECK: stgsc %r0, -1 # encoding: [0xe3,0x00,0x0f,0xff,0xff,0x49] +#CHECK: stgsc %r0, 0 # encoding: [0xe3,0x00,0x00,0x00,0x00,0x49] +#CHECK: stgsc %r0, 1 # encoding: [0xe3,0x00,0x00,0x01,0x00,0x49] +#CHECK: stgsc %r0, 524287 # encoding: [0xe3,0x00,0x0f,0xff,0x7f,0x49] +#CHECK: stgsc %r0, 0(%r1) # encoding: [0xe3,0x00,0x10,0x00,0x00,0x49] +#CHECK: stgsc %r0, 0(%r15) # encoding: [0xe3,0x00,0xf0,0x00,0x00,0x49] +#CHECK: stgsc %r0, 524287(%r1,%r15) # encoding: [0xe3,0x01,0xff,0xff,0x7f,0x49] +#CHECK: stgsc %r0, 524287(%r15,%r1) # encoding: [0xe3,0x0f,0x1f,0xff,0x7f,0x49] + + stgsc %r0, -524288 + stgsc %r0, -1 + stgsc %r0, 0 + stgsc %r0, 1 + stgsc %r0, 524287 + stgsc %r0, 0(%r1) + stgsc %r0, 0(%r15) + stgsc %r0, 524287(%r1,%r15) + stgsc %r0, 524287(%r15,%r1) + +#CHECK: vap %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x71] +#CHECK: vap %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x71] +#CHECK: vap %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x71] +#CHECK: vap %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x71] +#CHECK: vap %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x71] +#CHECK: vap %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x71] +#CHECK: vap %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x71] + + vap %v0, %v0, %v0, 0, 0 + vap %v0, %v0, %v0, 0, 15 + vap %v0, %v0, %v0, 255, 0 + vap %v0, %v0, %v31, 0, 0 + vap %v0, %v31, %v0, 0, 0 + vap %v31, %v0, %v0, 0, 0 + vap %v13, %v17, %v21, 0x79, 11 + +#CHECK: vbperm %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x85] +#CHECK: vbperm %v0, %v0, %v15 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0x85] +#CHECK: vbperm %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x85] +#CHECK: vbperm %v0, %v15, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x85] +#CHECK: vbperm %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x85] +#CHECK: vbperm %v15, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x85] +#CHECK: vbperm %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x85] +#CHECK: vbperm %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x85] + + vbperm %v0, %v0, %v0 + vbperm %v0, %v0, %v15 + vbperm %v0, %v0, %v31 + vbperm %v0, %v15, %v0 + vbperm %v0, %v31, %v0 + vbperm %v15, %v0, %v0 + vbperm %v31, %v0, %v0 + vbperm %v18, %v3, %v20 + +#CHECK: vcp %v0, %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x77] +#CHECK: vcp %v0, %v0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x77] +#CHECK: vcp %v15, %v0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x77] +#CHECK: vcp %v31, %v0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x77] +#CHECK: vcp %v0, %v15, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x77] +#CHECK: vcp %v0, %v31, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x77] +#CHECK: vcp %v3, %v18, 4 # encoding: [0xe6,0x03,0x20,0x40,0x02,0x77] + + vcp %v0, %v0, 0 + vcp %v0, %v0, 15 + vcp %v15, %v0, 0 + vcp %v31, %v0, 0 + vcp %v0, %v15, 0 + vcp %v0, %v31, 0 + vcp %v3, %v18, 4 + +#CHECK: vcvb %r0, %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x50] +#CHECK: vcvb %r0, %v0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x50] +#CHECK: vcvb %r15, %v0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x50] +#CHECK: vcvb %r0, %v15, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x50] +#CHECK: vcvb %r0, %v31, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x50] +#CHECK: vcvb %r3, %v18, 4 # encoding: [0xe6,0x32,0x00,0x40,0x04,0x50] + + vcvb %r0, %v0, 0 + vcvb %r0, %v0, 15 + vcvb %r15, %v0, 0 + vcvb %r0, %v15, 0 + vcvb %r0, %v31, 0 + vcvb %r3, %v18, 4 + +#CHECK: vcvbg %r0, %v0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x52] +#CHECK: vcvbg %r0, %v0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x52] +#CHECK: vcvbg %r15, %v0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x52] +#CHECK: vcvbg %r0, %v15, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x52] +#CHECK: vcvbg %r0, %v31, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x52] +#CHECK: vcvbg %r3, %v18, 4 # encoding: [0xe6,0x32,0x00,0x40,0x04,0x52] + + vcvbg %r0, %v0, 0 + vcvbg %r0, %v0, 15 + vcvbg %r15, %v0, 0 + vcvbg %r0, %v15, 0 + vcvbg %r0, %v31, 0 + vcvbg %r3, %v18, 4 + +#CHECK: vcvd %v0, %r0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x58] +#CHECK: vcvd %v0, %r0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x58] +#CHECK: vcvd %v0, %r0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x58] +#CHECK: vcvd %v0, %r15, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x58] +#CHECK: vcvd %v15, %r0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x58] +#CHECK: vcvd %v31, %r0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x58] +#CHECK: vcvd %v18, %r9, 52, 11 # encoding: [0xe6,0x29,0x00,0xb3,0x48,0x58] + + vcvd %v0, %r0, 0, 0 + vcvd %v0, %r0, 0, 15 + vcvd %v0, %r0, 255, 0 + vcvd %v0, %r15, 0, 0 + vcvd %v15, %r0, 0, 0 + vcvd %v31, %r0, 0, 0 + vcvd %v18, %r9, 0x34, 11 + +#CHECK: vcvdg %v0, %r0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x5a] +#CHECK: vcvdg %v0, %r0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x5a] +#CHECK: vcvdg %v0, %r0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x5a] +#CHECK: vcvdg %v0, %r15, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x5a] +#CHECK: vcvdg %v15, %r0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x5a] +#CHECK: vcvdg %v31, %r0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x5a] +#CHECK: vcvdg %v18, %r9, 52, 11 # encoding: [0xe6,0x29,0x00,0xb3,0x48,0x5a] + + vcvdg %v0, %r0, 0, 0 + vcvdg %v0, %r0, 0, 15 + vcvdg %v0, %r0, 255, 0 + vcvdg %v0, %r15, 0, 0 + vcvdg %v15, %r0, 0, 0 + vcvdg %v31, %r0, 0, 0 + vcvdg %v18, %r9, 0x34, 11 + +#CHECK: vdp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x7a] +#CHECK: vdp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x7a] +#CHECK: vdp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x7a] +#CHECK: vdp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x7a] +#CHECK: vdp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x7a] +#CHECK: vdp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x7a] +#CHECK: vdp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x7a] + + vdp %v0, %v0, %v0, 0, 0 + vdp %v0, %v0, %v0, 0, 15 + vdp %v0, %v0, %v0, 255, 0 + vdp %v0, %v0, %v31, 0, 0 + vdp %v0, %v31, %v0, 0, 0 + vdp %v31, %v0, %v0, 0, 0 + vdp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vfkedb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xe8] +#CHECK: vfkedb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x04,0x32,0xe8] +#CHECK: vfkedb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x04,0x34,0xe8] +#CHECK: vfkedb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x04,0x38,0xe8] +#CHECK: vfkedb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x04,0x3a,0xe8] + + vfkedb %v0, %v0, %v0 + vfkedb %v0, %v0, %v31 + vfkedb %v0, %v31, %v0 + vfkedb %v31, %v0, %v0 + vfkedb %v18, %v3, %v20 + +#CHECK: vfkedbs %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x14,0x30,0xe8] +#CHECK: vfkedbs %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x14,0x32,0xe8] +#CHECK: vfkedbs %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x14,0x34,0xe8] +#CHECK: vfkedbs %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x14,0x38,0xe8] +#CHECK: vfkedbs %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x14,0x3a,0xe8] + + vfkedbs %v0, %v0, %v0 + vfkedbs %v0, %v0, %v31 + vfkedbs %v0, %v31, %v0 + vfkedbs %v31, %v0, %v0 + vfkedbs %v18, %v3, %v20 + +#CHECK: vfkhdb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xeb] +#CHECK: vfkhdb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x04,0x32,0xeb] +#CHECK: vfkhdb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x04,0x34,0xeb] +#CHECK: vfkhdb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x04,0x38,0xeb] +#CHECK: vfkhdb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x04,0x3a,0xeb] + + vfkhdb %v0, %v0, %v0 + vfkhdb %v0, %v0, %v31 + vfkhdb %v0, %v31, %v0 + vfkhdb %v31, %v0, %v0 + vfkhdb %v18, %v3, %v20 + +#CHECK: vfkhdbs %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x14,0x30,0xeb] +#CHECK: vfkhdbs %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x14,0x32,0xeb] +#CHECK: vfkhdbs %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x14,0x34,0xeb] +#CHECK: vfkhdbs %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x14,0x38,0xeb] +#CHECK: vfkhdbs %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x14,0x3a,0xeb] + + vfkhdbs %v0, %v0, %v0 + vfkhdbs %v0, %v0, %v31 + vfkhdbs %v0, %v31, %v0 + vfkhdbs %v31, %v0, %v0 + vfkhdbs %v18, %v3, %v20 + +#CHECK: vfkhedb %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x04,0x30,0xea] +#CHECK: vfkhedb %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x04,0x32,0xea] +#CHECK: vfkhedb %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x04,0x34,0xea] +#CHECK: vfkhedb %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x04,0x38,0xea] +#CHECK: vfkhedb %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x04,0x3a,0xea] + + vfkhedb %v0, %v0, %v0 + vfkhedb %v0, %v0, %v31 + vfkhedb %v0, %v31, %v0 + vfkhedb %v31, %v0, %v0 + vfkhedb %v18, %v3, %v20 + +#CHECK: vfkhedbs %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x14,0x30,0xea] +#CHECK: vfkhedbs %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x14,0x32,0xea] +#CHECK: vfkhedbs %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x14,0x34,0xea] +#CHECK: vfkhedbs %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x14,0x38,0xea] +#CHECK: vfkhedbs %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x14,0x3a,0xea] + + vfkhedbs %v0, %v0, %v0 + vfkhedbs %v0, %v0, %v31 + vfkhedbs %v0, %v31, %v0 + vfkhedbs %v31, %v0, %v0 + vfkhedbs %v18, %v3, %v20 + +#CHECK: vfmax %v0, %v0, %v0, 0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xef] +#CHECK: vfmax %v0, %v0, %v0, 15, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xef] +#CHECK: vfmax %v0, %v0, %v0, 0, 15, 0 # encoding: [0xe7,0x00,0x00,0x0f,0x00,0xef] +#CHECK: vfmax %v0, %v0, %v0, 0, 0, 4 # encoding: [0xe7,0x00,0x00,0x40,0x00,0xef] +#CHECK: vfmax %v0, %v0, %v31, 0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xef] +#CHECK: vfmax %v0, %v31, %v0, 0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xef] +#CHECK: vfmax %v31, %v0, %v0, 0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xef] +#CHECK: vfmax %v18, %v3, %v20, 11, 9, 12 # encoding: [0xe7,0x23,0x40,0xc9,0xba,0xef] + + vfmax %v0, %v0, %v0, 0, 0, 0 + vfmax %v0, %v0, %v0, 15, 0, 0 + vfmax %v0, %v0, %v0, 0, 15, 0 + vfmax %v0, %v0, %v0, 0, 0, 4 + vfmax %v0, %v0, %v31, 0, 0, 0 + vfmax %v0, %v31, %v0, 0, 0, 0 + vfmax %v31, %v0, %v0, 0, 0, 0 + vfmax %v18, %v3, %v20, 11, 9, 12 + +#CHECK: vfmaxdb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xef] +#CHECK: vfmaxdb %v0, %v0, %v0, 4 # encoding: [0xe7,0x00,0x00,0x40,0x30,0xef] +#CHECK: vfmaxdb %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xef] +#CHECK: vfmaxdb %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xef] +#CHECK: vfmaxdb %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xef] +#CHECK: vfmaxdb %v18, %v3, %v20, 12 # encoding: [0xe7,0x23,0x40,0xc0,0x3a,0xef] + + vfmaxdb %v0, %v0, %v0, 0 + vfmaxdb %v0, %v0, %v0, 4 + vfmaxdb %v0, %v0, %v31, 0 + vfmaxdb %v0, %v31, %v0, 0 + vfmaxdb %v31, %v0, %v0, 0 + vfmaxdb %v18, %v3, %v20, 12 + +#CHECK: vfmin %v0, %v0, %v0, 0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xee] +#CHECK: vfmin %v0, %v0, %v0, 15, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xee] +#CHECK: vfmin %v0, %v0, %v0, 0, 15, 0 # encoding: [0xe7,0x00,0x00,0x0f,0x00,0xee] +#CHECK: vfmin %v0, %v0, %v0, 0, 0, 4 # encoding: [0xe7,0x00,0x00,0x40,0x00,0xee] +#CHECK: vfmin %v0, %v0, %v31, 0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xee] +#CHECK: vfmin %v0, %v31, %v0, 0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xee] +#CHECK: vfmin %v31, %v0, %v0, 0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xee] +#CHECK: vfmin %v18, %v3, %v20, 11, 9, 12 # encoding: [0xe7,0x23,0x40,0xc9,0xba,0xee] + + vfmin %v0, %v0, %v0, 0, 0, 0 + vfmin %v0, %v0, %v0, 15, 0, 0 + vfmin %v0, %v0, %v0, 0, 15, 0 + vfmin %v0, %v0, %v0, 0, 0, 4 + vfmin %v0, %v0, %v31, 0, 0, 0 + vfmin %v0, %v31, %v0, 0, 0, 0 + vfmin %v31, %v0, %v0, 0, 0, 0 + vfmin %v18, %v3, %v20, 11, 9, 12 + +#CHECK: vfmindb %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0xee] +#CHECK: vfmindb %v0, %v0, %v0, 4 # encoding: [0xe7,0x00,0x00,0x40,0x30,0xee] +#CHECK: vfmindb %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x32,0xee] +#CHECK: vfmindb %v0, %v31, %v0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0xee] +#CHECK: vfmindb %v31, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0xee] +#CHECK: vfmindb %v18, %v3, %v20, 12 # encoding: [0xe7,0x23,0x40,0xc0,0x3a,0xee] + + vfmindb %v0, %v0, %v0, 0 + vfmindb %v0, %v0, %v0, 4 + vfmindb %v0, %v0, %v31, 0 + vfmindb %v0, %v31, %v0, 0 + vfmindb %v31, %v0, %v0, 0 + vfmindb %v18, %v3, %v20, 12 + +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x9f] +#CHECK: vfnma %v0, %v0, %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x0f,0x00,0x00,0x9f] +#CHECK: vfnma %v0, %v0, %v0, %v0, 15, 0 # encoding: [0xe7,0x00,0x00,0x0f,0x00,0x9f] +#CHECK: vfnma %v0, %v0, %v0, %v31, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x9f] +#CHECK: vfnma %v0, %v0, %v31, %v0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x9f] +#CHECK: vfnma %v0, %v31, %v0, %v0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x9f] +#CHECK: vfnma %v31, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x9f] +#CHECK: vfnma %v13, %v17, %v21, %v25, 9, 11 # encoding: [0xe7,0xd1,0x5b,0x09,0x97,0x9f] + + vfnma %v0, %v0, %v0, %v0, 0, 0 + vfnma %v0, %v0, %v0, %v0, 0, 15 + vfnma %v0, %v0, %v0, %v0, 15, 0 + vfnma %v0, %v0, %v0, %v31, 0, 0 + vfnma %v0, %v0, %v31, %v0, 0, 0 + vfnma %v0, %v31, %v0, %v0, 0, 0 + vfnma %v31, %v0, %v0, %v0, 0, 0 + vfnma %v13, %v17, %v21, %v25, 9, 11 + +#CHECK: vfnmadb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x03,0x00,0x00,0x9f] +#CHECK: vfnmadb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x03,0x00,0xf1,0x9f] +#CHECK: vfnmadb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf3,0x00,0x02,0x9f] +#CHECK: vfnmadb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x03,0x00,0x04,0x9f] +#CHECK: vfnmadb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x03,0x00,0x08,0x9f] +#CHECK: vfnmadb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x00,0x97,0x9f] + + vfnmadb %v0, %v0, %v0, %v0 + vfnmadb %v0, %v0, %v0, %v31 + vfnmadb %v0, %v0, %v31, %v0 + vfnmadb %v0, %v31, %v0, %v0 + vfnmadb %v31, %v0, %v0, %v0 + vfnmadb %v13, %v17, %v21, %v25 + +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x9e] +#CHECK: vfnms %v0, %v0, %v0, %v0, 0, 15 # encoding: [0xe7,0x00,0x0f,0x00,0x00,0x9e] +#CHECK: vfnms %v0, %v0, %v0, %v0, 15, 0 # encoding: [0xe7,0x00,0x00,0x0f,0x00,0x9e] +#CHECK: vfnms %v0, %v0, %v0, %v31, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0x9e] +#CHECK: vfnms %v0, %v0, %v31, %v0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x9e] +#CHECK: vfnms %v0, %v31, %v0, %v0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x9e] +#CHECK: vfnms %v31, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x9e] +#CHECK: vfnms %v13, %v17, %v21, %v25, 9, 11 # encoding: [0xe7,0xd1,0x5b,0x09,0x97,0x9e] + + vfnms %v0, %v0, %v0, %v0, 0, 0 + vfnms %v0, %v0, %v0, %v0, 0, 15 + vfnms %v0, %v0, %v0, %v0, 15, 0 + vfnms %v0, %v0, %v0, %v31, 0, 0 + vfnms %v0, %v0, %v31, %v0, 0, 0 + vfnms %v0, %v31, %v0, %v0, 0, 0 + vfnms %v31, %v0, %v0, %v0, 0, 0 + vfnms %v13, %v17, %v21, %v25, 9, 11 + +#CHECK: vfnmsdb %v0, %v0, %v0, %v0 # encoding: [0xe7,0x00,0x03,0x00,0x00,0x9e] +#CHECK: vfnmsdb %v0, %v0, %v0, %v31 # encoding: [0xe7,0x00,0x03,0x00,0xf1,0x9e] +#CHECK: vfnmsdb %v0, %v0, %v31, %v0 # encoding: [0xe7,0x00,0xf3,0x00,0x02,0x9e] +#CHECK: vfnmsdb %v0, %v31, %v0, %v0 # encoding: [0xe7,0x0f,0x03,0x00,0x04,0x9e] +#CHECK: vfnmsdb %v31, %v0, %v0, %v0 # encoding: [0xe7,0xf0,0x03,0x00,0x08,0x9e] +#CHECK: vfnmsdb %v13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x00,0x97,0x9e] + + vfnmsdb %v0, %v0, %v0, %v0 + vfnmsdb %v0, %v0, %v0, %v31 + vfnmsdb %v0, %v0, %v31, %v0 + vfnmsdb %v0, %v31, %v0, %v0 + vfnmsdb %v31, %v0, %v0, %v0 + vfnmsdb %v13, %v17, %v21, %v25 + +#CHECK: vlip %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x49] +#CHECK: vlip %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x49] +#CHECK: vlip %v0, 65535, 0 # encoding: [0xe6,0x00,0xff,0xff,0x00,0x49] +#CHECK: vlip %v15, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x00,0x49] +#CHECK: vlip %v31, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x49] +#CHECK: vlip %v17, 4660, 7 # encoding: [0xe6,0x10,0x12,0x34,0x78,0x49] + + vlip %v0, 0, 0 + vlip %v0, 0, 15 + vlip %v0, 0xffff, 0 + vlip %v15, 0, 0 + vlip %v31, 0, 0 + vlip %v17, 0x1234, 7 + +#CHECK: vllezlf %v0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x60,0x04] +#CHECK: vllezlf %v0, 4095 # encoding: [0xe7,0x00,0x0f,0xff,0x60,0x04] +#CHECK: vllezlf %v0, 0(%r15) # encoding: [0xe7,0x00,0xf0,0x00,0x60,0x04] +#CHECK: vllezlf %v0, 0(%r15,%r1) # encoding: [0xe7,0x0f,0x10,0x00,0x60,0x04] +#CHECK: vllezlf %v15, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x60,0x04] +#CHECK: vllezlf %v31, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x68,0x04] +#CHECK: vllezlf %v18, 1383(%r3,%r4) # encoding: [0xe7,0x23,0x45,0x67,0x68,0x04] + + vllezlf %v0, 0 + vllezlf %v0, 4095 + vllezlf %v0, 0(%r15) + vllezlf %v0, 0(%r15,%r1) + vllezlf %v15, 0 + vllezlf %v31, 0 + vllezlf %v18, 0x567(%r3,%r4) + +#CHECK: vlrl %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x35] +#CHECK: vlrl %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x35] +#CHECK: vlrl %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x35] +#CHECK: vlrl %v0, 0, 255 # encoding: [0xe6,0xff,0x00,0x00,0x00,0x35] +#CHECK: vlrl %v15, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x35] +#CHECK: vlrl %v31, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x35] +#CHECK: vlrl %v18, 1383(%r4), 3 # encoding: [0xe6,0x03,0x45,0x67,0x21,0x35] + + vlrl %v0, 0, 0 + vlrl %v0, 4095, 0 + vlrl %v0, 0(%r15), 0 + vlrl %v0, 0, 255 + vlrl %v15, 0, 0 + vlrl %v31, 0, 0 + vlrl %v18, 1383(%r4), 3 + +#CHECK: vlrlr %v0, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x37] +#CHECK: vlrlr %v0, %r0, 4095 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x37] +#CHECK: vlrlr %v0, %r0, 0(%r15) # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x37] +#CHECK: vlrlr %v0, %r15, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x37] +#CHECK: vlrlr %v15, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x37] +#CHECK: vlrlr %v31, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x37] +#CHECK: vlrlr %v18, %r3, 1383(%r4) # encoding: [0xe6,0x03,0x45,0x67,0x21,0x37] + + vlrlr %v0, %r0, 0 + vlrlr %v0, %r0, 4095 + vlrlr %v0, %r0, 0(%r15) + vlrlr %v0, %r15, 0 + vlrlr %v15, %r0, 0 + vlrlr %v31, %r0, 0 + vlrlr %v18, %r3, 1383(%r4) + +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0xb8] +#CHECK: vmsl %v0, %v0, %v0, %v0, 15, 0 # encoding: [0xe7,0x00,0x0f,0x00,0x00,0xb8] +#CHECK: vmsl %v0, %v0, %v0, %v0, 0, 12 # encoding: [0xe7,0x00,0x00,0xc0,0x00,0xb8] +#CHECK: vmsl %v0, %v0, %v0, %v15, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf0,0xb8] +#CHECK: vmsl %v0, %v0, %v0, %v31, 0, 0 # encoding: [0xe7,0x00,0x00,0x00,0xf1,0xb8] +#CHECK: vmsl %v0, %v0, %v15, %v0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x00,0xb8] +#CHECK: vmsl %v0, %v0, %v31, %v0, 0, 0 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0xb8] +#CHECK: vmsl %v0, %v15, %v0, %v0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0xb8] +#CHECK: vmsl %v0, %v31, %v0, %v0, 0, 0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0xb8] +#CHECK: vmsl %v15, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0xb8] +#CHECK: vmsl %v31, %v0, %v0, %v0, 0, 0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0xb8] +#CHECK: vmsl %v18, %v3, %v20, %v5, 0, 4 # encoding: [0xe7,0x23,0x40,0x40,0x5a,0xb8] +#CHECK: vmsl %v18, %v3, %v20, %v5, 11, 8 # encoding: [0xe7,0x23,0x4b,0x80,0x5a,0xb8] + + vmsl %v0, %v0, %v0, %v0, 0, 0 + vmsl %v0, %v0, %v0, %v0, 15, 0 + vmsl %v0, %v0, %v0, %v0, 0, 12 + vmsl %v0, %v0, %v0, %v15, 0, 0 + vmsl %v0, %v0, %v0, %v31, 0, 0 + vmsl %v0, %v0, %v15, %v0, 0, 0 + vmsl %v0, %v0, %v31, %v0, 0, 0 + vmsl %v0, %v15, %v0, %v0, 0, 0 + vmsl %v0, %v31, %v0, %v0, 0, 0 + vmsl %v15, %v0, %v0, %v0, 0, 0 + vmsl %v31, %v0, %v0, %v0, 0, 0 + vmsl %v18, %v3, %v20, %v5, 0, 4 + vmsl %v18, %v3, %v20, %v5, 11, 8 + +#CHECK: vmslg %v0, %v0, %v0, %v0, 0 # encoding: [0xe7,0x00,0x03,0x00,0x00,0xb8] +#CHECK: vmslg %v0, %v0, %v0, %v0, 12 # encoding: [0xe7,0x00,0x03,0xc0,0x00,0xb8] +#CHECK: vmslg %v0, %v0, %v0, %v15, 0 # encoding: [0xe7,0x00,0x03,0x00,0xf0,0xb8] +#CHECK: vmslg %v0, %v0, %v0, %v31, 0 # encoding: [0xe7,0x00,0x03,0x00,0xf1,0xb8] +#CHECK: vmslg %v0, %v0, %v15, %v0, 0 # encoding: [0xe7,0x00,0xf3,0x00,0x00,0xb8] +#CHECK: vmslg %v0, %v0, %v31, %v0, 0 # encoding: [0xe7,0x00,0xf3,0x00,0x02,0xb8] +#CHECK: vmslg %v0, %v15, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x03,0x00,0x00,0xb8] +#CHECK: vmslg %v0, %v31, %v0, %v0, 0 # encoding: [0xe7,0x0f,0x03,0x00,0x04,0xb8] +#CHECK: vmslg %v15, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x03,0x00,0x00,0xb8] +#CHECK: vmslg %v31, %v0, %v0, %v0, 0 # encoding: [0xe7,0xf0,0x03,0x00,0x08,0xb8] +#CHECK: vmslg %v18, %v3, %v20, %v5, 4 # encoding: [0xe7,0x23,0x43,0x40,0x5a,0xb8] +#CHECK: vmslg %v18, %v3, %v20, %v5, 8 # encoding: [0xe7,0x23,0x43,0x80,0x5a,0xb8] + + vmslg %v0, %v0, %v0, %v0, 0 + vmslg %v0, %v0, %v0, %v0, 12 + vmslg %v0, %v0, %v0, %v15, 0 + vmslg %v0, %v0, %v0, %v31, 0 + vmslg %v0, %v0, %v15, %v0, 0 + vmslg %v0, %v0, %v31, %v0, 0 + vmslg %v0, %v15, %v0, %v0, 0 + vmslg %v0, %v31, %v0, %v0, 0 + vmslg %v15, %v0, %v0, %v0, 0 + vmslg %v31, %v0, %v0, %v0, 0 + vmslg %v18, %v3, %v20, %v5, 4 + vmslg %v18, %v3, %v20, %v5, 8 + +#CHECK: vmp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x78] +#CHECK: vmp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x78] +#CHECK: vmp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x78] +#CHECK: vmp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x78] +#CHECK: vmp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x78] +#CHECK: vmp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x78] +#CHECK: vmp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x78] + + vmp %v0, %v0, %v0, 0, 0 + vmp %v0, %v0, %v0, 0, 15 + vmp %v0, %v0, %v0, 255, 0 + vmp %v0, %v0, %v31, 0, 0 + vmp %v0, %v31, %v0, 0, 0 + vmp %v31, %v0, %v0, 0, 0 + vmp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vmsp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x79] +#CHECK: vmsp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x79] +#CHECK: vmsp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x79] +#CHECK: vmsp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x79] +#CHECK: vmsp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x79] +#CHECK: vmsp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x79] +#CHECK: vmsp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x79] + + vmsp %v0, %v0, %v0, 0, 0 + vmsp %v0, %v0, %v0, 0, 15 + vmsp %v0, %v0, %v0, 255, 0 + vmsp %v0, %v0, %v31, 0, 0 + vmsp %v0, %v31, %v0, 0, 0 + vmsp %v31, %v0, %v0, 0, 0 + vmsp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vnn %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6e] +#CHECK: vnn %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6e] +#CHECK: vnn %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6e] +#CHECK: vnn %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6e] +#CHECK: vnn %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6e] + + vnn %v0, %v0, %v0 + vnn %v0, %v0, %v31 + vnn %v0, %v31, %v0 + vnn %v31, %v0, %v0 + vnn %v18, %v3, %v20 + +#CHECK: vnx %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6c] +#CHECK: vnx %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6c] +#CHECK: vnx %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6c] +#CHECK: vnx %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6c] +#CHECK: vnx %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6c] + + vnx %v0, %v0, %v0 + vnx %v0, %v0, %v31 + vnx %v0, %v31, %v0 + vnx %v31, %v0, %v0 + vnx %v18, %v3, %v20 + +#CHECK: voc %v0, %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x6f] +#CHECK: voc %v0, %v0, %v31 # encoding: [0xe7,0x00,0xf0,0x00,0x02,0x6f] +#CHECK: voc %v0, %v31, %v0 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x6f] +#CHECK: voc %v31, %v0, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x6f] +#CHECK: voc %v18, %v3, %v20 # encoding: [0xe7,0x23,0x40,0x00,0x0a,0x6f] + + voc %v0, %v0, %v0 + voc %v0, %v0, %v31 + voc %v0, %v31, %v0 + voc %v31, %v0, %v0 + voc %v18, %v3, %v20 + +#CHECK: vpkz %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x34] +#CHECK: vpkz %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x34] +#CHECK: vpkz %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x34] +#CHECK: vpkz %v0, 0, 255 # encoding: [0xe6,0xff,0x00,0x00,0x00,0x34] +#CHECK: vpkz %v15, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x34] +#CHECK: vpkz %v31, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x34] +#CHECK: vpkz %v18, 1383(%r4), 3 # encoding: [0xe6,0x03,0x45,0x67,0x21,0x34] + + vpkz %v0, 0, 0 + vpkz %v0, 4095, 0 + vpkz %v0, 0(%r15), 0 + vpkz %v0, 0, 255 + vpkz %v15, 0, 0 + vpkz %v31, 0, 0 + vpkz %v18, 1383(%r4), 3 + +#CHECK: vpopctb %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x00,0x50] +#CHECK: vpopctb %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x00,0x50] +#CHECK: vpopctb %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x04,0x50] +#CHECK: vpopctb %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x00,0x50] +#CHECK: vpopctb %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x08,0x50] +#CHECK: vpopctb %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x04,0x50] + + vpopctb %v0, %v0 + vpopctb %v0, %v15 + vpopctb %v0, %v31 + vpopctb %v15, %v0 + vpopctb %v31, %v0 + vpopctb %v14, %v17 + +#CHECK: vpopctf %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x20,0x50] +#CHECK: vpopctf %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x20,0x50] +#CHECK: vpopctf %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x24,0x50] +#CHECK: vpopctf %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x20,0x50] +#CHECK: vpopctf %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x28,0x50] +#CHECK: vpopctf %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x24,0x50] + + vpopctf %v0, %v0 + vpopctf %v0, %v15 + vpopctf %v0, %v31 + vpopctf %v15, %v0 + vpopctf %v31, %v0 + vpopctf %v14, %v17 + +#CHECK: vpopctg %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x30,0x50] +#CHECK: vpopctg %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x30,0x50] +#CHECK: vpopctg %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x34,0x50] +#CHECK: vpopctg %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x30,0x50] +#CHECK: vpopctg %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x38,0x50] +#CHECK: vpopctg %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x34,0x50] + + vpopctg %v0, %v0 + vpopctg %v0, %v15 + vpopctg %v0, %v31 + vpopctg %v15, %v0 + vpopctg %v31, %v0 + vpopctg %v14, %v17 + +#CHECK: vpopcth %v0, %v0 # encoding: [0xe7,0x00,0x00,0x00,0x10,0x50] +#CHECK: vpopcth %v0, %v15 # encoding: [0xe7,0x0f,0x00,0x00,0x10,0x50] +#CHECK: vpopcth %v0, %v31 # encoding: [0xe7,0x0f,0x00,0x00,0x14,0x50] +#CHECK: vpopcth %v15, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x10,0x50] +#CHECK: vpopcth %v31, %v0 # encoding: [0xe7,0xf0,0x00,0x00,0x18,0x50] +#CHECK: vpopcth %v14, %v17 # encoding: [0xe7,0xe1,0x00,0x00,0x14,0x50] + + vpopcth %v0, %v0 + vpopcth %v0, %v15 + vpopcth %v0, %v31 + vpopcth %v15, %v0 + vpopcth %v31, %v0 + vpopcth %v14, %v17 + +#CHECK: vpsop %v0, %v0, 0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x5b] +#CHECK: vpsop %v0, %v0, 0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x5b] +#CHECK: vpsop %v0, %v0, 0, 255, 0 # encoding: [0xe6,0x00,0xff,0x00,0x00,0x5b] +#CHECK: vpsop %v0, %v0, 255, 0, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x5b] +#CHECK: vpsop %v0, %v31, 0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x5b] +#CHECK: vpsop %v31, %v0, 0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x5b] +#CHECK: vpsop %v13, %v17, 52, 121, 11 # encoding: [0xe6,0xd1,0x79,0xb3,0x44,0x5b] + + vpsop %v0, %v0, 0, 0, 0 + vpsop %v0, %v0, 0, 0, 15 + vpsop %v0, %v0, 0, 255, 0 + vpsop %v0, %v0, 255, 0, 0 + vpsop %v0, %v31, 0, 0, 0 + vpsop %v31, %v0, 0, 0, 0 + vpsop %v13, %v17, 0x34, 0x79, 11 + +#CHECK: vrp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x7b] +#CHECK: vrp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x7b] +#CHECK: vrp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x7b] +#CHECK: vrp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x7b] +#CHECK: vrp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x7b] +#CHECK: vrp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x7b] +#CHECK: vrp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x7b] + + vrp %v0, %v0, %v0, 0, 0 + vrp %v0, %v0, %v0, 0, 15 + vrp %v0, %v0, %v0, 255, 0 + vrp %v0, %v0, %v31, 0, 0 + vrp %v0, %v31, %v0, 0, 0 + vrp %v31, %v0, %v0, 0, 0 + vrp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vsdp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x7e] +#CHECK: vsdp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x7e] +#CHECK: vsdp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x7e] +#CHECK: vsdp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x7e] +#CHECK: vsdp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x7e] +#CHECK: vsdp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x7e] +#CHECK: vsdp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x7e] + + vsdp %v0, %v0, %v0, 0, 0 + vsdp %v0, %v0, %v0, 0, 15 + vsdp %v0, %v0, %v0, 255, 0 + vsdp %v0, %v0, %v31, 0, 0 + vsdp %v0, %v31, %v0, 0, 0 + vsdp %v31, %v0, %v0, 0, 0 + vsdp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vsp %v0, %v0, %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x73] +#CHECK: vsp %v0, %v0, %v0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x73] +#CHECK: vsp %v0, %v0, %v0, 255, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x73] +#CHECK: vsp %v0, %v0, %v31, 0, 0 # encoding: [0xe6,0x00,0xf0,0x00,0x02,0x73] +#CHECK: vsp %v0, %v31, %v0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x73] +#CHECK: vsp %v31, %v0, %v0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x73] +#CHECK: vsp %v13, %v17, %v21, 121, 11 # encoding: [0xe6,0xd1,0x50,0xb7,0x96,0x73] + + vsp %v0, %v0, %v0, 0, 0 + vsp %v0, %v0, %v0, 0, 15 + vsp %v0, %v0, %v0, 255, 0 + vsp %v0, %v0, %v31, 0, 0 + vsp %v0, %v31, %v0, 0, 0 + vsp %v31, %v0, %v0, 0, 0 + vsp %v13, %v17, %v21, 0x79, 11 + +#CHECK: vsrp %v0, %v0, 0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x59] +#CHECK: vsrp %v0, %v0, 0, 0, 15 # encoding: [0xe6,0x00,0x00,0xf0,0x00,0x59] +#CHECK: vsrp %v0, %v0, 0, 255, 0 # encoding: [0xe6,0x00,0xff,0x00,0x00,0x59] +#CHECK: vsrp %v0, %v0, 255, 0, 0 # encoding: [0xe6,0x00,0x00,0x0f,0xf0,0x59] +#CHECK: vsrp %v0, %v31, 0, 0, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x59] +#CHECK: vsrp %v31, %v0, 0, 0, 0 # encoding: [0xe6,0xf0,0x00,0x00,0x08,0x59] +#CHECK: vsrp %v13, %v17, 52, 121, 11 # encoding: [0xe6,0xd1,0x79,0xb3,0x44,0x59] + + vsrp %v0, %v0, 0, 0, 0 + vsrp %v0, %v0, 0, 0, 15 + vsrp %v0, %v0, 0, 255, 0 + vsrp %v0, %v0, 255, 0, 0 + vsrp %v0, %v31, 0, 0, 0 + vsrp %v31, %v0, 0, 0, 0 + vsrp %v13, %v17, 0x34, 0x79, 11 + +#CHECK: vstrl %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x3d] +#CHECK: vstrl %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x3d] +#CHECK: vstrl %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x3d] +#CHECK: vstrl %v0, 0, 255 # encoding: [0xe6,0xff,0x00,0x00,0x00,0x3d] +#CHECK: vstrl %v15, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x3d] +#CHECK: vstrl %v31, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x3d] +#CHECK: vstrl %v18, 1383(%r4), 3 # encoding: [0xe6,0x03,0x45,0x67,0x21,0x3d] + + vstrl %v0, 0, 0 + vstrl %v0, 4095, 0 + vstrl %v0, 0(%r15), 0 + vstrl %v0, 0, 255 + vstrl %v15, 0, 0 + vstrl %v31, 0, 0 + vstrl %v18, 1383(%r4), 3 + +#CHECK: vstrlr %v0, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x3f] +#CHECK: vstrlr %v0, %r0, 4095 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x3f] +#CHECK: vstrlr %v0, %r0, 0(%r15) # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x3f] +#CHECK: vstrlr %v0, %r15, 0 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x3f] +#CHECK: vstrlr %v15, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x3f] +#CHECK: vstrlr %v31, %r0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x3f] +#CHECK: vstrlr %v18, %r3, 1383(%r4) # encoding: [0xe6,0x03,0x45,0x67,0x21,0x3f] + + vstrlr %v0, %r0, 0 + vstrlr %v0, %r0, 4095 + vstrlr %v0, %r0, 0(%r15) + vstrlr %v0, %r15, 0 + vstrlr %v15, %r0, 0 + vstrlr %v31, %r0, 0 + vstrlr %v18, %r3, 1383(%r4) + +#CHECK: vtp %v0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x5f] +#CHECK: vtp %v15 # encoding: [0xe6,0x0f,0x00,0x00,0x00,0x5f] +#CHECK: vtp %v31 # encoding: [0xe6,0x0f,0x00,0x00,0x04,0x5f] + + vtp %v0 + vtp %v15 + vtp %v31 + +#CHECK: vupkz %v0, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0x00,0x3c] +#CHECK: vupkz %v0, 4095, 0 # encoding: [0xe6,0x00,0x0f,0xff,0x00,0x3c] +#CHECK: vupkz %v0, 0(%r15), 0 # encoding: [0xe6,0x00,0xf0,0x00,0x00,0x3c] +#CHECK: vupkz %v0, 0, 255 # encoding: [0xe6,0xff,0x00,0x00,0x00,0x3c] +#CHECK: vupkz %v15, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf0,0x3c] +#CHECK: vupkz %v31, 0, 0 # encoding: [0xe6,0x00,0x00,0x00,0xf1,0x3c] +#CHECK: vupkz %v18, 1383(%r4), 3 # encoding: [0xe6,0x03,0x45,0x67,0x21,0x3c] + + vupkz %v0, 0, 0 + vupkz %v0, 4095, 0 + vupkz %v0, 0(%r15), 0 + vupkz %v0, 0, 255 + vupkz %v15, 0, 0 + vupkz %v31, 0, 0 + vupkz %v18, 1383(%r4), 3 + +#CHECK: wfkedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xe8] +#CHECK: wfkedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xe8] +#CHECK: wfkedb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x0c,0x32,0xe8] +#CHECK: wfkedb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x0c,0x34,0xe8] +#CHECK: wfkedb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x0c,0x38,0xe8] +#CHECK: wfkedb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x0c,0x3a,0xe8] + + wfkedb %v0, %v0, %v0 + wfkedb %f0, %f0, %f0 + wfkedb %v0, %v0, %v31 + wfkedb %v0, %v31, %v0 + wfkedb %v31, %v0, %v0 + wfkedb %v18, %v3, %v20 + +#CHECK: wfkedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xe8] +#CHECK: wfkedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xe8] +#CHECK: wfkedbs %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x1c,0x32,0xe8] +#CHECK: wfkedbs %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x1c,0x34,0xe8] +#CHECK: wfkedbs %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x1c,0x38,0xe8] +#CHECK: wfkedbs %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x1c,0x3a,0xe8] + + wfkedbs %v0, %v0, %v0 + wfkedbs %f0, %f0, %f0 + wfkedbs %v0, %v0, %v31 + wfkedbs %v0, %v31, %v0 + wfkedbs %v31, %v0, %v0 + wfkedbs %v18, %v3, %v20 + +#CHECK: wfkhdb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xeb] +#CHECK: wfkhdb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xeb] +#CHECK: wfkhdb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x0c,0x32,0xeb] +#CHECK: wfkhdb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x0c,0x34,0xeb] +#CHECK: wfkhdb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x0c,0x38,0xeb] +#CHECK: wfkhdb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x0c,0x3a,0xeb] + + wfkhdb %v0, %v0, %v0 + wfkhdb %f0, %f0, %f0 + wfkhdb %v0, %v0, %v31 + wfkhdb %v0, %v31, %v0 + wfkhdb %v31, %v0, %v0 + wfkhdb %v18, %v3, %v20 + +#CHECK: wfkhdbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xeb] +#CHECK: wfkhdbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xeb] +#CHECK: wfkhdbs %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x1c,0x32,0xeb] +#CHECK: wfkhdbs %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x1c,0x34,0xeb] +#CHECK: wfkhdbs %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x1c,0x38,0xeb] +#CHECK: wfkhdbs %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x1c,0x3a,0xeb] + + wfkhdbs %v0, %v0, %v0 + wfkhdbs %f0, %f0, %f0 + wfkhdbs %v0, %v0, %v31 + wfkhdbs %v0, %v31, %v0 + wfkhdbs %v31, %v0, %v0 + wfkhdbs %v18, %v3, %v20 + +#CHECK: wfkhedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xea] +#CHECK: wfkhedb %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x0c,0x30,0xea] +#CHECK: wfkhedb %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x0c,0x32,0xea] +#CHECK: wfkhedb %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x0c,0x34,0xea] +#CHECK: wfkhedb %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x0c,0x38,0xea] +#CHECK: wfkhedb %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x0c,0x3a,0xea] + + wfkhedb %v0, %v0, %v0 + wfkhedb %f0, %f0, %f0 + wfkhedb %v0, %v0, %v31 + wfkhedb %v0, %v31, %v0 + wfkhedb %v31, %v0, %v0 + wfkhedb %v18, %v3, %v20 + +#CHECK: wfkhedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xea] +#CHECK: wfkhedbs %f0, %f0, %f0 # encoding: [0xe7,0x00,0x00,0x1c,0x30,0xea] +#CHECK: wfkhedbs %f0, %f0, %v31 # encoding: [0xe7,0x00,0xf0,0x1c,0x32,0xea] +#CHECK: wfkhedbs %f0, %v31, %f0 # encoding: [0xe7,0x0f,0x00,0x1c,0x34,0xea] +#CHECK: wfkhedbs %v31, %f0, %f0 # encoding: [0xe7,0xf0,0x00,0x1c,0x38,0xea] +#CHECK: wfkhedbs %v18, %f3, %v20 # encoding: [0xe7,0x23,0x40,0x1c,0x3a,0xea] + + wfkhedbs %v0, %v0, %v0 + wfkhedbs %f0, %f0, %f0 + wfkhedbs %v0, %v0, %v31 + wfkhedbs %v0, %v31, %v0 + wfkhedbs %v31, %v0, %v0 + wfkhedbs %v18, %v3, %v20 + +#CHECK: wfmaxdb %f0, %f0, %f0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xef] +#CHECK: wfmaxdb %f0, %f0, %f0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xef] +#CHECK: wfmaxdb %f0, %f0, %f0, 4 # encoding: [0xe7,0x00,0x00,0x48,0x30,0xef] +#CHECK: wfmaxdb %f0, %f0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xef] +#CHECK: wfmaxdb %f0, %v31, %f0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xef] +#CHECK: wfmaxdb %v31, %f0, %f0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xef] +#CHECK: wfmaxdb %v18, %f3, %v20, 11 # encoding: [0xe7,0x23,0x40,0xb8,0x3a,0xef] + + wfmaxdb %v0, %v0, %v0, 0 + wfmaxdb %f0, %f0, %f0, 0 + wfmaxdb %v0, %v0, %v0, 4 + wfmaxdb %v0, %v0, %v31, 0 + wfmaxdb %v0, %v31, %v0, 0 + wfmaxdb %v31, %v0, %v0, 0 + wfmaxdb %v18, %v3, %v20, 11 + +#CHECK: wfmindb %f0, %f0, %f0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xee] +#CHECK: wfmindb %f0, %f0, %f0, 0 # encoding: [0xe7,0x00,0x00,0x08,0x30,0xee] +#CHECK: wfmindb %f0, %f0, %f0, 4 # encoding: [0xe7,0x00,0x00,0x48,0x30,0xee] +#CHECK: wfmindb %f0, %f0, %v31, 0 # encoding: [0xe7,0x00,0xf0,0x08,0x32,0xee] +#CHECK: wfmindb %f0, %v31, %f0, 0 # encoding: [0xe7,0x0f,0x00,0x08,0x34,0xee] +#CHECK: wfmindb %v31, %f0, %f0, 0 # encoding: [0xe7,0xf0,0x00,0x08,0x38,0xee] +#CHECK: wfmindb %v18, %f3, %v20, 11 # encoding: [0xe7,0x23,0x40,0xb8,0x3a,0xee] + + wfmindb %v0, %v0, %v0, 0 + wfmindb %f0, %f0, %f0, 0 + wfmindb %v0, %v0, %v0, 4 + wfmindb %v0, %v0, %v31, 0 + wfmindb %v0, %v31, %v0, 0 + wfmindb %v31, %v0, %v0, 0 + wfmindb %v18, %v3, %v20, 11 + +#CHECK: wfnmadb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x9f] +#CHECK: wfnmadb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x9f] +#CHECK: wfnmadb %f0, %f0, %f0, %v31 # encoding: [0xe7,0x00,0x03,0x08,0xf1,0x9f] +#CHECK: wfnmadb %f0, %f0, %v31, %f0 # encoding: [0xe7,0x00,0xf3,0x08,0x02,0x9f] +#CHECK: wfnmadb %f0, %v31, %f0, %f0 # encoding: [0xe7,0x0f,0x03,0x08,0x04,0x9f] +#CHECK: wfnmadb %v31, %f0, %f0, %f0 # encoding: [0xe7,0xf0,0x03,0x08,0x08,0x9f] +#CHECK: wfnmadb %f13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x08,0x97,0x9f] + + wfnmadb %v0, %v0, %v0, %v0 + wfnmadb %f0, %f0, %f0, %f0 + wfnmadb %v0, %v0, %v0, %v31 + wfnmadb %v0, %v0, %v31, %v0 + wfnmadb %v0, %v31, %v0, %v0 + wfnmadb %v31, %v0, %v0, %v0 + wfnmadb %v13, %v17, %v21, %v25 + +#CHECK: wfnmsdb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x9e] +#CHECK: wfnmsdb %f0, %f0, %f0, %f0 # encoding: [0xe7,0x00,0x03,0x08,0x00,0x9e] +#CHECK: wfnmsdb %f0, %f0, %f0, %v31 # encoding: [0xe7,0x00,0x03,0x08,0xf1,0x9e] +#CHECK: wfnmsdb %f0, %f0, %v31, %f0 # encoding: [0xe7,0x00,0xf3,0x08,0x02,0x9e] +#CHECK: wfnmsdb %f0, %v31, %f0, %f0 # encoding: [0xe7,0x0f,0x03,0x08,0x04,0x9e] +#CHECK: wfnmsdb %v31, %f0, %f0, %f0 # encoding: [0xe7,0xf0,0x03,0x08,0x08,0x9e] +#CHECK: wfnmsdb %f13, %v17, %v21, %v25 # encoding: [0xe7,0xd1,0x53,0x08,0x97,0x9e] + + wfnmsdb %v0, %v0, %v0, %v0 + wfnmsdb %f0, %f0, %f0, %f0 + wfnmsdb %v0, %v0, %v0, %v31 + wfnmsdb %v0, %v0, %v31, %v0 + wfnmsdb %v0, %v31, %v0, %v0 + wfnmsdb %v31, %v0, %v0, %v0 + wfnmsdb %v13, %v17, %v21, %v25 +