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[MC][SVE] Fix data operand for instruction alias of st1d.

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The version of `st1d` that operates with vector plus immediate
addressing mode uses the alias `st1d { <Zn>.d }, <Pg>, [<Za>.d]` for
rendering `st1d { <Zn>.d }, <Pg>, [<Za>.d, #0]`. The disassembler was
generating `<Zn>.s` instead of `<Zn>.d>`.

Differential Revision: https://reviews.llvm.org/D86633
This commit is contained in:
Francesco Petrogalli 2020-08-26 15:43:56 +00:00
parent a48e0377f5
commit 5f5352f7e7
5 changed files with 85 additions and 1 deletions
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2
lib/Target/AArch64/SVEInstrFormats.td
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@ -5416,7 +5416,7 @@ multiclass sve_mem_64b_sst_vi_ptrs<bits<3> opc, string asm,
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn, $imm5]",
(!cast<Instruction>(NAME # _IMM) ZPR64:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, imm_ty:$imm5), 0>;
def : InstAlias<asm # "\t$Zt, $Pg, [$Zn]",
(!cast<Instruction>(NAME # _IMM) Z_s:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
(!cast<Instruction>(NAME # _IMM) Z_d:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, 0), 1>;
def : Pat<(op (nxv2i64 ZPR:$data), (nxv2i1 PPR:$gp), (nxv2i64 ZPR:$ptrs), imm_ty:$index, vt),
(!cast<Instruction>(NAME # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, imm_ty:$index)>;

24
test/MC/AArch64/SVE/st1b.s
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@ -168,3 +168,27 @@ st1b { z31.d }, p7, [z31.d, #31]
// CHECK-ENCODING: [0xff,0xbf,0x5f,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 5f e4 <unknown>
st1b { z0.s }, p7, [z0.s, #0]
// CHECK-INST: st1b { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 60 e4 <unknown>
st1b { z0.s }, p7, [z0.s]
// CHECK-INST: st1b { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0x60,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 60 e4 <unknown>
st1b { z0.d }, p7, [z0.d, #0]
// CHECK-INST: st1b { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 40 e4 <unknown>
st1b { z0.d }, p7, [z0.d]
// CHECK-INST: st1b { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0x40,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 40 e4 <unknown>

12
test/MC/AArch64/SVE/st1d.s
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@ -78,3 +78,15 @@ st1d { z31.d }, p7, [z31.d, #248]
// CHECK-ENCODING: [0xff,0xbf,0xdf,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf df e5 <unknown>
st1d { z0.d }, p7, [z0.d, #0]
// CHECK-INST: st1d { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc c0 e5 <unknown>
st1d { z0.d }, p7, [z0.d]
// CHECK-INST: st1d { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc c0 e5 <unknown>

24
test/MC/AArch64/SVE/st1h.s
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@ -168,3 +168,27 @@ st1h { z31.d }, p7, [z31.d, #62]
// CHECK-ENCODING: [0xff,0xbf,0xdf,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf df e4 <unknown>
st1h { z0.s }, p7, [z0.s, #0]
// CHECK-INST: st1h { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc e0 e4 <unknown>
st1h { z0.s }, p7, [z0.s]
// CHECK-INST: st1h { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0xe0,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc e0 e4 <unknown>
st1h { z0.d }, p7, [z0.d, #0]
// CHECK-INST: st1h { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc c0 e4 <unknown>
st1h { z0.d }, p7, [z0.d]
// CHECK-INST: st1h { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0xc0,0xe4]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc c0 e4 <unknown>

24
test/MC/AArch64/SVE/st1w.s
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@ -138,3 +138,27 @@ st1w { z31.d }, p7, [z31.d, #124]
// CHECK-ENCODING: [0xff,0xbf,0x5f,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: ff bf 5f e5 <unknown>
st1w { z0.s }, p7, [z0.s, #0]
// CHECK-INST: st1w { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0x60,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 60 e5 <unknown>
st1w { z0.s }, p7, [z0.s]
// CHECK-INST: st1w { z0.s }, p7, [z0.s]
// CHECK-ENCODING: [0x00,0xbc,0x60,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 60 e5 <unknown>
st1w { z0.d }, p7, [z0.d, #0]
// CHECK-INST: st1w { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0x40,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 40 e5 <unknown>
st1w { z0.d }, p7, [z0.d]
// CHECK-INST: st1w { z0.d }, p7, [z0.d]
// CHECK-ENCODING: [0x00,0xbc,0x40,0xe5]
// CHECK-ERROR: instruction requires: sve
// CHECK-UNKNOWN: 00 bc 40 e5 <unknown>