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[RISCV] Update RVV ISA section-header comments. NFC.

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Some of the section headers had become stale with the transition from
RVV specification version 0.9 to 0.10. This patch brings them up to
date.
This commit is contained in:
Fraser Cormack 2021-02-25 14:07:58 +00:00
parent e8bbfa6ce1
commit 5fe445512d
3 changed files with 16 additions and 18 deletions
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8
lib/Target/RISCV/RISCVInstrInfoVPseudos.td
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@ -3375,12 +3375,12 @@ defm PseudoVWMACCSU : VPseudoTernaryW_VV_VX;
defm PseudoVWMACCUS : VPseudoTernaryW_VX; defm PseudoVWMACCUS : VPseudoTernaryW_VX;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.16. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVMERGE : VPseudoBinaryV_VM_XM_IM; defm PseudoVMERGE : VPseudoBinaryV_VM_XM_IM;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.17. Vector Integer Move Instructions // 12.16. Vector Integer Move Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm PseudoVMV_V : VPseudoUnaryV_V_X_I_NoDummyMask; defm PseudoVMV_V : VPseudoUnaryV_V_X_I_NoDummyMask;
@ -3966,12 +3966,12 @@ defm "" : VPatTernaryW_VV_VX<"int_riscv_vwmaccsu", "PseudoVWMACCSU", AllWidenabl
defm "" : VPatTernaryW_VX<"int_riscv_vwmaccus", "PseudoVWMACCUS", AllWidenableIntVectors>; defm "" : VPatTernaryW_VX<"int_riscv_vwmaccus", "PseudoVWMACCUS", AllWidenableIntVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.16. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm "" : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">; defm "" : VPatBinaryV_VM_XM_IM<"int_riscv_vmerge", "PseudoVMERGE">;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 12.17. Vector Integer Move Instructions // 12.16. Vector Integer Move Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
foreach vti = AllVectors in { foreach vti = AllVectors in {
def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$rs1), def : Pat<(vti.Vector (int_riscv_vmv_v_v (vti.Vector vti.RegClass:$rs1),

14
lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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@ -468,7 +468,7 @@ defm "" : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV">;
defm "" : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">; defm "" : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU">;
defm "" : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">; defm "" : VPatBinarySDNode_VV_VX<srem, "PseudoVREM">;
// 12.16. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), vti.RegClass:$rs1, def : Pat<(vti.Vector (vselect (vti.Mask VMV0:$vm), vti.RegClass:$rs1,
vti.RegClass:$rs2)), vti.RegClass:$rs2)),
@ -647,7 +647,7 @@ foreach vti = AllFloatVectors in {
vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.SEW)>; vti.RegClass:$rs1, vti.ScalarRegClass:$rs2, vti.AVL, vti.SEW)>;
} }
// 14.11. Vector Floating-Point Compare Instructions // 14.13. Vector Floating-Point Compare Instructions
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
@ -661,8 +661,8 @@ defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">;
defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; defm "" : VPatFPSetCCSDNode_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">;
// Floating-point vselects: // Floating-point vselects:
// 12.16. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
// 14.13. Vector Floating-Point Merge Instruction // 14.15. Vector Floating-Point Merge Instruction
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), fvti.RegClass:$rs1, def : Pat<(fvti.Vector (vselect (fvti.Mask VMV0:$vm), fvti.RegClass:$rs1,
fvti.RegClass:$rs2)), fvti.RegClass:$rs2)),
@ -685,13 +685,13 @@ foreach fvti = AllFloatVectors in {
fvti.RegClass:$rs2, 0, VMV0:$vm, fvti.AVL, fvti.SEW)>; fvti.RegClass:$rs2, 0, VMV0:$vm, fvti.AVL, fvti.SEW)>;
} }
// 14.15. Vector Single-Width Floating-Point/Integer Type-Convert Instructions // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
defm "" : VPatConvertFP2ISDNode_V<fp_to_sint, "PseudoVFCVT_RTZ_X_F_V">; defm "" : VPatConvertFP2ISDNode_V<fp_to_sint, "PseudoVFCVT_RTZ_X_F_V">;
defm "" : VPatConvertFP2ISDNode_V<fp_to_uint, "PseudoVFCVT_RTZ_XU_F_V">; defm "" : VPatConvertFP2ISDNode_V<fp_to_uint, "PseudoVFCVT_RTZ_XU_F_V">;
defm "" : VPatConvertI2FPSDNode_V<sint_to_fp, "PseudoVFCVT_F_X_V">; defm "" : VPatConvertI2FPSDNode_V<sint_to_fp, "PseudoVFCVT_F_X_V">;
defm "" : VPatConvertI2FPSDNode_V<uint_to_fp, "PseudoVFCVT_F_XU_V">; defm "" : VPatConvertI2FPSDNode_V<uint_to_fp, "PseudoVFCVT_F_XU_V">;
// 14.16. Widening Floating-Point/Integer Type-Convert Instructions // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
defm "" : VPatWConvertFP2ISDNode_V<fp_to_sint, "PseudoVFWCVT_RTZ_X_F_V">; defm "" : VPatWConvertFP2ISDNode_V<fp_to_sint, "PseudoVFWCVT_RTZ_X_F_V">;
defm "" : VPatWConvertFP2ISDNode_V<fp_to_uint, "PseudoVFWCVT_RTZ_XU_F_V">; defm "" : VPatWConvertFP2ISDNode_V<fp_to_uint, "PseudoVFWCVT_RTZ_XU_F_V">;
defm "" : VPatWConvertI2FPSDNode_V<sint_to_fp, "PseudoVFWCVT_F_X_V">; defm "" : VPatWConvertI2FPSDNode_V<sint_to_fp, "PseudoVFWCVT_F_X_V">;
@ -704,7 +704,7 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
fvti.RegClass:$rs1, fvti.AVL, fvti.SEW)>; fvti.RegClass:$rs1, fvti.AVL, fvti.SEW)>;
} }
// 14.17. Narrowing Floating-Point/Integer Type-Convert Instructions // 14.19. Narrowing Floating-Point/Integer Type-Convert Instructions
defm "" : VPatNConvertFP2ISDNode_V<fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">; defm "" : VPatNConvertFP2ISDNode_V<fp_to_sint, "PseudoVFNCVT_RTZ_X_F_W">;
defm "" : VPatNConvertFP2ISDNode_V<fp_to_uint, "PseudoVFNCVT_RTZ_XU_F_W">; defm "" : VPatNConvertFP2ISDNode_V<fp_to_uint, "PseudoVFNCVT_RTZ_XU_F_W">;
defm "" : VPatNConvertI2FPSDNode_V<sint_to_fp, "PseudoVFNCVT_F_X_W">; defm "" : VPatNConvertI2FPSDNode_V<sint_to_fp, "PseudoVFNCVT_F_X_W">;

12
lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
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@ -603,7 +603,7 @@ defm "" : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV">;
defm "" : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">; defm "" : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU">;
defm "" : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">; defm "" : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM">;
// 12.16. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask VMV0:$vm), def : Pat<(vti.Vector (riscv_vselect_vl (vti.Mask VMV0:$vm),
vti.RegClass:$rs1, vti.RegClass:$rs1,
@ -628,7 +628,7 @@ foreach vti = AllIntegerVectors in {
vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, GPR:$vl, vti.SEW)>; vti.RegClass:$rs2, simm5:$rs1, VMV0:$vm, GPR:$vl, vti.SEW)>;
} }
// 12.17. Vector Integer Move Instructions // 12.16. Vector Integer Move Instructions
foreach vti = AllIntegerVectors in { foreach vti = AllIntegerVectors in {
def : Pat<(vti.Vector (riscv_vmv_v_x_vl GPR:$rs2, (XLenVT (VLOp GPR:$vl)))), def : Pat<(vti.Vector (riscv_vmv_v_x_vl GPR:$rs2, (XLenVT (VLOp GPR:$vl)))),
(!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX) (!cast<Instruction>("PseudoVMV_V_X_"#vti.LMul.MX)
@ -762,7 +762,7 @@ foreach vti = AllFloatVectors in {
GPR:$vl, vti.SEW)>; GPR:$vl, vti.SEW)>;
} }
// 14.11. Vector Floating-Point Compare Instructions // 14.13. Vector Floating-Point Compare Instructions
defm "" : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">; defm "" : VPatFPSetCCVL_VV_VF_FV<SETEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
defm "" : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">; defm "" : VPatFPSetCCVL_VV_VF_FV<SETOEQ, "PseudoVMFEQ", "PseudoVMFEQ">;
@ -775,8 +775,6 @@ defm "" : VPatFPSetCCVL_VV_VF_FV<SETOLT, "PseudoVMFLT", "PseudoVMFGT">;
defm "" : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">; defm "" : VPatFPSetCCVL_VV_VF_FV<SETLE, "PseudoVMFLE", "PseudoVMFGE">;
defm "" : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">; defm "" : VPatFPSetCCVL_VV_VF_FV<SETOLE, "PseudoVMFLE", "PseudoVMFGE">;
// 14.12. Vector Floating-Point Sign-Injection Instructions
// Handle fneg with VFSGNJN using the same input for both operands.
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
// 14.8. Vector Floating-Point Square-Root Instruction // 14.8. Vector Floating-Point Square-Root Instruction
def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask), def : Pat<(riscv_fsqrt_vl (vti.Vector vti.RegClass:$rs2), (vti.Mask true_mask),
@ -798,8 +796,8 @@ foreach vti = AllFloatVectors in {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
// Floating-point vselects: // Floating-point vselects:
// 12.16. Vector Integer Merge Instructions // 12.15. Vector Integer Merge Instructions
// 14.13. Vector Floating-Point Merge Instruction // 14.15. Vector Floating-Point Merge Instruction
def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask VMV0:$vm), def : Pat<(fvti.Vector (riscv_vselect_vl (fvti.Mask VMV0:$vm),
fvti.RegClass:$rs1, fvti.RegClass:$rs1,
fvti.RegClass:$rs2, fvti.RegClass:$rs2,