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Also CSE non-pic load from constant pools.
llvm-svn: 89440
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1c98078e57
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@ -978,7 +978,10 @@ bool ARMBaseInstrInfo::isIdentical(const MachineInstr *MI0,
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const MachineInstr *MI1,
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const MachineRegisterInfo *MRI) const {
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int Opcode = MI0->getOpcode();
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if (Opcode == ARM::t2LDRpci_pic || Opcode == ARM::tLDRpci_pic) {
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if (Opcode == ARM::t2LDRpci ||
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Opcode == ARM::t2LDRpci_pic ||
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Opcode == ARM::tLDRpci ||
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Opcode == ARM::tLDRpci_pic) {
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if (MI1->getOpcode() != Opcode)
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return false;
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if (MI0->getNumOperands() != MI1->getNumOperands())
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@ -1,4 +1,5 @@
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -disable-fp-elim | FileCheck %s
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; RUN: llc < %s -mtriple=thumbv7-apple-darwin -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC
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; rdar://7353541
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; rdar://7354376
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@ -17,12 +18,20 @@ entry:
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bb.nph: ; preds = %entry
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; CHECK: BB#1
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; CHECK: ldr.n r2, LCPI1_0
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; CHECK: add r2, pc
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; CHECK: ldr r{{[0-9]+}}, [r2]
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; CHECK: LBB1_2
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; CHECK: LCPI1_0:
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; CHECK-NOT: LCPI1_1:
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; CHECK: .section
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; PIC: BB#1
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; PIC: ldr.n r2, LCPI1_0
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; PIC: add r2, pc
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; PIC: ldr r{{[0-9]+}}, [r2]
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; PIC: LBB1_2
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; PIC: LCPI1_0:
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; PIC-NOT: LCPI1_1:
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; PIC: .section
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%.pre = load i32* @GV, align 4 ; <i32> [#uses=1]
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br label %bb
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