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[AArch64][GlobalISel] Refactor + improve CMN, ADDS, and ADD emit functions
These functions were extremely similar: - `emitADD` - `emitADDS` - `emitCMN` Refactor them a little, introducing a more generic `emitInstr` function to do most of the work. Also add support for the immediate + shifted register addressing modes in each of them. Update select-uaddo.mir to show that selecing ADDS now supports folding immediates + shifts. (I don't think this can impact CMN, because the CMN checks require a G_SUB with a non-constant on the RHS.) This is around a 0.02% code size improvement on CTMark at -O3. Differential Revision: https://reviews.llvm.org/D87529
This commit is contained in:
Jessica Paquette
parent
d8616d8c76
commit
5ffe1901d5
@ -171,8 +171,57 @@ private:
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emitIntegerCompare(MachineOperand &LHS, MachineOperand &RHS,
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MachineOperand &Predicate,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitADD(Register DefReg, MachineOperand &LHS, MachineOperand &RHS,
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MachineInstr *emitInstr(unsigned Opcode,
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std::initializer_list<llvm::DstOp> DstOps,
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std::initializer_list<llvm::SrcOp> SrcOps,
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MachineIRBuilder &MIRBuilder,
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const ComplexRendererFns &RenderFns = None) const;
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/// Helper function to emit a binary operation such as an ADD, ADDS, etc.
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///
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/// This is intended for instructions with the following opcode variants:
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///
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/// - Xri, Wri (arithmetic immediate form)
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/// - Xrs, Wrs (shifted register form)
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/// - Xrr, Wrr (register form)
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///
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/// For example, for ADD, we have ADDXri, ADDWri, ADDXrs, etc.
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///
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/// \p AddrModeAndSizeToOpcode must contain each of the opcode variants above
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/// in a specific order.
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///
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/// Below is an example of the expected input to \p AddrModeAndSizeToOpcode.
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///
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/// \code
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/// const std::array<std::array<unsigned, 2>, 3> Table {
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/// {{AArch64::ADDXri, AArch64::ADDWri},
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/// {AArch64::ADDXrs, AArch64::ADDWrs},
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/// {AArch64::ADDXrr, AArch64::ADDWrr}}};
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/// \endcode
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///
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/// Each row in the table corresponds to a different addressing mode. Each
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/// column corresponds to a different register size.
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///
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/// \attention Rows must be structured as follows:
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/// - Row 0: The ri opcode variants
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/// - Row 1: The rs opcode variants
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/// - Row 2: The rr opcode variants
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///
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/// \attention Columns must be structured as follows:
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/// - Column 0: The 64-bit opcode variants
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/// - Column 1: The 32-bit opcode variants
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///
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/// \p Dst is the destination register of the binop to emit.
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/// \p LHS is the left-hand operand of the binop to emit.
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/// \p RHS is the right-hand operand of the binop to emit.
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MachineInstr *emitBinOp(
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const std::array<std::array<unsigned, 2>, 3> &AddrModeAndSizeToOpcode,
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Register Dst, MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitADD(Register DefReg, MachineOperand &LHS,
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MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitADDS(Register Dst, MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitCMN(MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const;
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MachineInstr *emitTST(const Register &LHS, const Register &RHS,
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@ -2462,11 +2511,9 @@ bool AArch64InstructionSelector::select(MachineInstr &I) {
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}
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// Add and set the set condition flag.
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unsigned AddsOpc = OpSize == 32 ? AArch64::ADDSWrr : AArch64::ADDSXrr;
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MachineIRBuilder MIRBuilder(I);
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auto AddsMI = MIRBuilder.buildInstr(AddsOpc, {I.getOperand(0)},
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{I.getOperand(2), I.getOperand(3)});
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constrainSelectedInstRegOperands(*AddsMI, TII, TRI, RBI);
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emitADDS(I.getOperand(0).getReg(), I.getOperand(2), I.getOperand(3),
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MIRBuilder);
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// Now, put the overflow result in the register given by the first operand
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// to the G_UADDO. CSINC increments the result when the predicate is false,
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@ -3749,55 +3796,70 @@ getInsertVecEltOpInfo(const RegisterBank &RB, unsigned EltSize) {
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return std::make_pair(Opc, SubregIdx);
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}
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MachineInstr *AArch64InstructionSelector::emitInstr(
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unsigned Opcode, std::initializer_list<llvm::DstOp> DstOps,
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std::initializer_list<llvm::SrcOp> SrcOps, MachineIRBuilder &MIRBuilder,
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const ComplexRendererFns &RenderFns) const {
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assert(Opcode && "Expected an opcode?");
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assert(!isPreISelGenericOpcode(Opcode) &&
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"Function should only be used to produce selected instructions!");
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auto MI = MIRBuilder.buildInstr(Opcode, DstOps, SrcOps);
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if (RenderFns)
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for (auto &Fn : *RenderFns)
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Fn(MI);
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constrainSelectedInstRegOperands(*MI, TII, TRI, RBI);
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return &*MI;
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}
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MachineInstr *AArch64InstructionSelector::emitBinOp(
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const std::array<std::array<unsigned, 2>, 3> &AddrModeAndSizeToOpcode,
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Register Dst, MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const {
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MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
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assert(LHS.isReg() && RHS.isReg() && "Expected register operands?");
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auto Ty = MRI.getType(LHS.getReg());
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assert(Ty.isScalar() && "Expected a scalar?");
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unsigned Size = Ty.getSizeInBits();
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assert((Size == 32 || Size == 64) && "Expected a 32-bit or 64-bit type only");
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bool Is32Bit = Size == 32;
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if (auto Fns = selectArithImmed(RHS))
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return emitInstr(AddrModeAndSizeToOpcode[0][Is32Bit], {Dst}, {LHS},
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MIRBuilder, Fns);
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if (auto Fns = selectShiftedRegister(RHS))
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return emitInstr(AddrModeAndSizeToOpcode[1][Is32Bit], {Dst}, {LHS},
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MIRBuilder, Fns);
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return emitInstr(AddrModeAndSizeToOpcode[2][Is32Bit], {Dst}, {LHS, RHS},
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MIRBuilder);
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}
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MachineInstr *
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AArch64InstructionSelector::emitADD(Register DefReg, MachineOperand &LHS,
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MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const {
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assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
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MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
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static const unsigned OpcTable[2][2]{{AArch64::ADDXrr, AArch64::ADDXri},
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{AArch64::ADDWrr, AArch64::ADDWri}};
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bool Is32Bit = MRI.getType(LHS.getReg()).getSizeInBits() == 32;
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auto ImmFns = selectArithImmed(RHS);
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unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
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auto AddMI = MIRBuilder.buildInstr(Opc, {DefReg}, {LHS});
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const std::array<std::array<unsigned, 2>, 3> OpcTable{
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{{AArch64::ADDXri, AArch64::ADDWri},
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{AArch64::ADDXrs, AArch64::ADDWrs},
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{AArch64::ADDXrr, AArch64::ADDWrr}}};
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return emitBinOp(OpcTable, DefReg, LHS, RHS, MIRBuilder);
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}
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// If we matched a valid constant immediate, add those operands.
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if (ImmFns) {
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for (auto &RenderFn : *ImmFns)
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RenderFn(AddMI);
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} else {
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AddMI.addUse(RHS.getReg());
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}
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constrainSelectedInstRegOperands(*AddMI, TII, TRI, RBI);
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return &*AddMI;
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MachineInstr *
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AArch64InstructionSelector::emitADDS(Register Dst, MachineOperand &LHS,
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MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const {
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const std::array<std::array<unsigned, 2>, 3> OpcTable{
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{{AArch64::ADDSXri, AArch64::ADDSWri},
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{AArch64::ADDSXrs, AArch64::ADDSWrs},
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{AArch64::ADDSXrr, AArch64::ADDSWrr}}};
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return emitBinOp(OpcTable, Dst, LHS, RHS, MIRBuilder);
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}
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MachineInstr *
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AArch64InstructionSelector::emitCMN(MachineOperand &LHS, MachineOperand &RHS,
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MachineIRBuilder &MIRBuilder) const {
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assert(LHS.isReg() && RHS.isReg() && "Expected LHS and RHS to be registers!");
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MachineRegisterInfo &MRI = MIRBuilder.getMF().getRegInfo();
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static const unsigned OpcTable[2][2]{{AArch64::ADDSXrr, AArch64::ADDSXri},
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{AArch64::ADDSWrr, AArch64::ADDSWri}};
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bool Is32Bit = (MRI.getType(LHS.getReg()).getSizeInBits() == 32);
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auto ImmFns = selectArithImmed(RHS);
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unsigned Opc = OpcTable[Is32Bit][ImmFns.hasValue()];
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Register ZReg = Is32Bit ? AArch64::WZR : AArch64::XZR;
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auto CmpMI = MIRBuilder.buildInstr(Opc, {ZReg}, {LHS});
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// If we matched a valid constant immediate, add those operands.
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if (ImmFns) {
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for (auto &RenderFn : *ImmFns)
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RenderFn(CmpMI);
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} else {
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CmpMI.addUse(RHS.getReg());
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}
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constrainSelectedInstRegOperands(*CmpMI, TII, TRI, RBI);
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return &*CmpMI;
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return emitADDS(Is32Bit ? AArch64::WZR : AArch64::XZR, LHS, RHS, MIRBuilder);
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}
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MachineInstr *
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@ -60,3 +60,54 @@ body: |
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddo_s32_imm
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w0, $w1, $x2
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; Check that we get ADDSWri when we can fold in a constant.
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;
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; CHECK-LABEL: name: uaddo_s32_imm
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: %copy:gpr32sp = COPY $w0
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; CHECK: %add:gpr32 = ADDSWri %copy, 16, 0, implicit-def $nzcv
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; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
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; CHECK: $w0 = COPY %add
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; CHECK: RET_ReallyLR implicit $w0
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%copy:gpr(s32) = COPY $w0
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%constant:gpr(s32) = G_CONSTANT i32 16
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%add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy, %constant
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$w0 = COPY %add(s32)
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RET_ReallyLR implicit $w0
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...
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---
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name: uaddo_s32_shifted
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.1.entry:
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liveins: $w0, $w1, $x2
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; Check that we get ADDSWrs when we can fold in a shift.
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;
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; CHECK-LABEL: name: uaddo_s32_shifted
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; CHECK: liveins: $w0, $w1, $x2
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; CHECK: %copy1:gpr32 = COPY $w0
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; CHECK: %copy2:gpr32 = COPY $w1
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; CHECK: %add:gpr32 = ADDSWrs %copy1, %copy2, 16, implicit-def $nzcv
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; CHECK: %overflow:gpr32 = CSINCWr $wzr, $wzr, 3, implicit $nzcv
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; CHECK: $w0 = COPY %add
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; CHECK: RET_ReallyLR implicit $w0
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%copy1:gpr(s32) = COPY $w0
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%copy2:gpr(s32) = COPY $w1
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%constant:gpr(s32) = G_CONSTANT i32 16
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%shift:gpr(s32) = G_SHL %copy2(s32), %constant(s32)
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%add:gpr(s32), %overflow:gpr(s1) = G_UADDO %copy1, %shift
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$w0 = COPY %add(s32)
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RET_ReallyLR implicit $w0
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