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Update TableGen test files to use the new '...' range punctuation.

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This commit is contained in:
Paul C. Anagnostopoulos 2020-09-11 10:26:26 -04:00
parent 1210dd0a56
commit 6005fe3d82
17 changed files with 67 additions and 66 deletions
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6
test/TableGen/BitsInit.td
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@ -38,8 +38,8 @@ def {
bits<2> D8 = { 0 }; // type mismatch. RHS doesn't have enough bits
bits<8> E;
let E{7..0} = {0,0,1,?,?,?,?,?};
let E{3-0} = 0b0010;
let E{7...0} = {0,0,1,?,?,?,?,?};
let E{3...0} = 0b0010;
bits<8> F1 = { 0, 1, 0b1001, 0, 0b0 }; // ok
bits<7> F2 = { 0, 1, 0b1001, 0, 0b0 }; // LHS doesn't have enough bits
@ -50,7 +50,7 @@ def {
bits<8> G3 = { 0, 1, { 0b1001 }, 0, 0b0 }; // ok
bits<16> H;
let H{15-0} = { { 0b11001100 }, 0b00110011 };
let H{15...0} = { { 0b11001100 }, 0b00110011 };
bits<16> I = { G1, G2 };
// Make sure we can initialise ints with bits<> values.

16
test/TableGen/DAGDefaultOps.td
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@ -16,10 +16,10 @@ class TestEncoding : Instruction {
}
class TestReg<int index> : Register<"R"#index, []> {
let HWEncoding{15-4} = 0;
let HWEncoding{3-0} = !cast<bits<4>>(index);
let HWEncoding{15...4} = 0;
let HWEncoding{3...0} = !cast<bits<4>>(index);
}
foreach i = 0-15 in
foreach i = 0...15 in
def "R"#i : TestReg<i>;
def Reg : RegisterClass<"TestTarget", [i32], 32, (sequence "R%d", 0, 15)>;
@ -36,11 +36,11 @@ class RRI<string Mnemonic, bits<4> Opcode> : TestEncoding {
field bits<4> src1;
field bits<4> src2;
field bits<16> imm;
let Inst{31-28} = Opcode;
let Inst{27-24} = dest;
let Inst{23-20} = src1;
let Inst{19-16} = src2;
let Inst{15-0} = imm;
let Inst{31...28} = Opcode;
let Inst{27...24} = dest;
let Inst{23...20} = src1;
let Inst{19...16} = src2;
let Inst{15...0} = imm;
}
def AddRRI : RRI<"add", 0b0001>;

4
test/TableGen/ForeachLoop.td
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@ -7,7 +7,7 @@ class Register<string name, int idx> {
// CHECK-NOT: !strconcat
foreach i = 0-3 in
foreach i = 0...3 in
def Q#i : Register<"Q"#i, i>;
// CHECK: def Q0
@ -50,7 +50,7 @@ foreach i = [0, 1, 2, 3, 4, 5, 6, 7] in
// CHECK: string Name = "R7";
// CHECK: int Index = 7;
foreach i = {0-3,9-7} in {
foreach i = {0...3,9...7} in {
def S#i : Register<"Q"#i, i>;
def : Register<"T"#i, i>;
}

14
test/TableGen/HwModeEncodeDecode.td
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@ -22,9 +22,9 @@ def fooTypeEncA : InstructionEncoding {
field bits<32> SoftFail = 0;
bits<32> Inst;
bits<8> factor;
let Inst{7-0} = factor;
let Inst{3-2} = 0b11;
let Inst{1-0} = 0b00;
let Inst{7...0} = factor;
let Inst{3...2} = 0b11;
let Inst{1...0} = 0b00;
}
def fooTypeEncB : InstructionEncoding {
@ -32,8 +32,8 @@ def fooTypeEncB : InstructionEncoding {
field bits<32> SoftFail = 0;
bits<32> Inst;
bits<8> factor;
let Inst{15-8} = factor;
let Inst{1-0} = 0b11;
let Inst{15...8} = factor;
let Inst{1...0} = 0b11;
}
let OutOperandList = (outs) in {
@ -52,8 +52,8 @@ def bar: Instruction {
bits<32> Inst;
bits<32> SoftFail;
bits<8> factor;
let Inst{31-24} = factor;
let Inst{1-0} = 0b10;
let Inst{31...24} = factor;
let Inst{1...0} = 0b10;
let AsmString = "bar $factor";
}

4
test/TableGen/JSON.td
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@ -97,8 +97,8 @@ def VarObj : Variables {
bits<2> undef_bits;
bits<4> ref_bits;
let ref_bits{3-2} = 0b10;
let ref_bits{1-0} = undef_bits{1-0};
let ref_bits{3...2} = 0b10;
let ref_bits{1...0} = undef_bits{1...0};
// CHECK: data['VarObj']['ref_bits'][3] == 1
// CHECK: data['VarObj']['ref_bits'][2] == 0
// CHECK: data['VarObj']['ref_bits'][1]['kind'] == 'varbit'

4
test/TableGen/ListSlices.td
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@ -6,12 +6,12 @@ def A {
}
def B {
list<int> X = [10, 20, 30, 4, 1, 1231, 20] [2-4,2,2,0-6];
list<int> X = [10, 20, 30, 4, 1, 1231, 20] [2...4,2,2,0...6];
list<int> Y = X[4,5];
int Z = X[4];
list<int> C = A.B[1-4];
list<int> C = A.B[1...4];
list<list<int>> AA = [X, Y];

4
test/TableGen/UnsetBitInit.td
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@ -21,7 +21,7 @@ def A {
bit P;
bit Q;
let Inst{7-2} = 0x3f;
let Inst{7...2} = 0x3f;
let Inst{1} = P;
let Inst{0} = Q;
@ -34,7 +34,7 @@ class x {
}
class y<bits<2> B> : x {
let A{21-20} = B;
let A{21...20} = B;
}
def z : y<{0,?}>;

14
test/TableGen/cond-let.td
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@ -11,13 +11,13 @@ class C<bits<3> x, bits<4> y, bit z> {
y{1}: x{1},
y{0}: x{2},
{1} :?);
let n{10-9}= !cond(x{2}: y{3-2},
x{1}: y{2-1},
x{1}: y{1-0},
{1} : ?);
let n{8-6} = !cond(x{2}: 0b010, 1 : 0b110);
let n{5-4} = !cond(x{1}: y{3-2}, 1 : {0, 1});
let n{3-0} = !cond(x{0}: y{3-0}, 1 : {z, y{2}, y{1}, y{0}});
let n{10...9}= !cond(x{2}: y{3...2},
x{1}: y{2...1},
x{1}: y{1...0},
{1} : ?);
let n{8...6} = !cond(x{2}: 0b010, 1 : 0b110);
let n{5...4} = !cond(x{1}: y{3...2}, 1 : {0, 1});
let n{3...0} = !cond(x{0}: y{3...0}, 1 : {z, y{2}, y{1}, y{0}});
}

2
test/TableGen/dag-isel-regclass-emit-enum.td
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@ -12,7 +12,7 @@ let Namespace = "TestNamespace" in {
def R0 : Register<"r0">;
foreach i = 0-127 in {
foreach i = 0...127 in {
def GPR#i : RegisterClass<"TestTarget", [i32], 32,
(add R0)>;
}

2
test/TableGen/defset.td
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@ -40,7 +40,7 @@ multiclass C<int c> {
defset list<A> As = {
def A0 : A<1>;
foreach i = 1-2 in {
foreach i = 1...2 in {
def A#i : A<!add(i, 1)>;
}
defset list<A> SubAs = {

32
test/TableGen/foreach-variable-range.td
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@ -13,84 +13,84 @@ def Constants : ConstantsImpl;
// CHECK-DAG: def var_bound_whitespaceA0
// CHECK-DAG: def var_bound_whitespaceA1
// CHECK-DAG: def var_bound_whitespaceA2
foreach Index = Constants.Zero - Constants.Two in {
foreach Index = Constants.Zero ... Constants.Two in {
def var_bound_whitespaceA#Index;
}
// CHECK-DAG: def var_bound_whitespaceB0
// CHECK-DAG: def var_bound_whitespaceB1
// CHECK-DAG: def var_bound_whitespaceB2
foreach Index = Constants.Zero-Constants.Two in {
foreach Index = Constants.Zero...Constants.Two in {
def var_bounds_whitespaceB#Index;
}
// CHECK-DAG: def var_bound_whitespaceC0
// CHECK-DAG: def var_bound_whitespaceC1
// CHECK-DAG: def var_bound_whitespaceC2
foreach Index = Constants.Zero -Constants.Two in {
foreach Index = Constants.Zero ...Constants.Two in {
def var_bounds_whitespaceC#Index;
}
// CHECK-DAG: def var_bound_whitespaceD0
// CHECK-DAG: def var_bound_whitespaceD1
// CHECK-DAG: def var_bound_whitespaceD2
foreach Index = Constants.Zero- Constants.Two in {
foreach Index = Constants.Zero... Constants.Two in {
def var_bounds_whitespaceD#Index;
}
// CHECK-DAG: def const_lower_whitespaceA0
// CHECK-DAG: def const_lower_whitespaceA1
// CHECK-DAG: def const_lower_whitespaceA2
foreach Index = 0 - Constants.Two in {
foreach Index = 0 ... Constants.Two in {
def const_lower_whitespaceA#Index;
}
// CHECK-DAG: def const_lower_whitespaceB0
// CHECK-DAG: def const_lower_whitespaceB1
// CHECK-DAG: def const_lower_whitespaceB2
foreach Index = 0-Constants.Two in {
foreach Index = 0...Constants.Two in {
def const_lower_whitespaceB#Index;
}
// CHECK-DAG: def const_lower_whitespaceC0
// CHECK-DAG: def const_lower_whitespaceC1
// CHECK-DAG: def const_lower_whitespaceC2
foreach Index = 0 -Constants.Two in {
foreach Index = 0 ...Constants.Two in {
def const_lower_whitespaceC#Index;
}
// CHECK-DAG: def const_lower_whitespaceD0
// CHECK-DAG: def const_lower_whitespaceD1
// CHECK-DAG: def const_lower_whitespaceD2
foreach Index = 0- Constants.Two in {
foreach Index = 0... Constants.Two in {
def const_lower_whitespaceD#Index;
}
// CHECK-DAG: def const_upper_whitespaceA0
// CHECK-DAG: def const_upper_whitespaceA1
// CHECK-DAG: def const_upper_whitespaceA2
foreach Index = Constants.Zero - 2 in {
foreach Index = Constants.Zero ... 2 in {
def const_upper_whitespaceA#Index;
}
// CHECK-DAG: def const_upper_whitespaceB0
// CHECK-DAG: def const_upper_whitespaceB1
// CHECK-DAG: def const_upper_whitespaceB2
foreach Index = Constants.Zero-2 in {
foreach Index = Constants.Zero...2 in {
def const_upper_whitespaceB#Index;
}
// CHECK-DAG: def const_upper_whitespaceC0
// CHECK-DAG: def const_upper_whitespaceC1
// CHECK-DAG: def const_upper_whitespaceC2
foreach Index = Constants.Zero -2 in {
foreach Index = Constants.Zero ...2 in {
def const_upper_whitespaceC#Index;
}
// CHECK-DAG: def const_upper_whitespaceD0
// CHECK-DAG: def const_upper_whitespaceD1
// CHECK-DAG: def const_upper_whitespaceD2
foreach Index = Constants.Zero- 2 in {
foreach Index = Constants.Zero... 2 in {
def const_upper_whitespaceD#Index;
}
@ -98,7 +98,7 @@ foreach Index = Constants.Zero- 2 in {
// CHECK-DAG: def multi_rangeA1
// CHECK-DAG: def multi_rangeA2
// CHECK-DAG: def multi_rangeA3
foreach Index = {Constants.Zero-Constants.One, Constants.Two-Constants.Three} in {
foreach Index = {Constants.Zero...Constants.One, Constants.Two...Constants.Three} in {
def multi_rangeA#Index;
}
@ -107,7 +107,7 @@ foreach Index = {Constants.Zero-Constants.One, Constants.Two-Constants.Three} in
// CHECK-DAG: def multi_rangeB3
// CHECK-DAG: def multi_rangeB4
// CHECK-DAG: def multi_rangeB5
foreach Index = {0-Constants.One, Constants.Three-Constants.Five} in {
foreach Index = {0...Constants.One, Constants.Three...Constants.Five} in {
def multi_rangeB#Index;
}
@ -115,7 +115,7 @@ foreach Index = {0-Constants.One, Constants.Three-Constants.Five} in {
// CHECK-DAG: def multi_rangeC1
// CHECK-DAG: def multi_rangeC2
// CHECK-DAG: def multi_rangeC3
foreach Index = {0-Constants.One, 2-Constants.Three} in {
foreach Index = {0...Constants.One, 2...Constants.Three} in {
def multi_rangeC#Index;
}
@ -123,6 +123,6 @@ foreach Index = {0-Constants.One, 2-Constants.Three} in {
// CHECK-DAG: def multi_rangeD1
// CHECK-DAG: def multi_rangeD2
// CHECK-DAG: def multi_rangeD3
foreach Index = {0-1, Constants.Two-3} in {
foreach Index = {0...1, Constants.Two...3} in {
def multi_rangeD#Index;
}

12
test/TableGen/if.td
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@ -11,12 +11,12 @@ class C<bits<3> x, bits<4> y, bit z> {
!if(y{2}, x{0},
!if(y{1}, x{1},
!if(y{0}, x{2}, ?))));
let n{10-9}= !if(x{2}, y{3-2},
!if(x{1}, y{2-1},
!if(x{0}, y{1-0}, ?)));
let n{8-6} = !if(x{2}, 0b010, 0b110);
let n{5-4} = !if(x{1}, y{3-2}, {0, 1});
let n{3-0} = !if(x{0}, y{3-0}, {z, y{2}, y{1}, y{0}});
let n{10...9}= !if(x{2}, y{3...2},
!if(x{1}, y{2...1},
!if(x{0}, y{1...0}, ?)));
let n{8...6} = !if(x{2}, 0b010, 0b110);
let n{5...4} = !if(x{1}, y{3...2}, {0, 1});
let n{3...0} = !if(x{0}, y{3...0}, {z, y{2}, y{1}, y{0}});
}
def C1 : C<{1, 0, 1}, {0, 1, 0, 1}, 0>;

6
test/TableGen/ifstmt.td
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@ -15,7 +15,7 @@ if 1 then def aYes;
// CHECK: def bNotThree2
// CHECK: def bNotThree4
// CHECK: def bThree3
foreach i = 1-4 in {
foreach i = 1...4 in {
if !eq(i, 3) then {
def "bThree" # i;
} else {
@ -61,8 +61,8 @@ defm c3: Multi<3>;
// CHECK-NOT: def dThenElse1
// CHECK-NOT: def dThenElse11
// CHECK: def dThenThen01
foreach i = 0-1 in
foreach j = 0-1 in
foreach i = 0...1 in
foreach j = 0...1 in
if !eq(i,0) then
if !eq(j,1) then
def "dThenThen"#i#j;

4
test/TableGen/list-element-bitref.td
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@ -2,8 +2,8 @@
// XFAIL: vg_leak
class C<list<bits<4>> L> {
bits<2> V0 = L[0]{1-0};
bits<2> V1 = L[1]{3-2};
bits<2> V0 = L[0]{1...0};
bits<2> V1 = L[1]{3...2};
string V2 = !if(L[0]{0}, "Odd", "Even");
}

3
test/TableGen/range-lists.td
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@ -1,7 +1,8 @@
// RUN: llvm-tblgen %s | FileCheck %s
// XFAIL: vg_leak
// This file has tests for range lists and range pieces.
// This file has tests for range lists and range pieces. Some use the
// deprecated '-' range punctuation just to be sure it still works.
// These are tests for bits ranges.

2
test/TableGen/simplify-patfrag.td
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@ -9,7 +9,7 @@ def Demo : Target {
}
// Some registers which can hold ints or floats
foreach i = 0-7 in
foreach i = 0...7 in
def "R" # i: Register<"r" # i>;
def GPR : RegisterClass<"Demo", [i32, f32], 32, (sequence "R%u", 0, 7)>;

4
test/TableGen/trydecode-emission3.td
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@ -28,8 +28,8 @@ def InstBOp : Operand<i32> {
def InstB : TestInstruction {
bits<2> op;
let Inst{7-2} = {0,0,0,0,0,0};
let Inst{1-0} = op;
let Inst{7...2} = {0,0,0,0,0,0};
let Inst{1...0} = op;
let OutOperandList = (outs InstBOp:$op);
let AsmString = "InstB";
}