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ExecutionDepsFix refactoring:
- Moving comments to class definition in header file - Changing comments to doxygen style - Rephrase loop traversal explaining comment This is the one of multiple patches that fix bugzilla https://bugs.llvm.org/show_bug.cgi?id=33869 Most of the patches are intended at refactoring the existent code. Additional relevant reviews: https://reviews.llvm.org/D40330 https://reviews.llvm.org/D40332 https://reviews.llvm.org/D40333 https://reviews.llvm.org/D40334 Differential Revision: https://reviews.llvm.org/D40331 Change-Id: I9a12618db5b66128611fa71b54a233414f6012ac llvm-svn: 323092
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@ -52,29 +52,29 @@ class TargetInstrInfo;
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/// keep track of the fact that the register is now available in multiple
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/// domains.
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struct DomainValue {
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// Basic reference counting.
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/// Basic reference counting.
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unsigned Refs = 0;
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// Bitmask of available domains. For an open DomainValue, it is the still
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// possible domains for collapsing. For a collapsed DomainValue it is the
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// domains where the register is available for free.
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/// Bitmask of available domains. For an open DomainValue, it is the still
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/// possible domains for collapsing. For a collapsed DomainValue it is the
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/// domains where the register is available for free.
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unsigned AvailableDomains;
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// Pointer to the next DomainValue in a chain. When two DomainValues are
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// merged, Victim.Next is set to point to Victor, so old DomainValue
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// references can be updated by following the chain.
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/// Pointer to the next DomainValue in a chain. When two DomainValues are
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/// merged, Victim.Next is set to point to Victor, so old DomainValue
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/// references can be updated by following the chain.
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DomainValue *Next;
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// Twiddleable instructions using or defining these registers.
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/// Twiddleable instructions using or defining these registers.
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SmallVector<MachineInstr*, 8> Instrs;
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DomainValue() { clear(); }
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// A collapsed DomainValue has no instructions to twiddle - it simply keeps
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// track of the domains where the registers are already available.
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/// A collapsed DomainValue has no instructions to twiddle - it simply keeps
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/// track of the domains where the registers are already available.
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bool isCollapsed() const { return Instrs.empty(); }
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// Is domain available?
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/// Is domain available?
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bool hasDomain(unsigned domain) const {
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assert(domain <
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static_cast<unsigned>(std::numeric_limits<unsigned>::digits) &&
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@ -82,7 +82,7 @@ struct DomainValue {
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return AvailableDomains & (1u << domain);
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}
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// Mark domain as available.
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/// Mark domain as available.
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void addDomain(unsigned domain) {
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AvailableDomains |= 1u << domain;
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}
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@ -92,17 +92,17 @@ struct DomainValue {
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AvailableDomains = 1u << domain;
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}
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// Return bitmask of domains that are available and in mask.
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/// Return bitmask of domains that are available and in mask.
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unsigned getCommonDomains(unsigned mask) const {
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return AvailableDomains & mask;
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}
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// First domain available.
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/// First domain available.
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unsigned getFirstDomain() const {
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return countTrailingZeros(AvailableDomains);
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}
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// Clear this DomainValue and point to next which has all its data.
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/// Clear this DomainValue and point to next which has all its data.
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void clear() {
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AvailableDomains = 0;
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Next = nullptr;
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@ -114,30 +114,69 @@ struct DomainValue {
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/// ReachingDefAnalysis and ExecutionDomainFix.
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/// It identifies basic blocks that are part of loops and should to be visited twice
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/// and returns efficient traversal order for all the blocks.
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///
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/// We want to visit every instruction in every basic block in order to update
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/// it's execution domain or collect clearance information. However, for the
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/// clearance calculation, we need to know clearances from all predecessors
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/// (including any backedges), therfore we need to visit some blocks twice.
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/// As an example, consider the following loop.
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///
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///
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/// PH -> A -> B (xmm<Undef> -> xmm<Def>) -> C -> D -> EXIT
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/// ^ |
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/// +----------------------------------+
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///
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/// The iteration order this pass will return is as follows:
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/// Optimized: PH A B C A' B' C' D
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///
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/// The basic block order is constructed as follows:
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/// Once we finish processing some block, we update the counters in MBBInfos
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/// and re-process any successors that are now 'done'.
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/// We call a block that is ready for its final round of processing `done`
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/// (isBlockDone), e.g. when all predecessor information is known.
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///
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/// Note that a naive traversal order would be to do two complete passes over
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/// all basic blocks/instructions, the first for recording clearances, the
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/// second for updating clearance based on backedges.
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/// However, for functions without backedges, or functions with a lot of
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/// straight-line code, and a small loop, that would be a lot of unnecessary
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/// work (since only the BBs that are part of the loop require two passes).
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///
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/// E.g., the naive iteration order for the above exmple is as follows:
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/// Naive: PH A B C D A' B' C' D'
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///
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/// In the optimized approach we avoid processing D twice, because we
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/// can entirely process the predecessors before getting to D.
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class LoopTraversal {
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private:
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struct MBBInfo {
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// Whether we have gotten to this block in primary processing yet.
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/// Whether we have gotten to this block in primary processing yet.
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bool PrimaryCompleted = false;
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// The number of predecessors for which primary processing has completed
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/// The number of predecessors for which primary processing has completed
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unsigned IncomingProcessed = 0;
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// The value of `IncomingProcessed` at the start of primary processing
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/// The value of `IncomingProcessed` at the start of primary processing
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unsigned PrimaryIncoming = 0;
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// The number of predecessors for which all processing steps are done.
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/// The number of predecessors for which all processing steps are done.
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unsigned IncomingCompleted = 0;
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MBBInfo() = default;
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};
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using MBBInfoMap = SmallVector<MBBInfo, 4>;
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/// Helps keep track if we proccessed this block and all its predecessors.
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MBBInfoMap MBBInfos;
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public:
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struct TraversedMBBInfo {
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/// The basic block.
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MachineBasicBlock *MBB = nullptr;
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/// True if this is the first time we process the basic block.
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bool PrimaryPass = true;
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/// True if the block that is ready for its final round of processing.
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bool IsDone = true;
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TraversedMBBInfo(MachineBasicBlock *BB = nullptr, bool Primary = true,
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@ -146,10 +185,13 @@ public:
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};
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LoopTraversal() {}
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/// \brief Identifies basic blocks that are part of loops and should to be
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/// visited twise and returns efficient traversal order for all the blocks.
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typedef SmallVector<TraversedMBBInfo, 4> TraversalOrder;
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TraversalOrder traverse(MachineFunction &MF);
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private:
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/// Returens true if the block is ready for its final round of processing.
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bool isBlockDone(MachineBasicBlock *MBB);
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};
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@ -168,9 +210,9 @@ private:
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using LiveRegsDefInfo = std::vector<int>;
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LiveRegsDefInfo LiveRegs;
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// Keeps clearance information for all registers. Note that this
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// is different from the usual definition notion of liveness. The CPU
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// doesn't care whether or not we consider a register killed.
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/// Keeps clearance information for all registers. Note that this
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/// is different from the usual definition notion of liveness. The CPU
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/// doesn't care whether or not we consider a register killed.
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using OutRegsInfoMap = SmallVector<LiveRegsDefInfo, 4>;
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OutRegsInfoMap MBBOutRegsInfos;
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@ -190,7 +232,7 @@ private:
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using MBBReachingDefsInfo = SmallVector<MBBDefsInfo, 4>;
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MBBReachingDefsInfo MBBReachingDefs;
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// Default values are 'nothing happened a long time ago'.
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/// Default values are 'nothing happened a long time ago'.
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const int ReachingDedDefaultVal = -(1 << 20);
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public:
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@ -216,14 +258,23 @@ public:
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/// Provides the instruction id of the closest reaching def instruction of
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/// PhysReg that reaches MI, relative to the begining of MI's basic block.
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int getReachingDef(MachineInstr *MI, int PhysReg);
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/// Provides the clearance - the number of instructions since the closest
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/// reaching def instuction of PhysReg that reaches MI.
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int getClearance(MachineInstr *MI, MCPhysReg PhysReg);
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private:
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/// Set up LiveRegs by merging predecessor live-out values.
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void enterBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Update live-out values.
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void leaveBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Process he given basic block.
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void processBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Update def-ages for registers defined by MI.
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/// Also break dependencies on partial defs and undef uses.
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void processDefs(MachineInstr *);
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};
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@ -241,9 +292,9 @@ class ExecutionDomainFix : public MachineFunctionPass {
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/// This counts as a DomainValue reference.
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using LiveRegsDVInfo = std::vector<DomainValue *>;
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LiveRegsDVInfo LiveRegs;
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// Keeps domain information for all registers. Note that this
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// is different from the usual definition notion of liveness. The CPU
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// doesn't care whether or not we consider a register killed.
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/// Keeps domain information for all registers. Note that this
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/// is different from the usual definition notion of liveness. The CPU
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/// doesn't care whether or not we consider a register killed.
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using OutRegsInfoMap = SmallVector<LiveRegsDVInfo, 4>;
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OutRegsInfoMap MBBOutRegsInfos;
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@ -267,30 +318,65 @@ public:
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}
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private:
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/// Translate TRI register number to a list of indices into our smaller tables
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/// of interesting registers.
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iterator_range<SmallVectorImpl<int>::const_iterator>
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regIndices(unsigned Reg) const;
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// DomainValue allocation.
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/// DomainValue allocation.
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DomainValue *alloc(int domain = -1);
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/// Add reference to DV.
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DomainValue *retain(DomainValue *DV) {
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if (DV) ++DV->Refs;
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return DV;
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}
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/// Release a reference to DV. When the last reference is released,
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/// collapse if needed.
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void release(DomainValue*);
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/// Follow the chain of dead DomainValues until a live DomainValue is reached.
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/// Update the referenced pointer when necessary.
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DomainValue *resolve(DomainValue*&);
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// LiveRegs manipulations.
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/// Set LiveRegs[rx] = dv, updating reference counts.
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void setLiveReg(int rx, DomainValue *DV);
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/// Kill register rx, recycle or collapse any DomainValue.
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void kill(int rx);
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/// Force register rx into domain.
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void force(int rx, unsigned domain);
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/// Collapse open DomainValue into given domain. If there are multiple
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/// registers using dv, they each get a unique collapsed DomainValue.
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void collapse(DomainValue *dv, unsigned domain);
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/// All instructions and registers in B are moved to A, and B is released.
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bool merge(DomainValue *A, DomainValue *B);
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/// Set up LiveRegs by merging predecessor live-out values.
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void enterBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Update live-out values.
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void leaveBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Process he given basic block.
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void processBasicBlock(const LoopTraversal::TraversedMBBInfo &TraversedMBB);
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/// Visit given insturcion.
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bool visitInstr(MachineInstr *);
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/// Update def-ages for registers defined by MI.
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/// If Kill is set, also kill off DomainValues clobbered by the defs.
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void processDefs(MachineInstr *, bool Kill);
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/// A soft instruction can be changed to work in other domains given by mask.
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void visitSoftInstr(MachineInstr*, unsigned mask);
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/// A hard instruction only works in one domain. All input registers will be
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/// forced into that domain.
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void visitHardInstr(MachineInstr*, unsigned domain);
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};
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@ -330,11 +416,30 @@ public:
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}
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private:
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/// Process he given basic block.
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void processBasicBlock(MachineBasicBlock *MBB);
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/// Update def-ages for registers defined by MI.
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/// Also break dependencies on partial defs and undef uses.
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void processDefs(MachineInstr *MI);
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/// \brief Helps avoid false dependencies on undef registers by updating the
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/// machine instructions' undef operand to use a register that the instruction
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/// is truly dependent on, or use a register with clearance higher than Pref.
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/// Returns true if it was able to find a true dependency, thus not requiring
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/// a dependency breaking instruction regardless of clearance.
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bool pickBestRegisterForUndef(MachineInstr *MI, unsigned OpIdx,
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unsigned Pref);
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/// \brief Return true to if it makes sense to break dependence on a partial def
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/// or undef use.
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bool shouldBreakDependence(MachineInstr*, unsigned OpIdx, unsigned Pref);
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/// \brief Break false dependencies on undefined register reads.
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/// Walk the block backward computing precise liveness. This is expensive, so we
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/// only do it on demand. Note that the occurrence of undefined register reads
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/// that should be broken is very rare, but when they occur we may have many in
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/// a single block.
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void processUndefReads(MachineBasicBlock*);
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};
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@ -27,8 +27,6 @@ INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
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INITIALIZE_PASS_END(BreakFalseDeps, "break-false-deps", "BreakFalseDeps", false,
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false)
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/// Translate TRI register number to a list of indices into our smaller tables
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/// of interesting registers.
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iterator_range<SmallVectorImpl<int>::const_iterator>
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ExecutionDomainFix::regIndices(unsigned Reg) const {
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assert(Reg < AliasMap.size() && "Invalid register");
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@ -47,8 +45,6 @@ DomainValue *ExecutionDomainFix::alloc(int domain) {
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return dv;
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}
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/// Release a reference to DV. When the last reference is released,
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/// collapse if needed.
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void ExecutionDomainFix::release(DomainValue *DV) {
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while (DV) {
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assert(DV->Refs && "Bad DomainValue");
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@ -67,8 +63,6 @@ void ExecutionDomainFix::release(DomainValue *DV) {
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}
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}
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/// Follow the chain of dead DomainValues until a live DomainValue is reached.
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/// Update the referenced pointer when necessary.
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DomainValue *ExecutionDomainFix::resolve(DomainValue *&DVRef) {
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DomainValue *DV = DVRef;
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if (!DV || !DV->Next)
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@ -85,7 +79,6 @@ DomainValue *ExecutionDomainFix::resolve(DomainValue *&DVRef) {
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return DV;
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}
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/// Set LiveRegs[rx] = dv, updating reference counts.
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void ExecutionDomainFix::setLiveReg(int rx, DomainValue *dv) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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@ -97,7 +90,6 @@ void ExecutionDomainFix::setLiveReg(int rx, DomainValue *dv) {
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LiveRegs[rx] = retain(dv);
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}
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// Kill register rx, recycle or collapse any DomainValue.
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void ExecutionDomainFix::kill(int rx) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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@ -108,7 +100,6 @@ void ExecutionDomainFix::kill(int rx) {
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LiveRegs[rx] = nullptr;
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}
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/// Force register rx into domain.
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void ExecutionDomainFix::force(int rx, unsigned domain) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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assert(!LiveRegs.empty() && "Must enter basic block first.");
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@ -130,8 +121,6 @@ void ExecutionDomainFix::force(int rx, unsigned domain) {
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}
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}
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/// Collapse open DomainValue into given domain. If there are multiple
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/// registers using dv, they each get a unique collapsed DomainValue.
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void ExecutionDomainFix::collapse(DomainValue *dv, unsigned domain) {
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assert(dv->hasDomain(domain) && "Cannot collapse");
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@ -147,7 +136,6 @@ void ExecutionDomainFix::collapse(DomainValue *dv, unsigned domain) {
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setLiveReg(rx, alloc(domain));
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}
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/// All instructions and registers in B are moved to A, and B is released.
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bool ExecutionDomainFix::merge(DomainValue *A, DomainValue *B) {
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assert(!A->isCollapsed() && "Cannot merge into collapsed");
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assert(!B->isCollapsed() && "Cannot merge from collapsed");
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@ -173,7 +161,6 @@ bool ExecutionDomainFix::merge(DomainValue *A, DomainValue *B) {
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return true;
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}
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/// Set up LiveRegs by merging predecessor live-out values.
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void ReachingDefAnalysis::enterBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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@ -228,7 +215,6 @@ void ReachingDefAnalysis::enterBasicBlock(
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<< (!TraversedMBB.IsDone ? ": incomplete\n" : ": all preds known\n"));
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}
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/// Set up LiveRegs by merging predecessor live-out values.
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void ExecutionDomainFix::enterBasicBlock(
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const LoopTraversal::TraversedMBBInfo &TraversedMBB) {
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@ -328,11 +314,6 @@ bool ExecutionDomainFix::visitInstr(MachineInstr *MI) {
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return !DomP.first;
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}
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/// \brief Helps avoid false dependencies on undef registers by updating the
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/// machine instructions' undef operand to use a register that the instruction
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/// is truly dependent on, or use a register with clearance higher than Pref.
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/// Returns true if it was able to find a true dependency, thus not requiring
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/// a dependency breaking instruction regardless of clearance.
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bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI,
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unsigned OpIdx, unsigned Pref) {
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MachineOperand &MO = MI->getOperand(OpIdx);
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@ -389,8 +370,6 @@ bool BreakFalseDeps::pickBestRegisterForUndef(MachineInstr *MI,
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return false;
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}
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/// \brief Return true to if it makes sense to break dependence on a partial def
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/// or undef use.
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bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
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unsigned Pref) {
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unsigned reg = MI->getOperand(OpIdx).getReg();
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@ -405,10 +384,6 @@ bool BreakFalseDeps::shouldBreakDependence(MachineInstr *MI, unsigned OpIdx,
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return false;
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}
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// Update def-ages for registers defined by MI.
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// If Kill is set, also kill off DomainValues clobbered by the defs.
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//
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// Also break dependencies on partial defs and undef uses.
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void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
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assert(!MI->isDebugValue() && "Won't process debug values");
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const MCInstrDesc &MCID = MI->getDesc();
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@ -431,8 +406,6 @@ void ExecutionDomainFix::processDefs(MachineInstr *MI, bool Kill) {
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}
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}
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// Update def-ages for registers defined by MI.
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// Also break dependencies on partial defs and undef uses.
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void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
|
||||
assert(!MI->isDebugValue() && "Won't process debug values");
|
||||
|
||||
@ -461,8 +434,6 @@ void ReachingDefAnalysis::processDefs(MachineInstr *MI) {
|
||||
++CurInstr;
|
||||
}
|
||||
|
||||
// Update def-ages for registers defined by MI.
|
||||
// Also break dependencies on partial defs and undef uses.
|
||||
void BreakFalseDeps::processDefs(MachineInstr *MI) {
|
||||
assert(!MI->isDebugValue() && "Won't process debug values");
|
||||
|
||||
@ -494,12 +465,6 @@ void BreakFalseDeps::processDefs(MachineInstr *MI) {
|
||||
}
|
||||
}
|
||||
|
||||
/// \break Break false dependencies on undefined register reads.
|
||||
///
|
||||
/// Walk the block backward computing precise liveness. This is expensive, so we
|
||||
/// only do it on demand. Note that the occurrence of undefined register reads
|
||||
/// that should be broken is very rare, but when they occur we may have many in
|
||||
/// a single block.
|
||||
void BreakFalseDeps::processUndefReads(MachineBasicBlock *MBB) {
|
||||
if (UndefReads.empty())
|
||||
return;
|
||||
@ -531,8 +496,6 @@ void BreakFalseDeps::processUndefReads(MachineBasicBlock *MBB) {
|
||||
}
|
||||
}
|
||||
|
||||
// A hard instruction only works in one domain. All input registers will be
|
||||
// forced into that domain.
|
||||
void ExecutionDomainFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
|
||||
// Collapse all uses.
|
||||
for (unsigned i = mi->getDesc().getNumDefs(),
|
||||
@ -555,7 +518,6 @@ void ExecutionDomainFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
|
||||
}
|
||||
}
|
||||
|
||||
// A soft instruction can be changed to work in other domains given by mask.
|
||||
void ExecutionDomainFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
|
||||
// Bitmask of available domains for this instruction after taking collapsed
|
||||
// operands into account.
|
||||
@ -720,34 +682,6 @@ LoopTraversal::traverse(MachineFunction &MF) {
|
||||
// Initialize the MMBInfos
|
||||
MBBInfos.assign(MF.getNumBlockIDs(), MBBInfo());
|
||||
|
||||
/*
|
||||
* We want to visit every instruction in every basic block in order to update
|
||||
* it's execution domain or break any false dependencies. However, for the
|
||||
* dependency breaking, we need to know clearances from all predecessors
|
||||
* (including any backedges). One way to do so would be to do two complete
|
||||
* passes over all basic blocks/instructions, the first for recording
|
||||
* clearances, the second to break the dependencies. However, for functions
|
||||
* without backedges, or functions with a lot of straight-line code, and
|
||||
* a small loop, that would be a lot of unnecessary work (since only the
|
||||
* BBs that are part of the loop require two passes). As an example,
|
||||
* consider the following loop.
|
||||
*
|
||||
*
|
||||
* PH -> A -> B (xmm<Undef> -> xmm<Def>) -> C -> D -> EXIT
|
||||
* ^ |
|
||||
* +----------------------------------+
|
||||
*
|
||||
* The iteration order is as follows:
|
||||
* Naive: PH A B C D A' B' C' D'
|
||||
* Optimized: PH A B C A' B' C' D
|
||||
*
|
||||
* Note that we avoid processing D twice, because we can entirely process
|
||||
* the predecessors before getting to D. We call a block that is ready
|
||||
* for its second round of processing `done` (isBlockDone). Once we finish
|
||||
* processing some block, we update the counters in MBBInfos and re-process
|
||||
* any successors that are now done.
|
||||
*/
|
||||
|
||||
MachineBasicBlock *Entry = &*MF.begin();
|
||||
ReversePostOrderTraversal<MachineBasicBlock*> RPOT(Entry);
|
||||
SmallVector<MachineBasicBlock *, 4> Workqueue;
|
||||
|
Loading…
Reference in New Issue
Block a user