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Remove unnecessary let hasCtrlDep=1 now it can be inferred.

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llvm-svn: 24611
This commit is contained in:
Evan Cheng 2005-12-05 23:09:43 +00:00
parent 3d51fa3305
commit 60cc8da341
1 changed files with 24 additions and 26 deletions
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50
lib/Target/X86/X86InstrInfo.td
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@ -193,13 +193,13 @@ let isTerminator = 1 in
// //
// Return instructions. // Return instructions.
let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in let isTerminator = 1, isReturn = 1, isBarrier = 1 in
def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>; def RET : I<0xC3, RawFrm, (ops), "ret", [(ret)]>;
let isTerminator = 1, isReturn = 1, isBarrier = 1, hasCtrlDep=1 in let isTerminator = 1, isReturn = 1, isBarrier = 1 in
def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>; def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt", []>;
// All branches are RawFrm, Void, Branch, and Terminators // All branches are RawFrm, Void, Branch, and Terminators
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in let isBranch = 1, isTerminator = 1 in
class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> : class IBr<bits<8> opcode, dag ops, string asm, list<dag> pattern> :
I<opcode, RawFrm, ops, asm, pattern>; I<opcode, RawFrm, ops, asm, pattern>;
@ -332,30 +332,28 @@ def IN16ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port), def IN32ri : Ii8<0xE5, RawFrm, (ops i8imm:$port),
"in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>; "in{l} {$port, %eax|%EAX, $port}", []>, Imp<[],[EAX]>;
let hasCtrlDep=1 in { def OUT8rr : I<0xEE, RawFrm, (ops),
def OUT8rr : I<0xEE, RawFrm, (ops), "out{b} {%al, %dx|%DX, %AL}",
"out{b} {%al, %dx|%DX, %AL}", [(writeport AL, DX)]>, Imp<[DX, AL], []>;
[(writeport AL, DX)]>, Imp<[DX, AL], []>; def OUT16rr : I<0xEF, RawFrm, (ops),
def OUT16rr : I<0xEF, RawFrm, (ops), "out{w} {%ax, %dx|%DX, %AX}",
"out{w} {%ax, %dx|%DX, %AX}", [(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize;
[(writeport AX, DX)]>, Imp<[DX, AX], []>, OpSize; def OUT32rr : I<0xEF, RawFrm, (ops),
def OUT32rr : I<0xEF, RawFrm, (ops), "out{l} {%eax, %dx|%DX, %EAX}",
"out{l} {%eax, %dx|%DX, %EAX}", [(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
[(writeport EAX, DX)]>, Imp<[DX, EAX], []>;
def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port), def OUT8ir : Ii8<0xE6, RawFrm, (ops i16i8imm:$port),
"out{b} {%al, $port|$port, %AL}", "out{b} {%al, $port|$port, %AL}",
[(writeport AL, (i16 immZExt8:$port))]>, [(writeport AL, (i16 immZExt8:$port))]>,
Imp<[AL], []>; Imp<[AL], []>;
def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), def OUT16ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
"out{w} {%ax, $port|$port, %AX}", "out{w} {%ax, $port|$port, %AX}",
[(writeport AX, (i16 immZExt8:$port))]>, [(writeport AX, (i16 immZExt8:$port))]>,
Imp<[AX], []>, OpSize; Imp<[AX], []>, OpSize;
def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port), def OUT32ir : Ii8<0xE7, RawFrm, (ops i16i8imm:$port),
"out{l} {%eax, $port|$port, %EAX}", "out{l} {%eax, $port|$port, %EAX}",
[(writeport EAX, (i16 immZExt8:$port))]>, [(writeport EAX, (i16 immZExt8:$port))]>,
Imp<[EAX], []>; Imp<[EAX], []>;
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Move Instructions... // Move Instructions...