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[TargetLowering] Add ISD::EXTRACT_VECTOR_ELT support to SimplifyDemandedBits

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Let SimplifyDemandedBits attempt to simplify all elements of a vector extraction.

Part of PR39689.

llvm-svn: 348839
This commit is contained in:
Simon Pilgrim 2018-12-11 11:08:40 +00:00
parent 908f7120f3
commit 60da28c9f9
3 changed files with 23 additions and 12 deletions
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19
lib/CodeGen/SelectionDAG/TargetLowering.cpp
View File

@ -1220,6 +1220,25 @@ bool TargetLowering::SimplifyDemandedBits(SDValue Op,
Known.Zero |= ~InMask;
break;
}
case ISD::EXTRACT_VECTOR_ELT: {
// Demand the bits from every vector element.
SDValue Src = Op.getOperand(0);
unsigned EltBitWidth = Src.getScalarValueSizeInBits();
// If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
// anything about the extended bits.
APInt DemandedSrcBits = DemandedBits;
if (BitWidth > EltBitWidth)
DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth);
if (SimplifyDemandedBits(Src, DemandedSrcBits, Known2, TLO, Depth + 1))
return true;
Known = Known2;
if (BitWidth > EltBitWidth)
Known = Known.zext(BitWidth);
break;
}
case ISD::BITCAST: {
SDValue Src = Op.getOperand(0);
EVT SrcVT = Src.getValueType();

12
test/CodeGen/X86/known-signbits-vector.ll
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@ -74,11 +74,9 @@ define float @signbits_ashr_extract_sitofp_0(<2 x i64> %a0) nounwind {
;
; X64-LABEL: signbits_ashr_extract_sitofp_0:
; X64: # %bb.0:
; X64-NEXT: vpsrad $31, %xmm0, %xmm1
; X64-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[1,1,3,3]
; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X64-NEXT: vpsrlq $32, %xmm0, %xmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vcvtsi2ssl %eax, %xmm2, %xmm0
; X64-NEXT: vcvtsi2ssl %eax, %xmm1, %xmm0
; X64-NEXT: retq
%1 = ashr <2 x i64> %a0, <i64 32, i64 32>
%2 = extractelement <2 x i64> %1, i32 0
@ -183,9 +181,7 @@ define float @signbits_ashr_insert_ashr_extract_sitofp(i64 %a0, i64 %a1) nounwin
; X64-NEXT: vmovq %rsi, %xmm0
; X64-NEXT: vmovq %rdi, %xmm1
; X64-NEXT: vpunpcklqdq {{.*#+}} xmm0 = xmm1[0],xmm0[0]
; X64-NEXT: vpsrad $3, %xmm0, %xmm1
; X64-NEXT: vpsrlq $3, %xmm0, %xmm0
; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5],xmm1[6,7]
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vcvtsi2ssl %eax, %xmm2, %xmm0
; X64-NEXT: retq
@ -282,10 +278,6 @@ define float @signbits_ashr_sext_sextinreg_and_extract_sitofp(<2 x i64> %a0, <2
; X64-NEXT: vpsubq %xmm2, %xmm0, %xmm0
; X64-NEXT: movslq %edi, %rax
; X64-NEXT: vpinsrq $0, %rax, %xmm1, %xmm1
; X64-NEXT: vpsllq $20, %xmm1, %xmm1
; X64-NEXT: vpsrad $20, %xmm1, %xmm2
; X64-NEXT: vpsrlq $20, %xmm1, %xmm1
; X64-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3],xmm1[4,5],xmm2[6,7]
; X64-NEXT: vpand %xmm1, %xmm0, %xmm0
; X64-NEXT: vmovq %xmm0, %rax
; X64-NEXT: vcvtsi2ssl %eax, %xmm3, %xmm0

4
test/CodeGen/X86/pr35918.ll
View File

@ -16,7 +16,7 @@ define void @fetch_r16g16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32],
; X86-SKYLAKE-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X86-SKYLAKE-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X86-SKYLAKE-NEXT: vpsrld $7, %xmm0, %xmm0
; X86-SKYLAKE-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4],zero,zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u]
; X86-SKYLAKE-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4],zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u,u]
; X86-SKYLAKE-NEXT: vmovd %xmm0, %ecx
; X86-SKYLAKE-NEXT: orl $-16777216, %ecx # imm = 0xFF000000
; X86-SKYLAKE-NEXT: movl %ecx, (%eax)
@ -54,7 +54,7 @@ define void @fetch_r16g16_snorm_unorm8(<4 x i8>*, i8*, i32, i32, { [2048 x i32],
; X64-SKYLAKE-NEXT: vpxor %xmm1, %xmm1, %xmm1
; X64-SKYLAKE-NEXT: vpmaxsd %xmm1, %xmm0, %xmm0
; X64-SKYLAKE-NEXT: vpsrld $7, %xmm0, %xmm0
; X64-SKYLAKE-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4],zero,zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u]
; X64-SKYLAKE-NEXT: vpshufb {{.*#+}} xmm0 = xmm0[0,4],zero,xmm0[u,u,u,u,u,u,u,u,u,u,u,u,u]
; X64-SKYLAKE-NEXT: vmovd %xmm0, %eax
; X64-SKYLAKE-NEXT: orl $-16777216, %eax # imm = 0xFF000000
; X64-SKYLAKE-NEXT: movl %eax, (%rdi)