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[X86] In shrinkAndImmediate, place the new constant into the topological sort.

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Revert the change to use APInt::isSignedIntN from
5ff5cf8e057782e3e648ecf5ccf1d9990b53ee90.

Its clear that the games we were playing to avoid the topological
sort aren't working. So just fix it once and for all.

Fixes PR48888.
This commit is contained in:
Craig Topper 2021-01-26 11:28:25 -08:00
parent f11e7efb47
commit 60dd07a304
3 changed files with 40 additions and 3 deletions
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3
lib/Target/X86/X86ISelDAGToDAG.cpp
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@ -617,7 +617,7 @@ X86DAGToDAGISel::IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const {
// best of both worlds. // best of both worlds.
if (U->getOpcode() == ISD::AND && if (U->getOpcode() == ISD::AND &&
Imm->getAPIntValue().getBitWidth() == 64 && Imm->getAPIntValue().getBitWidth() == 64 &&
Imm->getAPIntValue().isSignedIntN(32)) Imm->getAPIntValue().isIntN(32))
return false; return false;
// If this really a zext_inreg that can be represented with a movzx // If this really a zext_inreg that can be represented with a movzx
@ -4282,6 +4282,7 @@ bool X86DAGToDAGISel::shrinkAndImmediate(SDNode *And) {
// A negative mask allows a smaller encoding. Create a new 'and' node. // A negative mask allows a smaller encoding. Create a new 'and' node.
SDValue NewMask = CurDAG->getConstant(NegMaskVal, SDLoc(And), VT); SDValue NewMask = CurDAG->getConstant(NegMaskVal, SDLoc(And), VT);
insertDAGNode(*CurDAG, SDValue(And, 0), NewMask);
SDValue NewAnd = CurDAG->getNode(ISD::AND, SDLoc(And), VT, And0, NewMask); SDValue NewAnd = CurDAG->getNode(ISD::AND, SDLoc(And), VT, And0, NewMask);
ReplaceNode(And, NewAnd.getNode()); ReplaceNode(And, NewAnd.getNode());
SelectCode(NewAnd.getNode()); SelectCode(NewAnd.getNode());

4
test/CodeGen/X86/pr48458.ll
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@ -4,8 +4,8 @@
define i1 @foo(i64* %0) { define i1 @foo(i64* %0) {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %top ; CHECK: # %bb.0: # %top
; CHECK-NEXT: movq (%rdi), %rax ; CHECK-NEXT: movq $-2147483648, %rax # imm = 0x80000000
; CHECK-NEXT: andq $-2147483648, %rax # imm = 0x80000000 ; CHECK-NEXT: testq %rax, (%rdi)
; CHECK-NEXT: sete %al ; CHECK-NEXT: sete %al
; CHECK-NEXT: retq ; CHECK-NEXT: retq
top: top:

36
test/CodeGen/X86/pr48888.ll Normal file
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@ -0,0 +1,36 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu | FileCheck %s
define void @test(i64* %p) nounwind {
; CHECK-LABEL: test:
; CHECK: # %bb.0: # %bb
; CHECK-NEXT: movq (%rdi), %rax
; CHECK-NEXT: andl $-2, %eax
; CHECK-NEXT: cmpq $2, %rax
; CHECK-NEXT: cmpl $2, %eax
; CHECK-NEXT: retq
bb:
%i = load i64, i64* %p, align 8, !range !0
%i1 = and i64 %i, 6
%i2 = icmp eq i64 %i1, 2
br i1 %i2, label %bb3, label %bb5
bb3: ; preds = %bb
%i4 = icmp ne {}* undef, null
br label %bb5
bb5: ; preds = %bb3, %bb
br label %bb6
bb6: ; preds = %bb5
br i1 %i2, label %bb7, label %bb9
bb7: ; preds = %bb6
%i8 = getelementptr inbounds i64, i64* undef, i64 5
br label %bb9
bb9: ; preds = %bb7, %bb6
ret void
}
!0 = !{i64 0, i64 5}