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[mips] Add instruction selection patterns for blez and bgez.
llvm-svn: 182396
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@ -294,6 +294,11 @@ def : WrapperPat<tglobaltlsaddr, DADDiu, CPU64Regs>;
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defm : BrcondPats<CPU64Regs, BEQ64, BNE64, SLT64, SLTu64, SLTi64, SLTiu64,
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ZERO_64>;
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def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
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(BLEZ64 i64:$lhs, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setgt i64:$lhs, -1)), bb:$dst),
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(BGEZ64 i64:$lhs, bb:$dst)>;
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// setcc patterns
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defm : SeteqPats<CPU64Regs, SLTiu64, XOR64, SLTu64, ZERO_64>;
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defm : SetlePats<CPU64Regs, SLT64, SLTu64>;
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@ -1277,6 +1277,11 @@ def : MipsPat<(brcond RC:$cond, bb:$dst),
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defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
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def : MipsPat<(brcond (i32 (setlt i32:$lhs, 1)), bb:$dst),
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(BLEZ i32:$lhs, bb:$dst)>;
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def : MipsPat<(brcond (i32 (setgt i32:$lhs, -1)), bb:$dst),
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(BGEZ i32:$lhs, bb:$dst)>;
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// setcc patterns
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multiclass SeteqPats<RegisterClass RC, Instruction SLTiuOp, Instruction XOROp,
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Instruction SLTuOp, Register ZEROReg> {
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36
test/CodeGen/Mips/blez_bgez.ll
Normal file
36
test/CodeGen/Mips/blez_bgez.ll
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@ -0,0 +1,36 @@
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; RUN: llc -march=mipsel < %s | FileCheck %s
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; RUN: llc -march=mips64el -mcpu=mips64 < %s | FileCheck %s
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; CHECK: test_blez:
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; CHECK: blez ${{[0-9]+}}, $BB
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define void @test_blez(i32 %a) {
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entry:
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%cmp = icmp sgt i32 %a, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo1()
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br label %if.end
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if.end:
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ret void
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}
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declare void @foo1()
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; CHECK: test_bgez:
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; CHECK: bgez ${{[0-9]+}}, $BB
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define void @test_bgez(i32 %a) {
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entry:
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%cmp = icmp slt i32 %a, 0
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br i1 %cmp, label %if.then, label %if.end
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if.then:
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tail call void @foo1()
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br label %if.end
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if.end:
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ret void
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}
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@ -131,7 +131,7 @@ declare void @foo11()
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; filled.
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;
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; SUCCBB: succbbs_loop1:
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; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
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; SUCCBB: blez $5, $BB
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; SUCCBB-NEXT: addiu
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; SUCCBB: bne ${{[0-9]+}}, $zero, $BB
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; SUCCBB-NEXT: addiu
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