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[InstCombine] restrict icmp fold with 2 sdiv exact operands (PR32949)

This is the InstCombine counterpart to D32954. 
I added some comments about the code duplication in:
rL302436

Alive-based verification:
http://rise4fun.com/Alive/dPw

This is a 2nd fix for the problem reported in:
https://bugs.llvm.org/show_bug.cgi?id=32949

Differential Revision: https://reviews.llvm.org/D32970

llvm-svn: 303105
This commit is contained in:
Sanjay Patel 2017-05-15 19:27:53 +00:00
parent 6116bcb0ac
commit 612c21f9a9
2 changed files with 13 additions and 4 deletions

View File

@ -3068,16 +3068,23 @@ Instruction *InstCombiner::foldICmpBinOp(ICmpInst &I) {
}
}
break;
case Instruction::UDiv:
case Instruction::LShr:
if (I.isSigned())
if (I.isSigned() || !BO0->isExact() || !BO1->isExact())
break;
LLVM_FALLTHROUGH;
return new ICmpInst(Pred, BO0->getOperand(0), BO1->getOperand(0));
case Instruction::SDiv:
if (!I.isEquality() || !BO0->isExact() || !BO1->isExact())
break;
return new ICmpInst(Pred, BO0->getOperand(0), BO1->getOperand(0));
case Instruction::AShr:
if (!BO0->isExact() || !BO1->isExact())
break;
return new ICmpInst(Pred, BO0->getOperand(0), BO1->getOperand(0));
case Instruction::Shl: {
bool NUW = BO0->hasNoUnsignedWrap() && BO1->hasNoUnsignedWrap();
bool NSW = BO0->hasNoSignedWrap() && BO1->hasNoSignedWrap();

View File

@ -695,11 +695,13 @@ define i1 @test48(i32 %X, i32 %Y, i32 %Z) {
ret i1 %C
}
; FIXME: The above transform only works for equality predicates.
; The above transform only works for equality predicates.
define i1 @PR32949(i32 %X, i32 %Y, i32 %Z) {
; CHECK-LABEL: @PR32949(
; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 %X, %Y
; CHECK-NEXT: [[A:%.*]] = sdiv exact i32 %X, %Z
; CHECK-NEXT: [[B:%.*]] = sdiv exact i32 %Y, %Z
; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[A]], [[B]]
; CHECK-NEXT: ret i1 [[C]]
;
%A = sdiv exact i32 %X, %Z