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[AArch64][Inline-Asm] Return the 32-bit floating point register class

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when constraint "w" is used on a 32-bit operand.

This enables compiling the following code, which used to error out in
the backend:

void foo1(int a) {
  asm volatile ("sqxtn h0, %s0\n" : : "w"(a):);
}

Fixes PR28633.

llvm-svn: 276344
This commit is contained in:
Akira Hatanaka 2016-07-21 21:39:05 +00:00
parent adecc6a299
commit 614eb1eca4
2 changed files with 9 additions and 1 deletions
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2
lib/Target/AArch64/AArch64ISelLowering.cpp
View File

@ -4703,7 +4703,7 @@ AArch64TargetLowering::getRegForInlineAsmConstraint(
return std::make_pair(0U, &AArch64::GPR64commonRegClass);
return std::make_pair(0U, &AArch64::GPR32commonRegClass);
case 'w':
if (VT == MVT::f32)
if (VT.getSizeInBits() == 32)
return std::make_pair(0U, &AArch64::FPR32RegClass);
if (VT.getSizeInBits() == 64)
return std::make_pair(0U, &AArch64::FPR64RegClass);

8
test/CodeGen/AArch64/arm64-inline-asm.ll
View File

@ -246,3 +246,11 @@ define <4 x float> @test_vreg_128bit(<4 x float> %in) nounwind {
; CHECK fadd v14.4s, v0.4s, v0.4s:
ret <4 x float> %1
}
define void @test_constraint_w(i32 %a) {
; CHECK: fmov [[SREG:s[0-9]+]], {{w[0-9]+}}
; CHECK: sqxtn h0, [[SREG]]
tail call void asm sideeffect "sqxtn h0, ${0:s}\0A", "w"(i32 %a)
ret void
}