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PPC: Enable aggressive anti-dependency breaking

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Aggressive anti-dependency breaking is enabled by default for all PPC cores.
This provides a general speedup on the P7 and other platforms (among other
factors, the instruction group formation for the non-embedded PPC cores is done
during post-RA scheduling). In order to do this safely, the incompatibility
between uses of the MFOCRF instruction and anti-dependency breaking are
resolved by marking MFOCRF with hasExtraSrcRegAllocReq. As noted in the removed
FIXME, the problem was that MFOCRF's output is sensitive to the identify of the
source register, and always paired with a shift to undo this effect. Because
anti-dependency breaking is unaware of this hidden dependency of the shift
amount on the source register of the MFOCRF instruction, changing that register
must be inhibited.

Two test cases were adjusted: The SjLj test was made more insensitive to
register choices and scheduling; the saveCR test disabled anti-dependency
breaking because part of what it is testing is proper register reuse.

llvm-svn: 190587
This commit is contained in:
Hal Finkel 2013-09-12 05:24:49 +00:00
parent c56d8f90fd
commit 6164109851
5 changed files with 18 additions and 25 deletions
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1
lib/Target/PowerPC/PPCInstr64Bit.td
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@ -270,6 +270,7 @@ def MTCRF8 : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, g8rc:$rS),
"mtcrf $FXM, $rS", BrMCRX>,
PPC970_MicroCode, PPC970_Unit_CRU;
let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
def MFOCRF8: XFXForm_5a<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM),
"mfocrf $rT, $FXM", SprMFCR>,
PPC970_DGroup_First, PPC970_Unit_CRU;

1
lib/Target/PowerPC/PPCInstrInfo.td
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@ -1939,6 +1939,7 @@ def MTCRF : XFXForm_5<31, 144, (outs), (ins i32imm:$FXM, gprc:$rS),
"mtcrf $FXM, $rS", BrMCRX>,
PPC970_MicroCode, PPC970_Unit_CRU;
let hasExtraSrcRegAllocReq = 1 in // to enable post-ra anti-dep breaking.
def MFOCRF: XFXForm_5a<31, 19, (outs gprc:$rT), (ins crbitm:$FXM),
"mfocrf $rT, $FXM", SprMFCR>,
PPC970_DGroup_First, PPC970_Unit_CRU;

12
lib/Target/PowerPC/PPCSubtarget.cpp
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@ -165,14 +165,7 @@ bool PPCSubtarget::enablePostRAScheduler(
CodeGenOpt::Level OptLevel,
TargetSubtargetInfo::AntiDepBreakMode& Mode,
RegClassVector& CriticalPathRCs) const {
// FIXME: It would be best to use TargetSubtargetInfo::ANTIDEP_ALL here,
// but we can't because we can't reassign the cr registers. There is a
// dependence between the cr register and the RLWINM instruction used
// to extract its value which the anti-dependency breaker can't currently
// see. Maybe we should make a late-expanded pseudo to encode this dependency.
// (the relevant code is in PPCDAGToDAGISel::SelectSETCC)
Mode = TargetSubtargetInfo::ANTIDEP_CRITICAL;
Mode = TargetSubtargetInfo::ANTIDEP_ALL;
CriticalPathRCs.clear();
@ -181,9 +174,6 @@ bool PPCSubtarget::enablePostRAScheduler(
else
CriticalPathRCs.push_back(&PPC::GPRCRegClass);
CriticalPathRCs.push_back(&PPC::F8RCRegClass);
CriticalPathRCs.push_back(&PPC::VRRCRegClass);
return OptLevel >= CodeGenOpt::Default;
}

2
test/CodeGen/PowerPC/2010-02-12-saveCR.ll
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@ -1,4 +1,4 @@
; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 | FileCheck %s
; RUN: llc < %s -mtriple=powerpc-apple-darwin -mcpu=g4 -break-anti-dependencies=none | FileCheck %s
; ModuleID = 'hh.c'
target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32"
target triple = "powerpc-apple-darwin9.6"

27
test/CodeGen/PowerPC/sjlj.ll
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@ -64,15 +64,16 @@ return: ; preds = %if.end, %if.then
; CHECK: std
; Make sure that we're not saving VRSAVE on non-Darwin:
; CHECK-NOT: mfspr
; CHECK: stfd
; CHECK: stvx
; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha
; CHECK: std 31, env_sigill@toc@l([[REG]])
; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l
; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
; CHECK: std 1, 16([[REG]])
; CHECK: std 2, 24([[REG]])
; CHECK-DAG: stfd
; CHECK-DAG: stvx
; CHECK-DAG: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha
; CHECK-DAG: std 31, env_sigill@toc@l([[REG]])
; CHECK-DAG: addi [[REGA:[0-9]+]], [[REG]], env_sigill@toc@l
; CHECK-DAG: std [[REGA]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
; CHECK-DAG: std 1, 16([[REGA]])
; CHECK-DAG: std 2, 24([[REGA]])
; CHECK: bcl 20, 31, .LBB1_1
; CHECK: li 3, 1
; CHECK: #EH_SjLj_Setup .LBB1_1
@ -134,11 +135,11 @@ return: ; preds = %if.end, %if.then
; CHECK: addis [[REG:[0-9]+]], 2, env_sigill@toc@ha
; CHECK: std 31, env_sigill@toc@l([[REG]])
; CHECK: addi [[REG]], [[REG]], env_sigill@toc@l
; CHECK: std [[REG]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
; CHECK: std 1, 16([[REG]])
; CHECK: std 2, 24([[REG]])
; CHECK: std 30, 32([[REG]])
; CHECK: addi [[REGB:[0-9]+]], [[REG]], env_sigill@toc@l
; CHECK-DAG: std [[REGB]], [[OFF:[0-9]+]](31) # 8-byte Folded Spill
; CHECK-DAG: std 1, 16([[REGB]])
; CHECK-DAG: std 2, 24([[REGB]])
; CHECK-DAG: std 30, 32([[REGB]])
; CHECK: bcl 20, 31,
; CHECK: blr