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[x86] lower calls to fmin and llvm.minnum.* using minss/minsd/minps/minpd (PR24475)
This is a follow-on to: http://reviews.llvm.org/rL255700 http://reviews.llvm.org/rL256454 http://reviews.llvm.org/rL256510 llvm-svn: 256522
This commit is contained in:
Sanjay Patel
parent
efb03dbc75
commit
61b36ff574
@ -1809,6 +1809,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
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setTargetDAGCombine(ISD::FSUB);
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setTargetDAGCombine(ISD::FNEG);
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setTargetDAGCombine(ISD::FMA);
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setTargetDAGCombine(ISD::FMINNUM);
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setTargetDAGCombine(ISD::FMAXNUM);
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setTargetDAGCombine(ISD::SUB);
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setTargetDAGCombine(ISD::LOAD);
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@ -26917,8 +26918,8 @@ static SDValue PerformFMinFMaxCombine(SDNode *N, SelectionDAG &DAG) {
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N->getOperand(0), N->getOperand(1));
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}
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static SDValue performFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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static SDValue performFMinNumFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
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const X86Subtarget *Subtarget) {
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if (Subtarget->useSoftFloat())
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return SDValue();
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@ -26926,7 +26927,6 @@ static SDValue performFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
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// should be able to lower to FMAX/FMIN alone.
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// TODO: If an operand is already known to be a NaN or not a NaN, this
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// should be an optional swap and FMAX/FMIN.
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// TODO: Allow fminnum.
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EVT VT = N->getValueType(0);
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if (!((Subtarget->hasSSE1() && (VT == MVT::f32 || VT == MVT::v4f32)) ||
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@ -26957,19 +26957,21 @@ static SDValue performFMaxNumCombine(SDNode *N, SelectionDAG &DAG,
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//
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// The SSE FP max/min instructions were not designed for this case, but rather
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// to implement:
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// Min = Op1 < Op0 ? Op1 : Op0
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// Max = Op1 > Op0 ? Op1 : Op0
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//
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// So they always return Op0 if either input is a NaN. However, we can still
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// use those instructions for fmaxnum by selecting away a NaN input.
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// If either operand is NaN, the 2nd source operand (Op0) is passed through.
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SDValue Max = DAG.getNode(X86ISD::FMAX, DL, VT, Op1, Op0);
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auto MinMaxOp = N->getOpcode() == ISD::FMAXNUM ? X86ISD::FMAX : X86ISD::FMIN;
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SDValue MinOrMax = DAG.getNode(MinMaxOp, DL, VT, Op1, Op0);
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SDValue IsOp0Nan = DAG.getSetCC(DL, SetCCType , Op0, Op0, ISD::SETUO);
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// If Op0 is a NaN, select Op1. Otherwise, select the max. If both operands
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// are NaN, the NaN value of Op1 is the result.
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auto SelectOpcode = VT.isVector() ? ISD::VSELECT : ISD::SELECT;
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return DAG.getNode(SelectOpcode, DL, VT, IsOp0Nan, Op1, Max);
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return DAG.getNode(SelectOpcode, DL, VT, IsOp0Nan, Op1, MinOrMax);
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}
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/// Do target-specific dag combines on X86ISD::FAND nodes.
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@ -27831,7 +27833,9 @@ SDValue X86TargetLowering::PerformDAGCombine(SDNode *N,
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case X86ISD::FOR: return PerformFORCombine(N, DAG, Subtarget);
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case X86ISD::FMIN:
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case X86ISD::FMAX: return PerformFMinFMaxCombine(N, DAG);
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case ISD::FMAXNUM: return performFMaxNumCombine(N, DAG, Subtarget);
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case ISD::FMINNUM:
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case ISD::FMAXNUM: return performFMinNumFMaxNumCombine(N, DAG,
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Subtarget);
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case X86ISD::FAND: return PerformFANDCombine(N, DAG, Subtarget);
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case X86ISD::FANDN: return PerformFANDNCombine(N, DAG, Subtarget);
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case X86ISD::BT: return PerformBTCombine(N, DAG, DCI);
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@ -1,5 +1,5 @@
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx < %s | FileCheck %s
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=sse2 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
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; RUN: llc -mtriple=x86_64-unknown-unknown -mattr=avx < %s | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
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declare float @fminf(float, float)
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declare double @fmin(double, double)
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@ -14,15 +14,45 @@ declare <2 x double> @llvm.minnum.v2f64(<2 x double>, <2 x double>)
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declare <4 x double> @llvm.minnum.v4f64(<4 x double>, <4 x double>)
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declare <8 x double> @llvm.minnum.v8f64(<8 x double>, <8 x double>)
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; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.
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; CHECK-LABEL: @test_fminf
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; CHECK: jmp fminf
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; SSE: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm2, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: minss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vminss %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define float @test_fminf(float %x, float %y) {
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%z = call float @fminf(float %x, float %y) readnone
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ret float %z
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}
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; FIXME: As the vector tests show, the SSE run shouldn't need this many moves.
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; CHECK-LABEL: @test_fmin
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; CHECK: jmp fmin
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; SSE: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm2, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: minsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vminsd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define double @test_fmin(double %x, double %y) {
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%z = call double @fmin(double %x, double %y) readnone
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ret double %z
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@ -36,14 +66,40 @@ define x86_fp80 @test_fminl(x86_fp80 %x, x86_fp80 %y) {
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}
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; CHECK-LABEL: @test_intrinsic_fminf
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; CHECK: jmp fminf
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; SSE: movaps %xmm0, %xmm2
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; SSE-NEXT: cmpunordss %xmm2, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm3
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; SSE-NEXT: andps %xmm1, %xmm3
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; SSE-NEXT: minss %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm1, %xmm2
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; SSE-NEXT: orps %xmm3, %xmm2
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; SSE-NEXT: movaps %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vminss %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordss %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define float @test_intrinsic_fminf(float %x, float %y) {
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%z = call float @llvm.minnum.f32(float %x, float %y) readnone
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ret float %z
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}
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; CHECK-LABEL: @test_intrinsic_fmin
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; CHECK: jmp fmin
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; SSE: movapd %xmm0, %xmm2
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; SSE-NEXT: cmpunordsd %xmm2, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm3
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: minsd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm1, %xmm2
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; SSE-NEXT: orpd %xmm3, %xmm2
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; SSE-NEXT: movapd %xmm2, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vminsd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordsd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define double @test_intrinsic_fmin(double %x, double %y) {
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%z = call double @llvm.minnum.f64(double %x, double %y) readnone
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ret double %z
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@ -57,50 +113,117 @@ define x86_fp80 @test_intrinsic_fminl(x86_fp80 %x, x86_fp80 %y) {
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}
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; CHECK-LABEL: @test_intrinsic_fmin_v2f32
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; CHECK: callq fminf
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; CHECK: callq fminf
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; SSE: movaps %xmm1, %xmm2
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; SSE-NEXT: minps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vminps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define <2 x float> @test_intrinsic_fmin_v2f32(<2 x float> %x, <2 x float> %y) {
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%z = call <2 x float> @llvm.minnum.v2f32(<2 x float> %x, <2 x float> %y) readnone
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ret <2 x float> %z
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}
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; CHECK-LABEL: @test_intrinsic_fmin_v4f32
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; CHECK: callq fminf
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; CHECK: callq fminf
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; CHECK: callq fminf
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; CHECK: callq fminf
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; SSE: movaps %xmm1, %xmm2
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; SSE-NEXT: minps %xmm0, %xmm2
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; SSE-NEXT: cmpunordps %xmm0, %xmm0
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; SSE-NEXT: andps %xmm0, %xmm1
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; SSE-NEXT: andnps %xmm2, %xmm0
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; SSE-NEXT: orps %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vminps %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordps %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvps %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define <4 x float> @test_intrinsic_fmin_v4f32(<4 x float> %x, <4 x float> %y) {
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%z = call <4 x float> @llvm.minnum.v4f32(<4 x float> %x, <4 x float> %y) readnone
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ret <4 x float> %z
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}
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; CHECK-LABEL: @test_intrinsic_fmin_v2f64
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; CHECK: callq fmin
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; CHECK: callq fmin
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; SSE: movapd %xmm1, %xmm2
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; SSE-NEXT: minpd %xmm0, %xmm2
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm1
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; SSE-NEXT: andnpd %xmm2, %xmm0
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; SSE-NEXT: orpd %xmm1, %xmm0
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; SSE-NEXT: retq
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;
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; AVX: vminpd %xmm0, %xmm1, %xmm2
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; AVX-NEXT: vcmpunordpd %xmm0, %xmm0, %xmm0
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; AVX-NEXT: vblendvpd %xmm0, %xmm1, %xmm2, %xmm0
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; AVX-NEXT: retq
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define <2 x double> @test_intrinsic_fmin_v2f64(<2 x double> %x, <2 x double> %y) {
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%z = call <2 x double> @llvm.minnum.v2f64(<2 x double> %x, <2 x double> %y) readnone
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ret <2 x double> %z
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}
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; CHECK-LABEL: @test_intrinsic_fmin_v4f64
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; CHECK: callq fmin
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; CHECK: callq fmin
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; CHECK: callq fmin
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; CHECK: callq fmin
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; SSE: movapd %xmm2, %xmm4
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; SSE-NEXT: minpd %xmm0, %xmm4
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm2
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; SSE-NEXT: andnpd %xmm4, %xmm0
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; SSE-NEXT: orpd %xmm2, %xmm0
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; SSE-NEXT: movapd %xmm3, %xmm2
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; SSE-NEXT: minpd %xmm1, %xmm2
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; SSE-NEXT: cmpunordpd %xmm1, %xmm1
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; SSE-NEXT: andpd %xmm1, %xmm3
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; SSE-NEXT: andnpd %xmm2, %xmm1
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; SSE-NEXT: orpd %xmm3, %xmm1
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; SSE-NEXT: retq
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;
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; AVX: vminpd %ymm0, %ymm1, %ymm2
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; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vblendvpd %ymm0, %ymm1, %ymm2, %ymm0
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; AVX-NEXT: retq
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define <4 x double> @test_intrinsic_fmin_v4f64(<4 x double> %x, <4 x double> %y) {
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%z = call <4 x double> @llvm.minnum.v4f64(<4 x double> %x, <4 x double> %y) readnone
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ret <4 x double> %z
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}
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; CHECK-LABEL: @test_intrinsic_fmin_v8f64
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; CHECK: callq fmin
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; CHECK: callq fmin
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; CHECK: callq fmin
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; CHECK: callq fmin
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; CHECK: callq fmin
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; CHECK: callq fmin
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; CHECK: callq fmin
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; CHECK: callq fmin
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; SSE: movapd %xmm4, %xmm8
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; SSE-NEXT: minpd %xmm0, %xmm8
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; SSE-NEXT: cmpunordpd %xmm0, %xmm0
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; SSE-NEXT: andpd %xmm0, %xmm4
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; SSE-NEXT: andnpd %xmm8, %xmm0
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; SSE-NEXT: orpd %xmm4, %xmm0
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; SSE-NEXT: movapd %xmm5, %xmm4
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; SSE-NEXT: minpd %xmm1, %xmm4
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; SSE-NEXT: cmpunordpd %xmm1, %xmm1
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; SSE-NEXT: andpd %xmm1, %xmm5
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; SSE-NEXT: andnpd %xmm4, %xmm1
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; SSE-NEXT: orpd %xmm5, %xmm1
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; SSE-NEXT: movapd %xmm6, %xmm4
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; SSE-NEXT: minpd %xmm2, %xmm4
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; SSE-NEXT: cmpunordpd %xmm2, %xmm2
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; SSE-NEXT: andpd %xmm2, %xmm6
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; SSE-NEXT: andnpd %xmm4, %xmm2
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; SSE-NEXT: orpd %xmm6, %xmm2
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; SSE-NEXT: movapd %xmm7, %xmm4
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; SSE-NEXT: minpd %xmm3, %xmm4
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; SSE-NEXT: cmpunordpd %xmm3, %xmm3
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; SSE-NEXT: andpd %xmm3, %xmm7
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; SSE-NEXT: andnpd %xmm4, %xmm3
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; SSE-NEXT: orpd %xmm7, %xmm3
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; SSE-NEXT: retq
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;
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; AVX: vminpd %ymm0, %ymm2, %ymm4
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; AVX-NEXT: vcmpunordpd %ymm0, %ymm0, %ymm0
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; AVX-NEXT: vblendvpd %ymm0, %ymm2, %ymm4, %ymm0
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; AVX-NEXT: vminpd %ymm1, %ymm3, %ymm2
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; AVX-NEXT: vcmpunordpd %ymm1, %ymm1, %ymm1
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; AVX-NEXT: vblendvpd %ymm1, %ymm3, %ymm2, %ymm1
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; AVX-NEXT: retq
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define <8 x double> @test_intrinsic_fmin_v8f64(<8 x double> %x, <8 x double> %y) {
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%z = call <8 x double> @llvm.minnum.v8f64(<8 x double> %x, <8 x double> %y) readnone
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ret <8 x double> %z
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