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[PowerPC] Add PowerPC population count, reversed load and store related builtins and instrinsics for XL compatibility
This patch is in a series of patches to provide builtins for compatibility with the XL compiler. This patch adds the builtins and instrisics for population count, reversed load and store related operations. Reviewed By: nemanjai, #powerpc Differential revision: https://reviews.llvm.org/D106021
This commit is contained in:
Victor Huang
parent
4f5c97bb0f
commit
61ce66a632
@ -1598,6 +1598,26 @@ let TargetPrefix = "ppc" in {
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def int_ppc_maddld
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: GCCBuiltin<"__builtin_ppc_maddld">,
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Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty, llvm_i64_ty], [IntrNoMem]>;
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// load
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def int_ppc_load2r
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: GCCBuiltin<"__builtin_ppc_load2r">,
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Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
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def int_ppc_load4r
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: GCCBuiltin<"__builtin_ppc_load4r">,
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Intrinsic<[llvm_i32_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
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def int_ppc_load8r
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: GCCBuiltin<"__builtin_ppc_load8r">,
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Intrinsic<[llvm_i64_ty], [llvm_ptr_ty], [IntrReadMem, IntrArgMemOnly]>;
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// store
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def int_ppc_store2r
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: GCCBuiltin<"__builtin_ppc_store2r">,
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Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_store4r
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: GCCBuiltin<"__builtin_ppc_store4r">,
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Intrinsic<[], [llvm_i32_ty, llvm_ptr_ty], [IntrWriteMem]>;
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def int_ppc_store8r
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: GCCBuiltin<"__builtin_ppc_store8r">,
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Intrinsic<[], [llvm_i64_ty, llvm_ptr_ty], [IntrWriteMem]>;
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}
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//===----------------------------------------------------------------------===//
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@ -1790,6 +1790,10 @@ def : Pat<(i64 (int_ppc_mulhd g8rc:$a, g8rc:$b)),
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(i64 (MULHD $a, $b))>;
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def : Pat<(i64 (int_ppc_mulhdu g8rc:$a, g8rc:$b)),
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(i64 (MULHDU $a, $b))>;
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def : Pat<(int_ppc_load8r ForceXForm:$ptr),
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(LDBRX ForceXForm:$ptr)>;
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def : Pat<(int_ppc_store8r g8rc:$a, ForceXForm:$ptr),
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(STDBRX g8rc:$a, ForceXForm:$ptr)>;
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}
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let Predicates = [IsISA3_0] in {
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@ -5274,6 +5274,16 @@ def : Pat<(i32 (int_ppc_mulhw gprc:$a, gprc:$b)),
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def : Pat<(i32 (int_ppc_mulhwu gprc:$a, gprc:$b)),
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(i32 (MULHWU $a, $b))>;
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def : Pat<(int_ppc_load2r ForceXForm:$ptr),
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(LHBRX ForceXForm:$ptr)>;
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def : Pat<(int_ppc_load4r ForceXForm:$ptr),
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(LWBRX ForceXForm:$ptr)>;
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def : Pat<(int_ppc_store2r gprc:$a, ForceXForm:$ptr),
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(STHBRX gprc:$a, ForceXForm:$ptr)>;
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def : Pat<(int_ppc_store4r gprc:$a, ForceXForm:$ptr),
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(STWBRX gprc:$a, ForceXForm:$ptr)>;
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// Fast 32-bit reverse bits algorithm:
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// Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):
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// n = ((n >> 1) & 0x55555555) | ((n << 1) & 0xAAAAAAAA);
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@ -0,0 +1,37 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s
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@ull = external global i64, align 8
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@ull_addr = external global i64*, align 8
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define dso_local void @test_builtin_ppc_store8r() {
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; CHECK-LABEL: test_builtin_ppc_store8r:
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; CHECK: stdbrx 3, 0, 4
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; CHECK-NEXT: blr
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;
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entry:
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%0 = load i64, i64* @ull, align 8
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%1 = load i64*, i64** @ull_addr, align 8
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%2 = bitcast i64* %1 to i8*
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call void @llvm.ppc.store8r(i64 %0, i8* %2)
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ret void
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}
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declare void @llvm.ppc.store8r(i64, i8*)
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define dso_local i64 @test_builtin_ppc_load8r() {
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; CHECK-LABEL: test_builtin_ppc_load8r:
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; CHECK: ldbrx 3, 0, 3
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; CHECK-NEXT: blr
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entry:
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%0 = load i64*, i64** @ull_addr, align 8
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%1 = bitcast i64* %0 to i8*
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%2 = call i64 @llvm.ppc.load8r(i8* %1)
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ret i64 %2
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}
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declare i64 @llvm.ppc.load8r(i8*)
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@ -0,0 +1,87 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
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@us = external global i16, align 2
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@us_addr = external global i16*, align 8
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@ui = external global i32, align 4
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@ui_addr = external global i32*, align 8
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define dso_local void @test_builtin_ppc_store2r() {
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; CHECK-64B-LABEL: test_builtin_ppc_store2r:
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; CHECK-64B: sthbrx 3, 0, 4
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; CHECK-64B-NEXT: blr
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; CHECK-32B-LABEL: test_builtin_ppc_store2r:
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; CHECK-32B: sthbrx 3, 0, 4
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; CHECK-32B-NEXT: blr
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entry:
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%0 = load i16, i16* @us, align 2
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%conv = zext i16 %0 to i32
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%1 = load i16*, i16** @us_addr, align 8
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%2 = bitcast i16* %1 to i8*
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call void @llvm.ppc.store2r(i32 %conv, i8* %2)
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ret void
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}
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declare void @llvm.ppc.store2r(i32, i8*)
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define dso_local void @test_builtin_ppc_store4r() {
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; CHECK-64B-LABEL: test_builtin_ppc_store4r:
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; CHECK-64B: stwbrx 3, 0, 4
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; CHECK-64B-NEXT: blr
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; CHECK-32B-LABEL: test_builtin_ppc_store4r:
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; CHECK-32B: stwbrx 3, 0, 4
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; CHECK-32B-NEXT: blr
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entry:
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%0 = load i32, i32* @ui, align 4
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%1 = load i32*, i32** @ui_addr, align 8
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%2 = bitcast i32* %1 to i8*
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call void @llvm.ppc.store4r(i32 %0, i8* %2)
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ret void
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}
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declare void @llvm.ppc.store4r(i32, i8*)
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define dso_local zeroext i16 @test_builtin_ppc_load2r() {
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; CHECK-64B-LABEL: test_builtin_ppc_load2r:
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; CHECK-64B: lhbrx 3, 0, 3
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; CHECK-64B-NEXT: clrldi 3, 3, 48
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; CHECK-64B-NEXT: blr
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; CHECK-32B-LABEL: test_builtin_ppc_load2r:
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; CHECK-32B: lhbrx 3, 0, 3
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; CHECK-32B-NEXT: clrlwi 3, 3, 16
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; CHECK-32B-NEXT: blr
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entry:
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%0 = load i16*, i16** @us_addr, align 8
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%1 = bitcast i16* %0 to i8*
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%2 = call i32 @llvm.ppc.load2r(i8* %1)
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%conv = trunc i32 %2 to i16
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ret i16 %conv
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}
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declare i32 @llvm.ppc.load2r(i8*)
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define dso_local zeroext i32 @test_builtin_ppc_load4r() {
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; CHECK-64B-LABEL: test_builtin_ppc_load4r:
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; CHECK-64B: lwbrx 3, 0, 3
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; CHECK-64B-NEXT: blr
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; CHECK-32B-LABEL: test_builtin_ppc_load4r:
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; CHECK-32B: lwbrx 3, 0, 3
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; CHECK-32B-NEXT: blr
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entry:
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%0 = load i32*, i32** @ui_addr, align 8
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%1 = bitcast i32* %0 to i8*
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%2 = call i32 @llvm.ppc.load4r(i8* %1)
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ret i32 %2
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}
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declare i32 @llvm.ppc.load4r(i8*)
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51
test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll
Normal file
51
test/CodeGen/PowerPC/builtins-ppc-xlcompat-popcnt.ll
Normal file
@ -0,0 +1,51 @@
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
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; RUN: -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-64B
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
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; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-32B
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; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-aix \
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; RUN: -mcpu=pwr7 < %s | FileCheck %s --check-prefix=CHECK-64B
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@ui = external global i32, align 4
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@ull = external global i64, align 8
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define dso_local signext i32 @test_builtin_ppc_poppar4() {
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; CHECK-32B-LABEL: test_builtin_ppc_poppar4:
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; CHECK-32B: popcntw 3, 3
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; CHECK-32B-NEXT: clrlwi 3, 3, 31
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; CHECK-32B-NEXT: blr
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; CHECK-64B-LABEL: test_builtin_ppc_poppar4:
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; CHECK-64B: popcntw 3, 3
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; CHECK-64B-NEXT: clrlwi 3, 3, 31
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; CHECK-64B-NEXT: blr
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entry:
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%0 = load i32, i32* @ui, align 4
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%1 = load i32, i32* @ui, align 4
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%2 = call i32 @llvm.ctpop.i32(i32 %1)
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%3 = and i32 %2, 1
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ret i32 %3
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}
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declare i32 @llvm.ctpop.i32(i32)
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define dso_local signext i32 @test_builtin_ppc_poppar8() {
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; CHECK-32B-LABEL: test_builtin_ppc_poppar8:
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; CHECK-32B: xor 3, 3, 4
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; CHECK-32B-NEXT: popcntw 3, 3
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; CHECK-32B-NEXT: clrlwi 3, 3, 31
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; CHECK-32B-NEXT: blr
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; CHECK-64B-LABEL: test_builtin_ppc_poppar8:
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; CHECK-64B: popcntd 3, 3
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; CHECK-64B-NEXT: clrldi 3, 3, 63
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; CHECK-64B-NEXT: blr
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entry:
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%0 = load i64, i64* @ull, align 8
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%1 = load i64, i64* @ull, align 8
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%2 = call i64 @llvm.ctpop.i64(i64 %1)
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%3 = and i64 %2, 1
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%cast = trunc i64 %3 to i32
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ret i32 %cast
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}
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declare i64 @llvm.ctpop.i64(i64)
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