RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-01-31 20:51:52 +01:00
Code Issues Projects Releases Wiki Activity

[ARM] VQSUB instruction

Browse Source 
Same as VQADD, VQSUB can be selected from llvm.ssub.sat intrinsics.

Differential Revision: https://reviews.llvm.org/D68567

llvm-svn: 374377
This commit is contained in:
David Green 2019-10-10 16:34:30 +00:00
parent 733e784b92
commit 61e346ad96
3 changed files with 16 additions and 51 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -267,6 +267,8 @@ void ARMTargetLowering::addMVEVectorTypes(bool HasMVEFP) {
setOperationAction(ISD::BSWAP, VT, Legal);
setOperationAction(ISD::SADDSAT, VT, Legal);
setOperationAction(ISD::UADDSAT, VT, Legal);
setOperationAction(ISD::SSUBSAT, VT, Legal);
setOperationAction(ISD::USUBSAT, VT, Legal);
// No native support for these.
setOperationAction(ISD::UDIV, VT, Expand);

8
lib/Target/ARM/ARMInstrMVE.td
View File

@ -1567,6 +1567,14 @@ let Predicates = [HasMVEInt] in {
foreach VT = [instr.VT] in
def : Pat<(VT (saddsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
(VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
foreach instr = [MVE_VQSUBu8, MVE_VQSUBu16, MVE_VQSUBu32] in
foreach VT = [instr.VT] in
def : Pat<(VT (usubsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
(VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
foreach instr = [MVE_VQSUBs8, MVE_VQSUBs16, MVE_VQSUBs32] in
foreach VT = [instr.VT] in
def : Pat<(VT (ssubsat (VT MQPR:$Qm), (VT MQPR:$Qn))),
(VT (instr (VT MQPR:$Qm), (VT MQPR:$Qn)))>;
}

57
test/CodeGen/Thumb2/mve-saturating-arith.ll
View File

@ -191,21 +191,7 @@ entry:
define arm_aapcs_vfpcc <16 x i8> @ssub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: ssub_int8_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vsub.i8 q2, q0, q1
; CHECK-NEXT: vmov.i8 q3, #0x80
; CHECK-NEXT: vcmp.s8 lt, q2, zr
; CHECK-NEXT: vmov.i8 q4, #0x7f
; CHECK-NEXT: vpsel q3, q4, q3
; CHECK-NEXT: vcmp.s8 gt, q0, q2
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: vcmp.s8 gt, q1, zr
; CHECK-NEXT: vmrs r1, p0
; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q3, q2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: vqsub.s8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
@ -215,21 +201,7 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @ssub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: ssub_int16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vsub.i16 q2, q0, q1
; CHECK-NEXT: vmov.i16 q3, #0x8000
; CHECK-NEXT: vcmp.s16 lt, q2, zr
; CHECK-NEXT: vmvn.i16 q4, #0x8000
; CHECK-NEXT: vpsel q3, q4, q3
; CHECK-NEXT: vcmp.s16 gt, q0, q2
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: vcmp.s16 gt, q1, zr
; CHECK-NEXT: vmrs r1, p0
; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q3, q2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: vqsub.s16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
@ -239,21 +211,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @ssub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: ssub_int32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: .vsave {d8, d9}
; CHECK-NEXT: vpush {d8, d9}
; CHECK-NEXT: vsub.i32 q2, q0, q1
; CHECK-NEXT: vmov.i32 q3, #0x80000000
; CHECK-NEXT: vcmp.s32 lt, q2, zr
; CHECK-NEXT: vmvn.i32 q4, #0x80000000
; CHECK-NEXT: vpsel q3, q4, q3
; CHECK-NEXT: vcmp.s32 gt, q0, q2
; CHECK-NEXT: vmrs r0, p0
; CHECK-NEXT: vcmp.s32 gt, q1, zr
; CHECK-NEXT: vmrs r1, p0
; CHECK-NEXT: eors r0, r1
; CHECK-NEXT: vmsr p0, r0
; CHECK-NEXT: vpsel q0, q3, q2
; CHECK-NEXT: vpop {d8, d9}
; CHECK-NEXT: vqsub.s32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)
@ -358,8 +316,7 @@ entry:
define arm_aapcs_vfpcc <16 x i8> @usub_int8_t(<16 x i8> %src1, <16 x i8> %src2) {
; CHECK-LABEL: usub_int8_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmax.u8 q0, q0, q1
; CHECK-NEXT: vsub.i8 q0, q0, q1
; CHECK-NEXT: vqsub.u8 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = call <16 x i8> @llvm.usub.sat.v16i8(<16 x i8> %src1, <16 x i8> %src2)
@ -369,8 +326,7 @@ entry:
define arm_aapcs_vfpcc <8 x i16> @usub_int16_t(<8 x i16> %src1, <8 x i16> %src2) {
; CHECK-LABEL: usub_int16_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmax.u16 q0, q0, q1
; CHECK-NEXT: vsub.i16 q0, q0, q1
; CHECK-NEXT: vqsub.u16 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %src1, <8 x i16> %src2)
@ -380,8 +336,7 @@ entry:
define arm_aapcs_vfpcc <4 x i32> @usub_int32_t(<4 x i32> %src1, <4 x i32> %src2) {
; CHECK-LABEL: usub_int32_t:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: vmax.u32 q0, q0, q1
; CHECK-NEXT: vsub.i32 q0, q0, q1
; CHECK-NEXT: vqsub.u32 q0, q0, q1
; CHECK-NEXT: bx lr
entry:
%0 = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %src1, <4 x i32> %src2)