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Don't call SimplifyDemandedBits on vectors
llvm-svn: 27128
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@ -1120,7 +1120,8 @@ SDOperand DAGCombiner::visitAND(SDNode *N) {
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}
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// fold (and (sign_extend_inreg x, i16 to i32), 1) -> (and x, 1)
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// fold (and (sra)) -> (and (srl)) when possible.
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if (SimplifyDemandedBits(SDOperand(N, 0)))
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if (!MVT::isVector(VT) &&
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SimplifyDemandedBits(SDOperand(N, 0)))
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return SDOperand();
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// fold (zext_inreg (extload x)) -> (zextload x)
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if (N0.getOpcode() == ISD::EXTLOAD) {
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