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Add AVX SSE4.2 instructions
llvm-svn: 107752
This commit is contained in:
Bruno Cardoso Lopes
parent
931471d7e8
commit
6222076cd1
@ -4705,36 +4705,196 @@ def MOVNTDQArm : SS48I<0x2A, MRMSrcMem, (outs VR128:$dst), (ins i128mem:$src),
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OpSize;
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//===----------------------------------------------------------------------===//
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// SSE4.2 Instructions
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// SSE4.2 - Compare Instructions
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//===----------------------------------------------------------------------===//
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/// SS42I_binop_rm_int - Simple SSE 4.2 binary operator
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let Constraints = "$src1 = $dst" in {
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multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
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Intrinsic IntId128, bit Commutable = 0> {
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def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize {
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let isCommutable = Commutable;
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}
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def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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multiclass SS42I_binop_rm_int<bits<8> opc, string OpcodeStr,
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Intrinsic IntId128, bit Is2Addr = 1> {
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def rr : SS428I<opc, MRMSrcReg, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst, (IntId128 VR128:$src1, VR128:$src2))]>,
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OpSize;
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def rm : SS428I<opc, MRMSrcMem, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2),
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!if(Is2Addr,
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!strconcat(OpcodeStr, "\t{$src2, $dst|$dst, $src2}"),
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!strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}")),
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[(set VR128:$dst,
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(IntId128 VR128:$src1,
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(bitconvert (memopv16i8 addr:$src2))))]>, OpSize;
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}
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defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42] in
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defm VPCMPGTQ : SS42I_binop_rm_int<0x37, "vpcmpgtq", int_x86_sse42_pcmpgtq,
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0>, VEX_4V;
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let Constraints = "$src1 = $dst" in
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defm PCMPGTQ : SS42I_binop_rm_int<0x37, "pcmpgtq", int_x86_sse42_pcmpgtq>;
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def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)),
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(PCMPGTQrr VR128:$src1, VR128:$src2)>;
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def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))),
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(PCMPGTQrm VR128:$src1, addr:$src2)>;
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//===----------------------------------------------------------------------===//
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// SSE4.2 - String/text Processing Instructions
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//===----------------------------------------------------------------------===//
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// Packed Compare Implicit Length Strings, Return Mask
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let Defs = [EFLAGS], usesCustomInserter = 1 in {
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def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"#PCMPISTRM128rr PSEUDO!",
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[(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
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imm:$src3))]>, OpSize;
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def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"#PCMPISTRM128rm PSEUDO!",
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[(set VR128:$dst, (int_x86_sse42_pcmpistrm128
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VR128:$src1, (load addr:$src2), imm:$src3))]>, OpSize;
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}
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let Defs = [XMM0, EFLAGS], isAsmParserOnly = 1,
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Predicates = [HasAVX, HasSSE42] in {
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def VPCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
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def VPCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"vpcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize, VEX;
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}
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let Defs = [XMM0, EFLAGS] in {
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def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
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def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
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}
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// Packed Compare Explicit Length Strings, Return Mask
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let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
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def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"#PCMPESTRM128rr PSEUDO!",
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[(set VR128:$dst,
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(int_x86_sse42_pcmpestrm128
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VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
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def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"#PCMPESTRM128rm PSEUDO!",
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[(set VR128:$dst, (int_x86_sse42_pcmpestrm128
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VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
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OpSize;
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42],
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Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
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def VPCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
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def VPCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"vpcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize, VEX;
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}
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let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
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def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
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def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
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}
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// Packed Compare Implicit Length Strings, Return Index
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let Defs = [ECX, EFLAGS] in {
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multiclass SS42AI_pcmpistri<Intrinsic IntId128, string asm = "pcmpistri"> {
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def rr : SS42AI<0x63, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
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[(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
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(implicit EFLAGS)]>, OpSize;
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def rm : SS42AI<0x63, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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!strconcat(asm, "\t{$src3, $src2, $src1|$src1, $src2, $src3}"),
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[(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
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(implicit EFLAGS)]>, OpSize;
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}
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42] in {
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defm VPCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128, "vpcmpistri">,
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VEX;
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defm VPCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128, "vpcmpistri">,
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VEX;
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defm VPCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128, "vpcmpistri">,
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VEX;
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defm VPCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128, "vpcmpistri">,
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VEX;
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defm VPCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128, "vpcmpistri">,
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VEX;
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defm VPCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128, "vpcmpistri">,
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VEX;
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}
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defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
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defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
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defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
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defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
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defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
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defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
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// Packed Compare Explicit Length Strings, Return Index
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let Defs = [ECX, EFLAGS], Uses = [EAX, EDX] in {
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multiclass SS42AI_pcmpestri<Intrinsic IntId128, string asm = "pcmpestri"> {
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def rr : SS42AI<0x61, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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!strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
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[(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
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(implicit EFLAGS)]>, OpSize;
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def rm : SS42AI<0x61, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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!strconcat(asm, "\t{$src5, $src3, $src1|$src1, $src3, $src5}"),
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[(set ECX,
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(IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
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(implicit EFLAGS)]>, OpSize;
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}
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}
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let isAsmParserOnly = 1, Predicates = [HasAVX, HasSSE42] in {
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defm VPCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128, "vpcmpestri">,
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VEX;
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defm VPCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128, "vpcmpestri">,
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VEX;
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defm VPCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128, "vpcmpestri">,
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VEX;
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defm VPCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128, "vpcmpestri">,
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VEX;
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defm VPCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128, "vpcmpestri">,
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VEX;
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defm VPCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128, "vpcmpestri">,
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VEX;
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}
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defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
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defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
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defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
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defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
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defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
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defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
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//===----------------------------------------------------------------------===//
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// SSE4.2 - CRC Instructions
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//===----------------------------------------------------------------------===//
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// No CRC instructions have AVX equivalents
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// crc intrinsic instruction
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// This set of instructions are only rm, the only difference is the size
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// of r and m.
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@ -4802,101 +4962,6 @@ let Constraints = "$src1 = $dst" in {
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REX_W;
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}
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// String/text processing instructions.
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let Defs = [EFLAGS], usesCustomInserter = 1 in {
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def PCMPISTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"#PCMPISTRM128rr PSEUDO!",
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[(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, VR128:$src2,
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imm:$src3))]>, OpSize;
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def PCMPISTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"#PCMPISTRM128rm PSEUDO!",
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[(set VR128:$dst, (int_x86_sse42_pcmpistrm128 VR128:$src1, (load addr:$src2),
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imm:$src3))]>, OpSize;
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}
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let Defs = [XMM0, EFLAGS] in {
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def PCMPISTRM128rr : SS42AI<0x62, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
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def PCMPISTRM128rm : SS42AI<0x62, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"pcmpistrm\t{$src3, $src2, $src1|$src1, $src2, $src3}", []>, OpSize;
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}
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let Defs = [EFLAGS], Uses = [EAX, EDX], usesCustomInserter = 1 in {
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def PCMPESTRM128REG : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"#PCMPESTRM128rr PSEUDO!",
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[(set VR128:$dst,
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(int_x86_sse42_pcmpestrm128
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VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5))]>, OpSize;
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def PCMPESTRM128MEM : SS42AI<0, Pseudo, (outs VR128:$dst),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"#PCMPESTRM128rm PSEUDO!",
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[(set VR128:$dst, (int_x86_sse42_pcmpestrm128
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VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5))]>,
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OpSize;
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}
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let Defs = [XMM0, EFLAGS], Uses = [EAX, EDX] in {
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def PCMPESTRM128rr : SS42AI<0x60, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
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def PCMPESTRM128rm : SS42AI<0x60, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"pcmpestrm\t{$src5, $src3, $src1|$src1, $src3, $src5}", []>, OpSize;
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}
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let Defs = [ECX, EFLAGS] in {
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multiclass SS42AI_pcmpistri<Intrinsic IntId128> {
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def rr : SS42AI<0x63, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src2, i8imm:$src3),
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"pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[(set ECX, (IntId128 VR128:$src1, VR128:$src2, imm:$src3)),
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(implicit EFLAGS)]>, OpSize;
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def rm : SS42AI<0x63, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src2, i8imm:$src3),
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"pcmpistri\t{$src3, $src2, $src1|$src1, $src2, $src3}",
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[(set ECX, (IntId128 VR128:$src1, (load addr:$src2), imm:$src3)),
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(implicit EFLAGS)]>, OpSize;
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}
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}
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defm PCMPISTRI : SS42AI_pcmpistri<int_x86_sse42_pcmpistri128>;
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defm PCMPISTRIA : SS42AI_pcmpistri<int_x86_sse42_pcmpistria128>;
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defm PCMPISTRIC : SS42AI_pcmpistri<int_x86_sse42_pcmpistric128>;
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defm PCMPISTRIO : SS42AI_pcmpistri<int_x86_sse42_pcmpistrio128>;
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defm PCMPISTRIS : SS42AI_pcmpistri<int_x86_sse42_pcmpistris128>;
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defm PCMPISTRIZ : SS42AI_pcmpistri<int_x86_sse42_pcmpistriz128>;
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let Defs = [ECX, EFLAGS] in {
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let Uses = [EAX, EDX] in {
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multiclass SS42AI_pcmpestri<Intrinsic IntId128> {
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def rr : SS42AI<0x61, MRMSrcReg, (outs),
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(ins VR128:$src1, VR128:$src3, i8imm:$src5),
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"pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
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[(set ECX, (IntId128 VR128:$src1, EAX, VR128:$src3, EDX, imm:$src5)),
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(implicit EFLAGS)]>, OpSize;
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def rm : SS42AI<0x61, MRMSrcMem, (outs),
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(ins VR128:$src1, i128mem:$src3, i8imm:$src5),
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"pcmpestri\t{$src5, $src3, $src1|$src1, $src3, $src5}",
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[(set ECX,
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(IntId128 VR128:$src1, EAX, (load addr:$src3), EDX, imm:$src5)),
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(implicit EFLAGS)]>, OpSize;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
defm PCMPESTRI : SS42AI_pcmpestri<int_x86_sse42_pcmpestri128>;
|
||||
defm PCMPESTRIA : SS42AI_pcmpestri<int_x86_sse42_pcmpestria128>;
|
||||
defm PCMPESTRIC : SS42AI_pcmpestri<int_x86_sse42_pcmpestric128>;
|
||||
defm PCMPESTRIO : SS42AI_pcmpestri<int_x86_sse42_pcmpestrio128>;
|
||||
defm PCMPESTRIS : SS42AI_pcmpestri<int_x86_sse42_pcmpestris128>;
|
||||
defm PCMPESTRIZ : SS42AI_pcmpestri<int_x86_sse42_pcmpestriz128>;
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// AES-NI Instructions
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
@ -12122,3 +12122,43 @@
|
||||
// CHECK: encoding: [0xc4,0xe2,0x79,0x2a,0x10]
|
||||
vmovntdqa (%eax), %xmm2
|
||||
|
||||
// CHECK: vpcmpgtq %xmm2, %xmm5, %xmm1
|
||||
// CHECK: encoding: [0xc4,0xe2,0x51,0x37,0xca]
|
||||
vpcmpgtq %xmm2, %xmm5, %xmm1
|
||||
|
||||
// CHECK: vpcmpgtq (%eax), %xmm5, %xmm3
|
||||
// CHECK: encoding: [0xc4,0xe2,0x51,0x37,0x18]
|
||||
vpcmpgtq (%eax), %xmm5, %xmm3
|
||||
|
||||
// CHECK: vpcmpistrm $7, %xmm2, %xmm5
|
||||
// CHECK: encoding: [0xc4,0xe3,0x79,0x62,0xea,0x07]
|
||||
vpcmpistrm $7, %xmm2, %xmm5
|
||||
|
||||
// CHECK: vpcmpistrm $7, (%eax), %xmm5
|
||||
// CHECK: encoding: [0xc4,0xe3,0x79,0x62,0x28,0x07]
|
||||
vpcmpistrm $7, (%eax), %xmm5
|
||||
|
||||
// CHECK: vpcmpestrm $7, %xmm2, %xmm5
|
||||
// CHECK: encoding: [0xc4,0xe3,0x79,0x60,0xea,0x07]
|
||||
vpcmpestrm $7, %xmm2, %xmm5
|
||||
|
||||
// CHECK: vpcmpestrm $7, (%eax), %xmm5
|
||||
// CHECK: encoding: [0xc4,0xe3,0x79,0x60,0x28,0x07]
|
||||
vpcmpestrm $7, (%eax), %xmm5
|
||||
|
||||
// CHECK: vpcmpistri $7, %xmm2, %xmm5
|
||||
// CHECK: encoding: [0xc4,0xe3,0x79,0x63,0xea,0x07]
|
||||
vpcmpistri $7, %xmm2, %xmm5
|
||||
|
||||
// CHECK: vpcmpistri $7, (%eax), %xmm5
|
||||
// CHECK: encoding: [0xc4,0xe3,0x79,0x63,0x28,0x07]
|
||||
vpcmpistri $7, (%eax), %xmm5
|
||||
|
||||
// CHECK: vpcmpestri $7, %xmm2, %xmm5
|
||||
// CHECK: encoding: [0xc4,0xe3,0x79,0x61,0xea,0x07]
|
||||
vpcmpestri $7, %xmm2, %xmm5
|
||||
|
||||
// CHECK: vpcmpestri $7, (%eax), %xmm5
|
||||
// CHECK: encoding: [0xc4,0xe3,0x79,0x61,0x28,0x07]
|
||||
vpcmpestri $7, (%eax), %xmm5
|
||||
|
||||
|
||||
@ -2186,3 +2186,42 @@ pshufb CPI1_0(%rip), %xmm1
|
||||
// CHECK: encoding: [0xc4,0x62,0x79,0x2a,0x20]
|
||||
vmovntdqa (%rax), %xmm12
|
||||
|
||||
// CHECK: vpcmpgtq %xmm12, %xmm10, %xmm11
|
||||
// CHECK: encoding: [0xc4,0x42,0x29,0x37,0xdc]
|
||||
vpcmpgtq %xmm12, %xmm10, %xmm11
|
||||
|
||||
// CHECK: vpcmpgtq (%rax), %xmm10, %xmm13
|
||||
// CHECK: encoding: [0xc4,0x62,0x29,0x37,0x28]
|
||||
vpcmpgtq (%rax), %xmm10, %xmm13
|
||||
|
||||
// CHECK: vpcmpistrm $7, %xmm12, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x43,0x79,0x62,0xd4,0x07]
|
||||
vpcmpistrm $7, %xmm12, %xmm10
|
||||
|
||||
// CHECK: vpcmpistrm $7, (%rax), %xmm10
|
||||
// CHECK: encoding: [0xc4,0x63,0x79,0x62,0x10,0x07]
|
||||
vpcmpistrm $7, (%rax), %xmm10
|
||||
|
||||
// CHECK: vpcmpestrm $7, %xmm12, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x43,0x79,0x60,0xd4,0x07]
|
||||
vpcmpestrm $7, %xmm12, %xmm10
|
||||
|
||||
// CHECK: vpcmpestrm $7, (%rax), %xmm10
|
||||
// CHECK: encoding: [0xc4,0x63,0x79,0x60,0x10,0x07]
|
||||
vpcmpestrm $7, (%rax), %xmm10
|
||||
|
||||
// CHECK: vpcmpistri $7, %xmm12, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x43,0x79,0x63,0xd4,0x07]
|
||||
vpcmpistri $7, %xmm12, %xmm10
|
||||
|
||||
// CHECK: vpcmpistri $7, (%rax), %xmm10
|
||||
// CHECK: encoding: [0xc4,0x63,0x79,0x63,0x10,0x07]
|
||||
vpcmpistri $7, (%rax), %xmm10
|
||||
|
||||
// CHECK: vpcmpestri $7, %xmm12, %xmm10
|
||||
// CHECK: encoding: [0xc4,0x43,0x79,0x61,0xd4,0x07]
|
||||
vpcmpestri $7, %xmm12, %xmm10
|
||||
|
||||
// CHECK: vpcmpestri $7, (%rax), %xmm10
|
||||
// CHECK: encoding: [0xc4,0x63,0x79,0x61,0x10,0x07]
|
||||
vpcmpestri $7, (%rax), %xmm10
|
||||
|
||||
Loading…
Reference in New Issue
Block a user