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https://github.com/RPCS3/llvm-mirror.git
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[SystemZ] Pass copy-hinted regs first from getRegAllocationHints().
When computing register allocation hints for a GRX32Bit register, make sure that any of the hinted registers that are also copy hints are returned first in the list. Review: Ulrich Weigand. llvm-svn: 349037
This commit is contained in:
Jonas Paulsson
parent
cceb8ca160
commit
6239df0eb2
@ -63,6 +63,10 @@ SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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const LiveRegMatrix *Matrix) const {
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const MachineRegisterInfo *MRI = &MF.getRegInfo();
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const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
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bool BaseImplRetVal = TargetRegisterInfo::getRegAllocationHints(
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VirtReg, Order, Hints, MF, VRM, Matrix);
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if (MRI->getRegClass(VirtReg) == &SystemZ::GRX32BitRegClass) {
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SmallVector<unsigned, 8> Worklist;
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SmallSet<unsigned, 4> DoneRegs;
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@ -84,8 +88,18 @@ SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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TRI->getCommonSubClass(getRC32(FalseMO, VRM, MRI),
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getRC32(TrueMO, VRM, MRI));
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if (RC && RC != &SystemZ::GRX32BitRegClass) {
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// Pass the registers of RC as hints while making sure that if
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// any of these registers are copy hints, hint them first.
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SmallSet<unsigned, 4> CopyHints;
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CopyHints.insert(Hints.begin(), Hints.end());
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Hints.clear();
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for (MCPhysReg Reg : Order)
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if (RC->contains(Reg) && !MRI->isReserved(Reg))
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if (CopyHints.count(Reg) &&
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RC->contains(Reg) && !MRI->isReserved(Reg))
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Hints.push_back(Reg);
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for (MCPhysReg Reg : Order)
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if (!CopyHints.count(Reg) &&
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RC->contains(Reg) && !MRI->isReserved(Reg))
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Hints.push_back(Reg);
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// Return true to make these hints the only regs available to
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// RA. This may mean extra spilling but since the alternative is
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@ -102,8 +116,7 @@ SystemZRegisterInfo::getRegAllocationHints(unsigned VirtReg,
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}
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}
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return TargetRegisterInfo::getRegAllocationHints(VirtReg, Order, Hints, MF,
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VRM, Matrix);
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return BaseImplRetVal;
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}
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const MCPhysReg *
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280
test/CodeGen/SystemZ/cond-move-regalloc-hints.mir
Normal file
280
test/CodeGen/SystemZ/cond-move-regalloc-hints.mir
Normal file
@ -0,0 +1,280 @@
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# RUN: llc -mtriple=s390x-linux-gnu -mcpu=z13 -start-before=greedy %s -o - \
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# RUN: | FileCheck %s
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#
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# Test that the reg alloc hints are given in a good order that gives no more
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# than 5 LGRs in output.
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--- |
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; ModuleID = 'tc.ll'
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source_filename = "tc.ll"
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target datalayout = "E-m:e-i1:8:16-i8:8:16-i64:64-f128:64-v128:64-a:8:16-n32:64"
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target triple = "s390x-unknown-linux-gnu"
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%0 = type { i32, i32, i32, float, float, float, i8*, i32 }
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define void @fun(i32 signext %arg, i32 zeroext %arg1) #0 {
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bb:
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%tmp = sext i32 %arg to i64
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%tmp2 = tail call i8* @sre_malloc()
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%tmp4 = tail call i8* @sre_malloc()
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%tmp6 = add i32 %arg, -1
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tail call void @malloc()
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%0 = trunc i32 %arg to i2
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%1 = add i2 %0, -1
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br label %bb8
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bb8: ; preds = %bb54, %bb
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%lsr.iv6 = phi i2 [ %lsr.iv.next7, %bb54 ], [ %1, %bb ]
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%tmp9 = phi i64 [ %tmp57, %bb54 ], [ 0, %bb ]
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%tmp10 = phi i64 [ 0, %bb54 ], [ %tmp, %bb ]
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%tmp12 = sub i64 %tmp, %tmp9
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br label %bb14
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bb14: ; preds = %bb39, %bb8
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%lsr.iv8 = phi i2 [ %lsr.iv.next9, %bb39 ], [ %lsr.iv6, %bb8 ]
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%lsr.iv = phi i32 [ %lsr.iv.next, %bb39 ], [ 1, %bb8 ]
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%tmp15 = phi i64 [ 0, %bb8 ], [ %tmp19, %bb39 ]
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%tmp17 = phi i32 [ %tmp6, %bb8 ], [ %tmp35, %bb39 ]
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%tmp18 = phi i32 [ 0, %bb8 ], [ %tmp34, %bb39 ]
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%2 = bitcast i8* %tmp2 to float**
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%tmp19 = add nuw nsw i64 %tmp15, 1
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%3 = zext i2 %lsr.iv8 to i64
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%4 = mul i64 %3, -1
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%tmp21 = getelementptr inbounds float*, float** %2, i64 %tmp15
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%tmp22 = load float*, float** %tmp21
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%tmp23 = trunc i64 %tmp15 to i32
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%scevgep = getelementptr float, float* %tmp22, i64 %tmp15
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br label %bb25
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bb25: ; preds = %bb25, %bb14
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%lsr.iv10 = phi i64 [ %lsr.iv.next11, %bb25 ], [ %4, %bb14 ]
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%lsr.iv3 = phi float* [ %scevgep4, %bb25 ], [ %scevgep, %bb14 ]
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%lsr.iv1 = phi i32 [ %lsr.iv.next2, %bb25 ], [ %lsr.iv, %bb14 ]
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%tmp27 = phi i32 [ %tmp35, %bb25 ], [ %tmp17, %bb14 ]
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%tmp28 = phi i32 [ %tmp34, %bb25 ], [ %tmp18, %bb14 ]
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%scevgep5 = getelementptr float, float* %lsr.iv3, i64 1
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%tmp31 = load float, float* %scevgep5
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%tmp32 = fcmp olt float %tmp31, undef
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%tmp34 = select i1 %tmp32, i32 %lsr.iv1, i32 %tmp28
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%tmp35 = select i1 %tmp32, i32 %tmp23, i32 %tmp27
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%lsr.iv.next2 = add i32 %lsr.iv1, 1
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%scevgep4 = getelementptr float, float* %lsr.iv3, i64 1
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%lsr.iv.next11 = add i64 %lsr.iv10, 1
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%tmp38 = icmp eq i64 %lsr.iv.next11, 0
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br i1 %tmp38, label %bb39, label %bb25
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bb39: ; preds = %bb25
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%lsr.iv.next = add i32 %lsr.iv, 1
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%lsr.iv.next9 = add i2 %lsr.iv8, -1
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%tmp41 = icmp eq i64 %tmp19, %tmp10
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br i1 %tmp41, label %bb42, label %bb14
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bb42: ; preds = %bb39
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%5 = bitcast i8* %tmp4 to i32*
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%tmp43 = getelementptr inbounds i32, i32* %5, i64 undef
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%tmp44 = load i32, i32* %tmp43
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%tmp45 = sub nsw i32 %tmp44, %arg
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%tmp46 = sext i32 %tmp45 to i64
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%tmp47 = getelementptr inbounds %0, %0* null, i64 %tmp46, i32 7
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%tmp48 = load i32, i32* %tmp47
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%tmp49 = add nsw i32 0, %tmp48
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store i32 %tmp49, i32* undef
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%cond = icmp eq i32 %arg1, 0
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br i1 %cond, label %bb52, label %bb54
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bb52: ; preds = %bb42
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%tmp5312 = bitcast float* undef to float*
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br label %bb54
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bb54: ; preds = %bb42, %bb52
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%6 = bitcast i8* %tmp4 to i32*
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%tmp55 = add i32 0, %arg
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%tmp56 = getelementptr inbounds i32, i32* %6, i64 undef
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store i32 %tmp55, i32* %tmp56
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%tmp57 = add i64 %tmp9, 1
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%lsr.iv.next7 = add i2 %lsr.iv6, -1
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br label %bb8
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}
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declare i8* @sre_malloc() #0
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declare void @malloc() #0
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; Function Attrs: nounwind
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declare void @llvm.stackprotector(i8*, i8**) #1
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attributes #0 = { "target-cpu"="z13" }
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attributes #1 = { nounwind }
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...
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# CHECK: lgr
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# CHECK: lgr
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# CHECK: lgr
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# CHECK: lgr
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# CHECK: lgr
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# CHECK-NOT: lgr
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---
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name: fun
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alignment: 4
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tracksRegLiveness: true
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registers:
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- { id: 0, class: gr64bit }
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- { id: 1, class: addr64bit }
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- { id: 2, class: addr64bit }
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- { id: 3, class: gr32bit }
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- { id: 4, class: gr32bit }
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- { id: 5, class: grx32bit }
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- { id: 6, class: addr64bit }
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- { id: 7, class: gr64bit }
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- { id: 8, class: grx32bit }
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- { id: 9, class: grx32bit }
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- { id: 10, class: addr64bit }
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- { id: 11, class: grx32bit }
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- { id: 12, class: grx32bit }
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- { id: 13, class: gr64bit }
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- { id: 14, class: gr64bit }
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- { id: 15, class: grx32bit }
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- { id: 16, class: gr64bit }
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- { id: 17, class: addr64bit }
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- { id: 18, class: addr64bit }
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- { id: 19, class: grx32bit }
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- { id: 20, class: grx32bit }
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- { id: 21, class: grx32bit }
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- { id: 22, class: grx32bit }
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- { id: 23, class: grx32bit }
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- { id: 24, class: grx32bit }
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- { id: 25, class: gr64bit }
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- { id: 26, class: gr64bit }
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- { id: 27, class: grx32bit }
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- { id: 28, class: grx32bit }
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- { id: 29, class: gr64bit }
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- { id: 30, class: grx32bit }
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- { id: 31, class: gr64bit }
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- { id: 32, class: gr64bit }
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- { id: 33, class: gr32bit }
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- { id: 34, class: grx32bit }
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- { id: 35, class: gr64bit }
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- { id: 36, class: gr64bit }
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- { id: 37, class: gr64bit }
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- { id: 38, class: grx32bit }
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- { id: 39, class: gr64bit }
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- { id: 40, class: grx32bit }
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- { id: 41, class: gr64bit }
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- { id: 42, class: gr64bit }
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- { id: 43, class: gr64bit }
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- { id: 44, class: gr64bit }
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- { id: 45, class: addr64bit }
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- { id: 46, class: gr64bit }
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- { id: 47, class: fp32bit }
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- { id: 48, class: fp32bit }
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- { id: 49, class: gr32bit }
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- { id: 50, class: gr32bit }
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- { id: 51, class: gr64bit }
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- { id: 52, class: addr64bit }
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- { id: 53, class: addr64bit }
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- { id: 54, class: gr64bit }
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- { id: 55, class: gr32bit }
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- { id: 56, class: addr64bit }
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- { id: 57, class: gr64bit }
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- { id: 58, class: grx32bit }
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- { id: 59, class: grx32bit }
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- { id: 60, class: addr64bit }
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- { id: 61, class: grx32bit }
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- { id: 62, class: grx32bit }
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- { id: 63, class: addr64bit }
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- { id: 64, class: addr64bit }
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- { id: 65, class: grx32bit }
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- { id: 66, class: grx32bit }
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- { id: 67, class: grx32bit }
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liveins:
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- { reg: '$r2d', virtual-reg: '%31' }
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- { reg: '$r3d', virtual-reg: '%32' }
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frameInfo:
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hasCalls: true
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body: |
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bb.0.bb:
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liveins: $r2d, $r3d
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%32:gr64bit = COPY $r3d
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%0:gr64bit = COPY $r2d
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ADJCALLSTACKDOWN 0, 0
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CallBRASL @sre_malloc, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $r2d
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%1:addr64bit = COPY $r2d
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ADJCALLSTACKUP 0, 0
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ADJCALLSTACKDOWN 0, 0
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CallBRASL @sre_malloc, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc, implicit-def $r2d
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%2:addr64bit = COPY $r2d
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ADJCALLSTACKUP 0, 0
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%3:gr32bit = AHIMuxK %0.subreg_l32, -1, implicit-def dead $cc
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ADJCALLSTACKDOWN 0, 0
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CallBRASL @malloc, csr_systemz, implicit-def dead $r14d, implicit-def dead $cc
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ADJCALLSTACKUP 0, 0
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%55:gr32bit = AHIMuxK %0.subreg_l32, 3, implicit-def dead $cc
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%56:addr64bit = LGHI 0
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%57:gr64bit = COPY %0
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bb.1.bb8:
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%62:grx32bit = LHIMux 0
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%59:grx32bit = LHIMux 1
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undef %41.subreg_l32:gr64bit = COPY %55
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%60:addr64bit = LGHI 0
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%61:grx32bit = COPY %3
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bb.2.bb14:
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%10:addr64bit = COPY %60
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%60:addr64bit = nuw nsw LA %10, 1, $noreg
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%43:gr64bit = RISBGN undef %43, %41, 62, 191, 0
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%63:addr64bit = LCGR %43, implicit-def dead $cc
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%45:addr64bit = SLLG %10, $noreg, 3
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%64:addr64bit = SLLG %10, $noreg, 2
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%64:addr64bit = AG %64, %1, 0, %45, implicit-def dead $cc :: (load 8 from %ir.tmp21)
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%65:grx32bit = COPY %59
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bb.3.bb25:
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successors: %bb.4(0x04000000), %bb.3(0x7c000000)
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%47:fp32bit = VL32 %64, 4, $noreg :: (load 4 from %ir.scevgep5)
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%25:gr64bit = LA %64, 4, $noreg
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CEBR %47, undef %48:fp32bit, implicit-def $cc
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%62:grx32bit = LOCRMux %62, %65, 15, 4, implicit $cc
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%61:grx32bit = LOCRMux %61, %10.subreg_l32, 15, 4, implicit killed $cc
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%65:grx32bit = AHIMux %65, 1, implicit-def dead $cc
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%63:addr64bit = LA %63, 1, $noreg
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CGHI %63, 0, implicit-def $cc
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%64:addr64bit = COPY %25
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BRC 14, 6, %bb.3, implicit killed $cc
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J %bb.4
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bb.4.bb39:
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successors: %bb.5(0x04000000), %bb.2(0x7c000000)
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%59:grx32bit = AHIMux %59, 1, implicit-def dead $cc
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%41.subreg_l32:gr64bit = AHIMux %41.subreg_l32, 3, implicit-def dead $cc
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CGR %60, %57, implicit-def $cc
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BRC 14, 6, %bb.2, implicit killed $cc
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J %bb.5
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bb.5.bb42:
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successors: %bb.6(0x30000000), %bb.7(0x50000000)
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%50:gr32bit = LMux %2, 0, $noreg :: (load 4 from %ir.tmp43)
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%50:gr32bit = nsw SR %50, %0.subreg_l32, implicit-def dead $cc
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%52:addr64bit = LGFR %50
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%52:addr64bit = MGHI %52, 40
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MVC undef %53:addr64bit, 0, 4, %52, 32 :: (store 4 into `i32* undef`), (load 4 from %ir.tmp47)
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CHIMux %32.subreg_l32, 0, implicit-def $cc
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BRC 14, 6, %bb.7, implicit killed $cc
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J %bb.6
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bb.6.bb52:
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bb.7.bb54:
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STMux %0.subreg_l32, %2, 0, $noreg :: (store 4 into %ir.tmp56)
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%56:addr64bit = LA %56, 1, $noreg
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%55:gr32bit = AHIMux %55, 3, implicit-def dead $cc
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%57:gr64bit = LGHI 0
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J %bb.1
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...
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