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ARM assembly parsing and encoding for extend instructions.
Assembly parser handling for extend instruction rotate operands. Add tests for the sign extend instructions. llvm-svn: 136252
This commit is contained in:
Jim Grosbach
parent
59edfce6f7
commit
624acaffd7
@ -397,11 +397,16 @@ def rot_imm_XFORM: SDNodeXForm<imm, [{
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case 24: return CurDAG->getTargetConstant(3, MVT::i32);
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}
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}]>;
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def RotImmAsmOperand : AsmOperandClass {
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let Name = "RotImm";
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let ParserMethod = "parseRotImm";
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}
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def rot_imm : Operand<i32>, PatLeaf<(i32 imm), [{
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int32_t v = N->getZExtValue();
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return v == 8 || v == 16 || v == 24; }],
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rot_imm_XFORM> {
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let PrintMethod = "printRotImmOperand";
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let ParserMatchClass = RotImmAsmOperand;
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}
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// shift_imm: An integer that encodes a shift amount and the type of shift
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@ -124,6 +124,7 @@ class ARMAsmParser : public MCTargetAsmParser {
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}
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OperandMatchResultTy parseSetEndImm(SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*>&);
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OperandMatchResultTy parseRotImm(SmallVectorImpl<MCParsedAsmOperand*>&);
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// Asm Match Converter Methods
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bool cvtLdWriteBackRegAddrMode2(MCInst &Inst, unsigned Opcode,
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@ -187,6 +188,7 @@ class ARMOperand : public MCParsedAsmOperand {
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ShiftedRegister,
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ShiftedImmediate,
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ShifterImmediate,
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RotateImmediate,
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Token
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} Kind;
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@ -260,6 +262,9 @@ class ARMOperand : public MCParsedAsmOperand {
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unsigned SrcReg;
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unsigned ShiftImm;
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} RegShiftedImm;
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struct {
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unsigned Imm;
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} RotImm;
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};
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ARMOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
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@ -312,6 +317,9 @@ public:
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case ShiftedImmediate:
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RegShiftedImm = o.RegShiftedImm;
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break;
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case RotateImmediate:
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RotImm = o.RotImm;
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break;
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}
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}
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@ -531,6 +539,7 @@ public:
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bool isShifterImm() const { return Kind == ShifterImmediate; }
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bool isRegShiftedReg() const { return Kind == ShiftedRegister; }
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bool isRegShiftedImm() const { return Kind == ShiftedImmediate; }
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bool isRotImm() const { return Kind == RotateImmediate; }
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bool isMemMode2() const {
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if (getMemAddrMode() != ARMII::AddrMode2)
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return false;
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@ -701,6 +710,12 @@ public:
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addRegListOperands(Inst, N);
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}
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void addRotImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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// Encoded as val>>3. The printer handles display as 8, 16, 24.
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Inst.addOperand(MCOperand::CreateImm(RotImm.Imm >> 3));
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}
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void addImmOperands(MCInst &Inst, unsigned N) const {
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assert(N == 1 && "Invalid number of operands!");
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addExpr(Inst, getImm());
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@ -1008,6 +1023,14 @@ public:
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return Op;
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}
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static ARMOperand *CreateRotImm(unsigned Imm, SMLoc S, SMLoc E) {
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ARMOperand *Op = new ARMOperand(RotateImmediate);
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Op->RotImm.Imm = Imm;
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Op->StartLoc = S;
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Op->EndLoc = E;
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return Op;
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}
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static ARMOperand *
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CreateRegList(const SmallVectorImpl<std::pair<unsigned, SMLoc> > &Regs,
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SMLoc StartLoc, SMLoc EndLoc) {
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@ -1183,6 +1206,9 @@ void ARMOperand::print(raw_ostream &OS) const {
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<< ", " << ARM_AM::getSORegOffset(RegShiftedImm.ShiftImm)
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<< ">";
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break;
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case RotateImmediate:
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OS << "<ror " << " #" << (RotImm.Imm * 8) << ">";
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break;
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case RegisterList:
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case DPRRegisterList:
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case SPRRegisterList: {
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@ -1810,6 +1836,58 @@ parseShifterImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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return MatchOperand_Success;
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}
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/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
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/// of instructions. Legal values are:
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/// ror #n 'n' in {0, 8, 16, 24}
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ARMAsmParser::OperandMatchResultTy ARMAsmParser::
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parseRotImm(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
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const AsmToken &Tok = Parser.getTok();
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SMLoc S = Tok.getLoc();
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if (Tok.isNot(AsmToken::Identifier)) {
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Error(S, "rotate operator 'ror' expected");
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return MatchOperand_ParseFail;
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}
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StringRef ShiftName = Tok.getString();
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if (ShiftName != "ror" && ShiftName != "ROR") {
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Error(S, "rotate operator 'ror' expected");
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return MatchOperand_ParseFail;
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}
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Parser.Lex(); // Eat the operator.
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// A '#' and a rotate amount.
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if (Parser.getTok().isNot(AsmToken::Hash)) {
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Error(Parser.getTok().getLoc(), "'#' expected");
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return MatchOperand_ParseFail;
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}
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Parser.Lex(); // Eat hash token.
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const MCExpr *ShiftAmount;
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SMLoc E = Parser.getTok().getLoc();
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if (getParser().ParseExpression(ShiftAmount)) {
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Error(E, "malformed rotate expression");
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return MatchOperand_ParseFail;
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}
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const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
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if (!CE) {
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Error(E, "rotate amount must be an immediate");
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return MatchOperand_ParseFail;
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}
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int64_t Val = CE->getValue();
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// Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
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// normally, zero is represented in asm by omitting the rotate operand
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// entirely.
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if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
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Error(E, "'ror' rotate amount must be 8, 16, or 24");
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return MatchOperand_ParseFail;
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}
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E = Parser.getTok().getLoc();
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Operands.push_back(ARMOperand::CreateRotImm(Val, S, E));
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return MatchOperand_Success;
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}
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/// cvtLdWriteBackRegAddrMode2 - Convert parsed operands to MCInst.
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/// Needed here because the Asm Gen Matcher can't handle properly tied operands
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/// when they refer multiple MIOperands inside a single one.
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@ -1802,3 +1802,115 @@ _func:
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@ CHECK: swp r1, r2, [r3] @ encoding: [0x92,0x10,0x03,0xe1]
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@ CHECK: swp r4, r4, [r6] @ encoding: [0x94,0x40,0x06,0xe1]
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@ CHECK: swpb r5, r1, [r9] @ encoding: [0x91,0x50,0x49,0xe1]
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@------------------------------------------------------------------------------
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@ SXTAB
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@------------------------------------------------------------------------------
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sxtab r2, r3, r4
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sxtab r4, r5, r6, ror #0
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sxtablt r6, r2, r9, ror #8
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sxtab r5, r1, r4, ror #16
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sxtab r7, r8, r3, ror #24
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@ CHECK: sxtab r2, r3, r4 @ encoding: [0x74,0x20,0xa3,0xe6]
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@ CHECK: sxtab r4, r5, r6 @ encoding: [0x76,0x40,0xa5,0xe6]
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@ CHECK: sxtablt r6, r2, r9, ror #8
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@ encoding: [0x79,0x64,0xa2,0xb6]
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@ CHECK: sxtab r5, r1, r4, ror #16
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@ encoding: [0x74,0x58,0xa1,0xe6]
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@ CHECK: sxtab r7, r8, r3, ror #24
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@ encoding: [0x73,0x7c,0xa8,0xe6]
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@------------------------------------------------------------------------------
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@ SXTAB16
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@------------------------------------------------------------------------------
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sxtab16ge r0, r1, r4
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sxtab16 r6, r2, r7, ror #0
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sxtab16 r3, r5, r8, ror #8
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sxtab16 r3, r2, r1, ror #16
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sxtab16eq r1, r2, r3, ror #24
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@ CHECK: sxtab16ge r0, r1, r4 @ encoding: [0x74,0x00,0x81,0xa6]
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@ CHECK: sxtab16 r6, r2, r7 @ encoding: [0x77,0x60,0x82,0xe6]
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@ CHECK: sxtab16 r3, r5, r8, ror #8
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@ encoding: [0x78,0x34,0x85,0xe6]
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@ CHECK: sxtab16 r3, r2, r1, ror #16
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@ encoding: [0x71,0x38,0x82,0xe6]
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@ CHECK: sxtab16eq r1, r2, r3, ror #24
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@ encoding: [0x73,0x1c,0x82,0x06]
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@------------------------------------------------------------------------------
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@ SXTAH
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@------------------------------------------------------------------------------
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sxtah r1, r3, r9
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sxtahhi r6, r1, r6, ror #0
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sxtah r3, r8, r3, ror #8
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sxtahlo r2, r2, r4, ror #16
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sxtah r9, r3, r3, ror #24
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@ CHECK: sxtah r1, r3, r9 @ encoding: [0x79,0x10,0xb3,0xe6]
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@ CHECK: sxtahhi r6, r1, r6 @ encoding: [0x76,0x60,0xb1,0x86]
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@ CHECK: sxtah r3, r8, r3, ror #8
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@ encoding: [0x73,0x34,0xb8,0xe6]
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@ CHECK: sxtahlo r2, r2, r4, ror #16
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@ encoding: [0x74,0x28,0xb2,0x36]
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@ CHECK: sxtah r9, r3, r3, ror #24
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@ encoding: [0x73,0x9c,0xb3,0xe6]
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@------------------------------------------------------------------------------
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@ SXTB
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@------------------------------------------------------------------------------
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sxtbge r2, r4
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sxtb r5, r6, ror #0
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sxtb r6, r9, ror #8
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sxtbcc r5, r1, ror #16
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sxtb r8, r3, ror #24
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@ CHECK: sxtbge r2, r4 @ encoding: [0x74,0x20,0xaf,0xa6]
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@ CHECK: sxtb r5, r6 @ encoding: [0x76,0x50,0xaf,0xe6]
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@ CHECK: sxtb r6, r9, ror #8
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@ encoding: [0x79,0x64,0xaf,0xe6]
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@ CHECK: sxtblo r5, r1, ror #16
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@ encoding: [0x71,0x58,0xaf,0x36]
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@ CHECK: sxtb r8, r3, ror #24
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@ encoding: [0x73,0x8c,0xaf,0xe6]
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@------------------------------------------------------------------------------
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@ SXTB16
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@------------------------------------------------------------------------------
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sxtb16 r1, r4
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sxtb16 r6, r7, ror #0
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sxtb16cs r3, r5, ror #8
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sxtb16 r3, r1, ror #16
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sxtb16ge r2, r3, ror #24
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@ CHECK: sxtb16 r1, r4 @ encoding: [0x74,0x10,0x8f,0xe6]
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@ CHECK: sxtb16 r6, r7 @ encoding: [0x77,0x60,0x8f,0xe6]
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@ CHECK: sxtb16hs r3, r5, ror #8
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@ encoding: [0x75,0x34,0x8f,0x26]
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@ CHECK: sxtb16 r3, r1, ror #16
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@ encoding: [0x71,0x38,0x8f,0xe6]
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@ CHECK: sxtb16ge r2, r3, ror #24
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@ encoding: [0x73,0x2c,0x8f,0xa6]
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@------------------------------------------------------------------------------
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@ SXTH
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@------------------------------------------------------------------------------
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sxthne r3, r9
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sxth r1, r6, ror #0
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sxth r3, r8, ror #8
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sxthle r2, r2, ror #16
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sxth r9, r3, ror #24
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@ CHECK: sxthne r3, r9 @ encoding: [0x79,0x30,0xbf,0x16]
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@ CHECK: sxth r1, r6 @ encoding: [0x76,0x10,0xbf,0xe6]
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@ CHECK: sxth r3, r8, ror #8
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@ encoding: [0x78,0x34,0xbf,0xe6]
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@ CHECK: sxthle r2, r2, ror #16
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@ encoding: [0x72,0x28,0xbf,0xd6]
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@ CHECK: sxth r9, r3, ror #24
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@ encoding: [0x73,0x9c,0xbf,0xe6]
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@ -237,4 +237,38 @@
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: source operands must be sequential
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@ CHECK-ERRORS: strexd r6, r5, r3, [r8]
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@ CHECK-ERRORS: ^
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@ Illegal rotate operators for extend instructions
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sxtb r8, r3, #8
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sxtb r8, r3, ror 24
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sxtb r8, r3, ror #8 -
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sxtab r3, r8, r3, ror #(fred - wilma)
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sxtab r7, r8, r3, ror #25
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sxtah r9, r3, r3, ror #-8
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sxtb16ge r2, r3, lsr #24
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@ CHECK-ERRORS: error: rotate operator 'ror' expected
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@ CHECK-ERRORS: sxtb r8, r3, #8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: '#' expected
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@ CHECK-ERRORS: sxtb r8, r3, ror 24
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: unknown token in expression
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@ CHECK-ERRORS: sxtb r8, r3, ror #8 -
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: malformed rotate expression
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@ CHECK-ERRORS: sxtb r8, r3, ror #8 -
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: rotate amount must be an immediate
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@ CHECK-ERRORS: sxtab r3, r8, r3, ror #(fred - wilma)
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
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@ CHECK-ERRORS: sxtab r7, r8, r3, ror #25
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: 'ror' rotate amount must be 8, 16, or 24
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@ CHECK-ERRORS: sxtah r9, r3, r3, ror #-8
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@ CHECK-ERRORS: ^
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@ CHECK-ERRORS: error: rotate operator 'ror' expected
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@ CHECK-ERRORS: sxtb16ge r2, r3, lsr #24
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@ CHECK-ERRORS: ^
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