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R600: Fold zero/one in export instructions
Reviewed-by: Tom Stellard <thomas.stellard at amd.com> llvm-svn: 175181
This commit is contained in:
Vincent Lejeune
parent
829906263d
commit
62582e7a09
@ -303,57 +303,6 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
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using namespace llvm::Intrinsic;
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using namespace llvm::AMDGPUIntrinsic;
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static SDValue
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InsertScalarToRegisterExport(SelectionDAG &DAG, DebugLoc DL, SDNode **ExportMap,
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unsigned Slot, unsigned Channel, unsigned Inst, unsigned Type,
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SDValue Scalar, SDValue Chain) {
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if (!ExportMap[Slot]) {
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SDValue Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT,
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DL, MVT::v4f32,
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DAG.getUNDEF(MVT::v4f32),
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Scalar,
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DAG.getConstant(Channel, MVT::i32));
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unsigned Mask = 1 << Channel;
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const SDValue Ops[] = {Chain, Vector, DAG.getConstant(Inst, MVT::i32),
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DAG.getConstant(Type, MVT::i32), DAG.getConstant(Slot, MVT::i32),
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DAG.getConstant(Mask, MVT::i32)};
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SDValue Res = DAG.getNode(
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AMDGPUISD::EXPORT,
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DL,
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MVT::Other,
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Ops, 6);
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ExportMap[Slot] = Res.getNode();
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return Res;
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}
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SDNode *ExportInstruction = (SDNode *) ExportMap[Slot] ;
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SDValue PreviousVector = ExportInstruction->getOperand(1);
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SDValue Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT,
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DL, MVT::v4f32,
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PreviousVector,
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Scalar,
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DAG.getConstant(Channel, MVT::i32));
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unsigned Mask = dyn_cast<ConstantSDNode>(ExportInstruction->getOperand(5))
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->getZExtValue();
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Mask |= (1 << Channel);
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const SDValue Ops[] = {ExportInstruction->getOperand(0), Vector,
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DAG.getConstant(Inst, MVT::i32),
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DAG.getConstant(Type, MVT::i32),
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DAG.getConstant(Slot, MVT::i32),
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DAG.getConstant(Mask, MVT::i32)};
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DAG.UpdateNodeOperands(ExportInstruction,
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Ops, 6);
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return Chain;
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}
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SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
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switch (Op.getOpcode()) {
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default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
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@ -379,16 +328,19 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const
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MFI->LiveOuts.push_back(Reg);
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return DAG.getCopyToReg(Chain, Op.getDebugLoc(), Reg, Op.getOperand(2));
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}
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case AMDGPUIntrinsic::R600_store_pixel_color: {
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MachineFunction &MF = DAG.getMachineFunction();
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R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
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int64_t RegIndex = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
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SDNode **OutputsMap = MFI->Outputs;
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return InsertScalarToRegisterExport(DAG, Op.getDebugLoc(), OutputsMap,
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RegIndex / 4, RegIndex % 4, 0, 0, Op.getOperand(2),
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Chain);
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case AMDGPUIntrinsic::R600_store_swizzle: {
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const SDValue Args[8] = {
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Chain,
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Op.getOperand(2), // Export Value
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Op.getOperand(3), // ArrayBase
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Op.getOperand(4), // Type
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DAG.getConstant(0, MVT::i32), // SWZ_X
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DAG.getConstant(1, MVT::i32), // SWZ_Y
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DAG.getConstant(2, MVT::i32), // SWZ_Z
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DAG.getConstant(3, MVT::i32) // SWZ_W
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};
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return DAG.getNode(AMDGPUISD::EXPORT, Op.getDebugLoc(), Op.getValueType(),
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Args, 8);
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}
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// default for switch(IntrinsicID)
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@ -1195,7 +1147,43 @@ SDValue R600TargetLowering::PerformDAGCombine(SDNode *N,
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LHS.getOperand(2),
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LHS.getOperand(3),
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CCOpcode);
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}
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case AMDGPUISD::EXPORT: {
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SDValue Arg = N->getOperand(1);
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if (Arg.getOpcode() != ISD::BUILD_VECTOR)
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break;
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SDValue NewBldVec[4] = {
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DAG.getUNDEF(MVT::f32),
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DAG.getUNDEF(MVT::f32),
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DAG.getUNDEF(MVT::f32),
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DAG.getUNDEF(MVT::f32)
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};
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SDValue NewArgs[8] = {
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N->getOperand(0), // Chain
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SDValue(),
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N->getOperand(2), // ArrayBase
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N->getOperand(3), // Type
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N->getOperand(4), // SWZ_X
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N->getOperand(5), // SWZ_Y
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N->getOperand(6), // SWZ_Z
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N->getOperand(7) // SWZ_W
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};
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for (unsigned i = 0; i < Arg.getNumOperands(); i++) {
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if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Arg.getOperand(i))) {
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if (C->isZero()) {
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NewArgs[4 + i] = DAG.getConstant(4, MVT::i32); // SEL_0
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} else if (C->isExactlyValue(1.0)) {
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NewArgs[4 + i] = DAG.getConstant(5, MVT::i32); // SEL_0
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} else {
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NewBldVec[i] = Arg.getOperand(i);
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}
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} else {
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NewBldVec[i] = Arg.getOperand(i);
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}
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}
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DebugLoc DL = N->getDebugLoc();
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NewArgs[1] = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4f32, NewBldVec, 4);
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return DAG.getNode(AMDGPUISD::EXPORT, DL, N->getVTList(), NewArgs, 8);
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}
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}
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return SDValue();
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@ -540,7 +540,7 @@ def INTERP_LOAD_P0 : R600_1OP <0xE0, "INTERP_LOAD_P0", []>;
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// Export Instructions
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//===----------------------------------------------------------------------===//
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def ExportType : SDTypeProfile<0, 5, [SDTCisFP<0>, SDTCisInt<1>]>;
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def ExportType : SDTypeProfile<0, 7, [SDTCisFP<0>, SDTCisInt<1>]>;
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def EXPORT: SDNode<"AMDGPUISD::EXPORT", ExportType,
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[SDNPHasChain, SDNPSideEffect]>;
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@ -612,22 +612,12 @@ multiclass ExportPattern<Instruction ExportInst, bits<8> cf_inst> {
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(v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
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>;
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def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 0),
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(i32 imm:$type), (i32 imm:$arraybase), (i32 imm)),
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(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
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0, 1, 2, 3, cf_inst, 0)
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>;
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def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 1),
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(i32 imm:$type), (i32 imm:$arraybase), (i32 imm)),
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(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
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0, 1, 2, 3, cf_inst, 0)
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def : Pat<(EXPORT (v4f32 R600_Reg128:$src), (i32 imm:$base), (i32 imm:$type),
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(i32 imm:$swz_x), (i32 imm:$swz_y), (i32 imm:$swz_z), (i32 imm:$swz_w)),
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(ExportInst R600_Reg128:$src, imm:$type, imm:$base,
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imm:$swz_x, imm:$swz_y, imm:$swz_z, imm:$swz_w, cf_inst, 0)
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>;
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def : Pat<(int_R600_store_swizzle (v4f32 R600_Reg128:$src), imm:$arraybase,
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imm:$type),
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(ExportInst R600_Reg128:$src, imm:$type, imm:$arraybase,
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0, 1, 2, 3, cf_inst, 0)
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>;
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}
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multiclass SteamOutputExportPattern<Instruction ExportInst,
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@ -18,11 +18,8 @@ let TargetPrefix = "R600", isTarget = 1 in {
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Intrinsic<[llvm_float_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
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def int_R600_store_swizzle :
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Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_R600_store_stream_output :
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Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>;
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def int_R600_store_pixel_color :
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Intrinsic<[], [llvm_float_ty, llvm_i32_ty], []>;
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def int_R600_store_pixel_depth :
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Intrinsic<[], [llvm_float_ty], []>;
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def int_R600_store_pixel_stencil :
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