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Add missed mayStore flag to STREXD / t2STREXD

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llvm-svn: 148742
This commit is contained in:
Anton Korobeynikov 2012-01-23 22:57:52 +00:00
parent 860d90844c
commit 62624b5220
2 changed files with 5 additions and 6 deletions
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6
lib/Target/ARM/ARMInstrInfo.td
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@ -4273,14 +4273,14 @@ def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>; NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr), def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>; NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
} let hasExtraSrcRegAllocReq = 1 in
let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
def STREXD : AIstrex<0b01, (outs GPR:$Rd), def STREXD : AIstrex<0b01, (outs GPR:$Rd),
(ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr), (ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> { NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []> {
let DecoderMethod = "DecodeDoubleRegStore"; let DecoderMethod = "DecodeDoubleRegStore";
} }
}
def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>, def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex", []>,
Requires<[IsARM, HasV7]> { Requires<[IsARM, HasV7]> {

5
lib/Target/ARM/ARMInstrThumb2.td
View File

@ -3065,9 +3065,7 @@ def t2STREX : Thumb2I<(outs rGPR:$Rd), (ins rGPR:$Rt,
let Inst{11-8} = Rd; let Inst{11-8} = Rd;
let Inst{7-0} = addr{7-0}; let Inst{7-0} = addr{7-0};
} }
} let hasExtraSrcRegAllocReq = 1 in
let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd), def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
(ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr), (ins rGPR:$Rt, rGPR:$Rt2, addr_offset_none:$addr),
AddrModeNone, 4, NoItinerary, AddrModeNone, 4, NoItinerary,
@ -3076,6 +3074,7 @@ def t2STREXD : T2I_strex<0b11, (outs rGPR:$Rd),
bits<4> Rt2; bits<4> Rt2;
let Inst{11-8} = Rt2; let Inst{11-8} = Rt2;
} }
}
def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>, def t2CLREX : T2I<(outs), (ins), NoItinerary, "clrex", "", []>,
Requires<[IsThumb2, HasV7]> { Requires<[IsThumb2, HasV7]> {