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[AMDGPU] Remove -amdgpu-spill-sgpr-to-smem.
Summary: The implementation was never completed and never used except in tests. Reviewers: arsenm, mareko Subscribers: qcolombet, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D69163 llvm-svn: 375293
This commit is contained in:
Jay Foad
parent
46e0f8f422
commit
6298616030
@ -48,11 +48,6 @@ void SIRegisterInfo::classifyPressureSet(unsigned PSetID, unsigned Reg,
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}
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}
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static cl::opt<bool> EnableSpillSGPRToSMEM(
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"amdgpu-spill-sgpr-to-smem",
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cl::desc("Use scalar stores to spill SGPRs if supported by subtarget"),
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cl::init(false));
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static cl::opt<bool> EnableSpillSGPRToVGPR(
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"amdgpu-spill-sgpr-to-vgpr",
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cl::desc("Enable spilling VGPRs to SGPRs"),
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@ -65,14 +60,8 @@ SIRegisterInfo::SIRegisterInfo(const GCNSubtarget &ST) :
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SGPRPressureSets(getNumRegPressureSets()),
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VGPRPressureSets(getNumRegPressureSets()),
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AGPRPressureSets(getNumRegPressureSets()),
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SpillSGPRToVGPR(false),
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SpillSGPRToSMEM(false),
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SpillSGPRToVGPR(EnableSpillSGPRToVGPR),
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isWave32(ST.isWave32()) {
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if (EnableSpillSGPRToSMEM && ST.hasScalarStores())
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SpillSGPRToSMEM = true;
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else if (EnableSpillSGPRToVGPR)
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SpillSGPRToVGPR = true;
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unsigned NumRegPressureSets = getNumRegPressureSets();
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SGPRSetID = NumRegPressureSets;
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@ -759,22 +748,6 @@ void SIRegisterInfo::buildSpillLoadStore(MachineBasicBlock::iterator MI,
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}
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}
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static std::pair<unsigned, unsigned> getSpillEltSize(unsigned SuperRegSize,
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bool Store) {
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if (SuperRegSize % 16 == 0) {
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return { 16, Store ? AMDGPU::S_BUFFER_STORE_DWORDX4_SGPR :
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AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR };
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}
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if (SuperRegSize % 8 == 0) {
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return { 8, Store ? AMDGPU::S_BUFFER_STORE_DWORDX2_SGPR :
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AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR };
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}
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return { 4, Store ? AMDGPU::S_BUFFER_STORE_DWORD_SGPR :
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AMDGPU::S_BUFFER_LOAD_DWORD_SGPR};
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}
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bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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int Index,
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RegScavenger *RS,
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@ -799,38 +772,16 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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MachineFrameInfo &FrameInfo = MF->getFrameInfo();
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bool SpillToSMEM = spillSGPRToSMEM();
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if (SpillToSMEM && OnlyToVGPR)
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return false;
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Register FrameReg = getFrameRegister(*MF);
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assert(SpillToVGPR || (SuperReg != MFI->getStackPtrOffsetReg() &&
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SuperReg != MFI->getFrameOffsetReg() &&
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SuperReg != MFI->getScratchWaveOffsetReg()));
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assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
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unsigned OffsetReg = AMDGPU::M0;
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unsigned M0CopyReg = AMDGPU::NoRegister;
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if (SpillToSMEM) {
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if (RS->isRegUsed(AMDGPU::M0)) {
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M0CopyReg = RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false);
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), M0CopyReg)
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.addReg(AMDGPU::M0);
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}
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}
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unsigned ScalarStoreOp;
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unsigned EltSize = 4;
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const TargetRegisterClass *RC = getPhysRegClass(SuperReg);
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if (SpillToSMEM && isSGPRClass(RC)) {
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// XXX - if private_element_size is larger than 4 it might be useful to be
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// able to spill wider vmem spills.
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std::tie(EltSize, ScalarStoreOp) =
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getSpillEltSize(getRegSizeInBits(*RC) / 8, true);
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}
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ArrayRef<int16_t> SplitParts = getRegSplitParts(RC, EltSize);
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unsigned NumSubRegs = SplitParts.empty() ? 1 : SplitParts.size();
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@ -845,47 +796,6 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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Register SubReg =
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NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]);
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if (SpillToSMEM) {
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int64_t FrOffset = FrameInfo.getObjectOffset(Index);
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// The allocated memory size is really the wavefront size * the frame
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// index size. The widest register class is 64 bytes, so a 4-byte scratch
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// allocation is enough to spill this in a single stack object.
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//
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// FIXME: Frame size/offsets are computed earlier than this, so the extra
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// space is still unnecessarily allocated.
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unsigned Align = FrameInfo.getObjectAlignment(Index);
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MachinePointerInfo PtrInfo
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= MachinePointerInfo::getFixedStack(*MF, Index, EltSize * i);
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MachineMemOperand *MMO
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= MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore,
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EltSize, MinAlign(Align, EltSize * i));
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// SMEM instructions only support a single offset, so increment the wave
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// offset.
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int64_t Offset = (ST.getWavefrontSize() * FrOffset) + (EltSize * i);
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if (Offset != 0) {
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), OffsetReg)
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.addReg(FrameReg)
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.addImm(Offset);
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} else {
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
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.addReg(FrameReg);
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}
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BuildMI(*MBB, MI, DL, TII->get(ScalarStoreOp))
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.addReg(SubReg, getKillRegState(IsKill)) // sdata
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.addReg(MFI->getScratchRSrcReg()) // sbase
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.addReg(OffsetReg, RegState::Kill) // soff
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.addImm(0) // glc
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.addImm(0) // dlc
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.addMemOperand(MMO);
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continue;
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}
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if (SpillToVGPR) {
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SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
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@ -914,10 +824,8 @@ bool SIRegisterInfo::spillSGPR(MachineBasicBlock::iterator MI,
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return false;
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// Spill SGPR to a frame index.
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// TODO: Should VI try to spill to VGPR and then spill to SMEM?
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if (!TmpVGPR.isValid())
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TmpVGPR = RS->scavengeRegister(&AMDGPU::VGPR_32RegClass, MI, 0);
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// TODO: Should VI try to spill to VGPR and then spill to SMEM?
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MachineInstrBuilder Mov
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= BuildMI(*MBB, MI, DL, TII->get(AMDGPU::V_MOV_B32_e32), TmpVGPR)
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@ -979,82 +887,24 @@ bool SIRegisterInfo::restoreSGPR(MachineBasicBlock::iterator MI,
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const DebugLoc &DL = MI->getDebugLoc();
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Register SuperReg = MI->getOperand(0).getReg();
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bool SpillToSMEM = spillSGPRToSMEM();
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if (SpillToSMEM && OnlyToVGPR)
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return false;
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assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
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unsigned OffsetReg = AMDGPU::M0;
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unsigned M0CopyReg = AMDGPU::NoRegister;
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if (SpillToSMEM) {
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if (RS->isRegUsed(AMDGPU::M0)) {
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M0CopyReg = RS->scavengeRegister(&AMDGPU::SReg_32_XM0RegClass, MI, 0, false);
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::COPY), M0CopyReg)
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.addReg(AMDGPU::M0);
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}
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}
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unsigned EltSize = 4;
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unsigned ScalarLoadOp;
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Register FrameReg = getFrameRegister(*MF);
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const TargetRegisterClass *RC = getPhysRegClass(SuperReg);
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if (SpillToSMEM && isSGPRClass(RC)) {
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// XXX - if private_element_size is larger than 4 it might be useful to be
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// able to spill wider vmem spills.
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std::tie(EltSize, ScalarLoadOp) =
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getSpillEltSize(getRegSizeInBits(*RC) / 8, false);
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}
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ArrayRef<int16_t> SplitParts = getRegSplitParts(RC, EltSize);
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unsigned NumSubRegs = SplitParts.empty() ? 1 : SplitParts.size();
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// SubReg carries the "Kill" flag when SubReg == SuperReg.
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int64_t FrOffset = FrameInfo.getObjectOffset(Index);
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Register TmpVGPR;
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for (unsigned i = 0, e = NumSubRegs; i < e; ++i) {
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Register SubReg =
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NumSubRegs == 1 ? SuperReg : getSubReg(SuperReg, SplitParts[i]);
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if (SpillToSMEM) {
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// FIXME: Size may be > 4 but extra bytes wasted.
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unsigned Align = FrameInfo.getObjectAlignment(Index);
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MachinePointerInfo PtrInfo
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= MachinePointerInfo::getFixedStack(*MF, Index, EltSize * i);
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MachineMemOperand *MMO
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= MF->getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad,
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EltSize, MinAlign(Align, EltSize * i));
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// Add i * 4 offset
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int64_t Offset = (ST.getWavefrontSize() * FrOffset) + (EltSize * i);
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if (Offset != 0) {
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_ADD_U32), OffsetReg)
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.addReg(FrameReg)
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.addImm(Offset);
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} else {
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BuildMI(*MBB, MI, DL, TII->get(AMDGPU::S_MOV_B32), OffsetReg)
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.addReg(FrameReg);
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}
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auto MIB =
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BuildMI(*MBB, MI, DL, TII->get(ScalarLoadOp), SubReg)
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.addReg(MFI->getScratchRSrcReg()) // sbase
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.addReg(OffsetReg, RegState::Kill) // soff
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.addImm(0) // glc
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.addImm(0) // dlc
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.addMemOperand(MMO);
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if (NumSubRegs > 1 && i == 0)
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MIB.addReg(SuperReg, RegState::ImplicitDefine);
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continue;
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}
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if (SpillToVGPR) {
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SIMachineFunctionInfo::SpilledReg Spill = VGPRSpills[i];
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auto MIB =
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@ -35,7 +35,6 @@ private:
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BitVector VGPRPressureSets;
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BitVector AGPRPressureSets;
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bool SpillSGPRToVGPR;
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bool SpillSGPRToSMEM;
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bool isWave32;
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void classifyPressureSet(unsigned PSetID, unsigned Reg,
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@ -47,10 +46,6 @@ public:
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return SpillSGPRToVGPR;
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}
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bool spillSGPRToSMEM() const {
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return SpillSGPRToSMEM;
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}
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/// Return the end register initially reserved for the scratch buffer in case
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/// spilling is needed.
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unsigned reservedPrivateSegmentBufferReg(const MachineFunction &MF) const;
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@ -1,33 +0,0 @@
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSMEM -check-prefix=ALL %s
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; FIXME: SGPR-to-SMEM requires an additional SGPR always to scavenge m0
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; ALL-LABEL: {{^}}max_9_sgprs:
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; ALL: SGPRBlocks: 1
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; ALL: NumSGPRsForWavesPerEU: 9
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define amdgpu_kernel void @max_9_sgprs() #0 {
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%one = load volatile i32, i32 addrspace(4)* undef
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%two = load volatile i32, i32 addrspace(4)* undef
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%three = load volatile i32, i32 addrspace(4)* undef
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%four = load volatile i32, i32 addrspace(4)* undef
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%five = load volatile i32, i32 addrspace(4)* undef
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%six = load volatile i32, i32 addrspace(4)* undef
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%seven = load volatile i32, i32 addrspace(4)* undef
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%eight = load volatile i32, i32 addrspace(4)* undef
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%nine = load volatile i32, i32 addrspace(4)* undef
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%ten = load volatile i32, i32 addrspace(4)* undef
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call void asm sideeffect "", "s,s,s,s,s,s,s,s"(i32 %one, i32 %two, i32 %three, i32 %four, i32 %five, i32 %six, i32 %seven, i32 %eight)
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store volatile i32 %one, i32 addrspace(1)* undef
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store volatile i32 %two, i32 addrspace(1)* undef
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store volatile i32 %three, i32 addrspace(1)* undef
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store volatile i32 %four, i32 addrspace(1)* undef
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store volatile i32 %five, i32 addrspace(1)* undef
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store volatile i32 %six, i32 addrspace(1)* undef
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store volatile i32 %seven, i32 addrspace(1)* undef
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store volatile i32 %eight, i32 addrspace(1)* undef
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store volatile i32 %nine, i32 addrspace(1)* undef
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store volatile i32 %ten, i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind "amdgpu-num-sgpr"="14" }
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@ -1,10 +1,6 @@
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=TOSGPR -check-prefix=ALL %s
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; If spilling to smem, additional registers are used for the resource
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; descriptor.
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; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=TOSGPR -check-prefix=ALL %s
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; FIXME: Vectorization can increase required SGPR count beyond limit.
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; FIXME: SGPR-to-SMEM requires an additional SGPR always to scavenge m0
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; ALL-LABEL: {{^}}max_9_sgprs:
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@ -55,13 +51,6 @@ define amdgpu_kernel void @max_9_sgprs() #0 {
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; XTOSGPR: SGPRBlocks: 1
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; XTOSGPR: NumSGPRsForWavesPerEU: 16
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; XTOSMEM: s_mov_b64 s[10:11], s[2:3]
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; XTOSMEM: s_mov_b64 s[8:9], s[0:1]
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; XTOSMEM: s_mov_b32 s7, s13
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; XTOSMEM: SGPRBlocks: 1
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; XTOSMEM: NumSGPRsForWavesPerEU: 16
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;
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; This test case is disabled: When calculating the spillslot addresses AMDGPU
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; creates an extra vreg to save/restore m0 which in a point of maximum register
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; pressure would trigger an endless loop; the compiler aborts earlier with
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@ -101,10 +90,6 @@ define amdgpu_kernel void @max_9_sgprs() #0 {
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; ; swapping the order the registers are copied from what normally
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; ; happens.
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; XTOSMEM: s_mov_b32 s5, s11
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; XTOSMEM: s_add_u32 m0, s5,
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; XTOSMEM: s_buffer_store_dword vcc_lo, s[0:3], m0
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; XALL: SGPRBlocks: 2
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; XALL: NumSGPRsForWavesPerEU: 18
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;define amdgpu_kernel void @max_12_sgprs_12_input_sgprs(i32 addrspace(1)* %out1,
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@ -1,6 +1,6 @@
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; RUN: llc -O0 -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,-WavefrontSize32,+WavefrontSize64 -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -O0 -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global,-WavefrontSize32,+WavefrontSize64 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNNOOPT -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCNOPT -check-prefix=GCN %s
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@ -1,5 +1,4 @@
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SGPR %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SMEM %s
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; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SGPR %s
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; Make sure this doesn't crash.
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; ALL-LABEL: {{^}}test:
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@ -14,15 +13,6 @@
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; SGPR-NEXT: s_nop 4
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; SGPR-NEXT: buffer_store_dword v0, off, s[0:[[HI]]{{\]}}, 0
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; Make sure scratch wave offset register is correctly incremented and
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; then restored.
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; SMEM: s_add_u32 m0, s[[OFF]], 0x100{{$}}
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; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[LO]]:[[HI]]], m0 ; 16-byte Folded Spill
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; SMEM: s_add_u32 m0, s[[OFF]], 0x100{{$}}
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; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[LO]]:[[HI]]], m0 ; 16-byte Folded Reload
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; SMEM: s_dcache_wb
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; ALL: s_endpgm
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define amdgpu_kernel void @test(i32 addrspace(1)* %out, i32 %in) {
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call void asm sideeffect "", "~{s[0:7]}" ()
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@ -1,14 +1,11 @@
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; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=TOVGPR -check-prefix=GCN %s
|
||||
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -amdgpu-spill-sgpr-to-smem=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=TOVGPR -check-prefix=GCN %s
|
||||
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=1 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=TOVGPR -check-prefix=GCN %s
|
||||
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=TOVMEM -check-prefix=GCN %s
|
||||
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-spill-sgpr-to-smem=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=TOVMEM -check-prefix=GCN %s
|
||||
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -amdgpu-spill-sgpr-to-smem=1 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=TOSMEM -check-prefix=GCN %s
|
||||
; RUN: llc -O0 -amdgpu-spill-sgpr-to-vgpr=0 -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=TOVMEM -check-prefix=GCN %s
|
||||
|
||||
; XXX - Why does it like to use vcc?
|
||||
|
||||
; GCN-LABEL: {{^}}spill_m0:
|
||||
; TOSMEM: s_mov_b32 s[[LO:[0-9]+]], SCRATCH_RSRC_DWORD0
|
||||
; TOSMEM: s_mov_b32 s[[HI:[0-9]+]], 0xe80000
|
||||
|
||||
; GCN-DAG: s_cmp_lg_u32
|
||||
|
||||
@ -19,11 +16,6 @@
|
||||
; TOVMEM-DAG: v_mov_b32_e32 [[SPILL_VREG:v[0-9]+]], [[M0_COPY]]
|
||||
; TOVMEM: buffer_store_dword [[SPILL_VREG]], off, s{{\[[0-9]+:[0-9]+\]}}, s{{[0-9]+}} offset:12 ; 4-byte Folded Spill
|
||||
|
||||
; TOSMEM-DAG: s_mov_b32 [[M0_COPY:s[0-9]+]], m0
|
||||
; TOSMEM: s_add_u32 m0, s3, 0x300{{$}}
|
||||
; TOSMEM-NOT: [[M0_COPY]]
|
||||
; TOSMEM: s_buffer_store_dword [[M0_COPY]], s{{\[}}[[LO]]:[[HI]]], m0 ; 4-byte Folded Spill
|
||||
|
||||
; GCN: s_cbranch_scc1 [[ENDIF:BB[0-9]+_[0-9]+]]
|
||||
|
||||
; GCN: [[ENDIF]]:
|
||||
@ -35,11 +27,6 @@
|
||||
; TOVMEM: v_readfirstlane_b32 [[M0_RESTORE:s[0-9]+]], [[RELOAD_VREG]]
|
||||
; TOVMEM: s_mov_b32 m0, [[M0_RESTORE]]
|
||||
|
||||
; TOSMEM: s_add_u32 m0, s3, 0x300{{$}}
|
||||
; TOSMEM: s_buffer_load_dword [[M0_RESTORE:s[0-9]+]], s{{\[}}[[LO]]:[[HI]]], m0 ; 4-byte Folded Reload
|
||||
; TOSMEM-NOT: [[M0_RESTORE]]
|
||||
; TOSMEM: s_mov_b32 m0, [[M0_RESTORE]]
|
||||
|
||||
; GCN: s_add_i32 s{{[0-9]+}}, m0, 1
|
||||
define amdgpu_kernel void @spill_m0(i32 %cond, i32 addrspace(1)* %out) #0 {
|
||||
entry:
|
||||
@ -64,26 +51,6 @@ endif:
|
||||
; GCN: s_mov_b32 m0, s6
|
||||
; GCN: v_interp_mov_f32
|
||||
|
||||
; TOSMEM-NOT: s_m0
|
||||
; TOSMEM: s_add_u32 m0, s7, 0x100
|
||||
; TOSMEM-NEXT: s_buffer_store_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Spill
|
||||
; FIXME: RegScavenger::isRegUsed() always returns true if m0 is reserved, so we have to save and restore it
|
||||
; FIXME-TOSMEM-NOT: m0
|
||||
|
||||
; FIXME-TOSMEM-NOT: m0
|
||||
; TOSMEM: s_add_u32 m0, s7, 0x300
|
||||
; TOSMEM: s_buffer_store_dword s{{[0-9]+}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 4-byte Folded Spill
|
||||
; FIXME-TOSMEM-NOT: m0
|
||||
|
||||
; TOSMEM: s_mov_b64 exec,
|
||||
; TOSMEM: s_cbranch_execz
|
||||
; TOSMEM: s_branch
|
||||
|
||||
; TOSMEM: BB{{[0-9]+_[0-9]+}}:
|
||||
; TOSMEM: s_add_u32 m0, s7, 0x500
|
||||
; TOSMEM-NEXT: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Reload
|
||||
|
||||
|
||||
; GCN-NOT: v_readlane_b32 m0
|
||||
; GCN-NOT: s_buffer_store_dword m0
|
||||
; GCN-NOT: s_buffer_load_dword m0
|
||||
@ -110,101 +77,6 @@ endif: ; preds = %else, %if
|
||||
ret void
|
||||
}
|
||||
|
||||
; Force save and restore of m0 during SMEM spill
|
||||
; GCN-LABEL: {{^}}m0_unavailable_spill:
|
||||
|
||||
; GCN: ; def m0, 1
|
||||
|
||||
; GCN: s_mov_b32 m0, s2
|
||||
; GCN: v_interp_mov_f32
|
||||
|
||||
; GCN: ; clobber m0
|
||||
|
||||
; TOSMEM: s_mov_b32 vcc_hi, m0
|
||||
; TOSMEM: s_add_u32 m0, s3, 0x100
|
||||
; TOSMEM-NEXT: s_buffer_store_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Spill
|
||||
; TOSMEM: s_mov_b32 m0, vcc_hi
|
||||
|
||||
; TOSMEM: s_mov_b64 exec,
|
||||
; TOSMEM: s_cbranch_execz
|
||||
; TOSMEM: s_branch
|
||||
|
||||
; TOSMEM: BB{{[0-9]+_[0-9]+}}:
|
||||
; TOSMEM: s_add_u32 m0, s3, 0x100
|
||||
; TOSMEM-NEXT: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, m0 ; 8-byte Folded Reload
|
||||
|
||||
; GCN-NOT: v_readlane_b32 m0
|
||||
; GCN-NOT: s_buffer_store_dword m0
|
||||
; GCN-NOT: s_buffer_load_dword m0
|
||||
define amdgpu_kernel void @m0_unavailable_spill(i32 %m0.arg) #0 {
|
||||
main_body:
|
||||
%m0 = call i32 asm sideeffect "; def $0, 1", "={m0}"() #0
|
||||
%tmp = call float @llvm.amdgcn.interp.mov(i32 2, i32 0, i32 0, i32 %m0.arg)
|
||||
call void asm sideeffect "; clobber $0", "~{m0}"() #0
|
||||
%cmp = fcmp ueq float 0.000000e+00, %tmp
|
||||
br i1 %cmp, label %if, label %else
|
||||
|
||||
if: ; preds = %main_body
|
||||
store volatile i32 8, i32 addrspace(1)* undef
|
||||
br label %endif
|
||||
|
||||
else: ; preds = %main_body
|
||||
store volatile i32 11, i32 addrspace(1)* undef
|
||||
br label %endif
|
||||
|
||||
endif:
|
||||
ret void
|
||||
}
|
||||
|
||||
; GCN-LABEL: {{^}}restore_m0_lds:
|
||||
; TOSMEM: s_load_dwordx2 [[REG:s\[[0-9]+:[0-9]+\]]]
|
||||
; TOSMEM: s_cmp_eq_u32
|
||||
; FIXME: RegScavenger::isRegUsed() always returns true if m0 is reserved, so we have to save and restore it
|
||||
; FIXME-TOSMEM-NOT: m0
|
||||
; TOSMEM: s_add_u32 m0, s3, 0x100
|
||||
; TOSMEM: s_buffer_store_dword s{{[0-9]+}}, s[88:91], m0 ; 4-byte Folded Spill
|
||||
; FIXME-TOSMEM-NOT: m0
|
||||
; TOSMEM: s_add_u32 m0, s3, 0x200
|
||||
; TOSMEM: s_buffer_store_dwordx2 [[REG]], s[88:91], m0 ; 8-byte Folded Spill
|
||||
; FIXME-TOSMEM-NOT: m0
|
||||
; TOSMEM: s_cbranch_scc1
|
||||
|
||||
; TOSMEM: s_mov_b32 m0, -1
|
||||
|
||||
; TOSMEM: s_mov_b32 vcc_hi, m0
|
||||
; TOSMEM: s_add_u32 m0, s3, 0x200
|
||||
; TOSMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[88:91], m0 ; 8-byte Folded Reload
|
||||
; TOSMEM: s_mov_b32 m0, vcc_hi
|
||||
; TOSMEM: s_waitcnt lgkmcnt(0)
|
||||
|
||||
; TOSMEM: ds_write_b64
|
||||
|
||||
; FIXME-TOSMEM-NOT: m0
|
||||
; TOSMEM: s_add_u32 m0, s3, 0x100
|
||||
; TOSMEM: s_buffer_load_dword s0, s[88:91], m0 ; 4-byte Folded Reload
|
||||
; FIXME-TOSMEM-NOT: m0
|
||||
; TOSMEM: s_waitcnt lgkmcnt(0)
|
||||
; TOSMEM-NOT: m0
|
||||
; TOSMEM: s_mov_b32 m0, s0
|
||||
; TOSMEM: ; use m0
|
||||
|
||||
; TOSMEM: s_dcache_wb
|
||||
; TOSMEM: s_endpgm
|
||||
define amdgpu_kernel void @restore_m0_lds(i32 %arg) {
|
||||
%m0 = call i32 asm sideeffect "s_mov_b32 m0, 0", "={m0}"() #0
|
||||
%sval = load volatile i64, i64 addrspace(4)* undef
|
||||
%cmp = icmp eq i32 %arg, 0
|
||||
br i1 %cmp, label %ret, label %bb
|
||||
|
||||
bb:
|
||||
store volatile i64 %sval, i64 addrspace(3)* undef
|
||||
call void asm sideeffect "; use $0", "{m0}"(i32 %m0) #0
|
||||
br label %ret
|
||||
|
||||
ret:
|
||||
ret void
|
||||
}
|
||||
|
||||
declare float @llvm.amdgcn.interp.mov(i32, i32, i32, i32) #1
|
||||
declare void @llvm.amdgcn.exp.f32(i32, i32, float, float, float, float, i1, i1) #0
|
||||
declare void @llvm.amdgcn.exp.compr.v2f16(i32, i32, <2 x half>, <2 x half>, i1, i1) #0
|
||||
|
||||
@ -1,22 +0,0 @@
|
||||
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs -stop-before=prologepilog < %s
|
||||
|
||||
; Spill to SMEM clobbers M0. Check that the implicit-def dead operand is present
|
||||
; in the pseudo instructions.
|
||||
|
||||
; CHECK-LABEL: {{^}}spill_sgpr:
|
||||
; CHECK: SI_SPILL_S32_SAVE {{.*}}, implicit-def dead %m0
|
||||
; CHECK: SI_SPILL_S32_RESTORE {{.*}}, implicit-def dead %m0
|
||||
define amdgpu_kernel void @spill_sgpr(i32 addrspace(1)* %out, i32 %in) #0 {
|
||||
%sgpr = call i32 asm sideeffect "; def $0", "=s" () #0
|
||||
%cmp = icmp eq i32 %in, 0
|
||||
br i1 %cmp, label %bb0, label %ret
|
||||
|
||||
bb0:
|
||||
call void asm sideeffect "; use $0", "s"(i32 %sgpr) #0
|
||||
br label %ret
|
||||
|
||||
ret:
|
||||
ret void
|
||||
}
|
||||
|
||||
attributes #0 = { nounwind }
|
||||
@ -1,21 +1,7 @@
|
||||
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR %s
|
||||
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=1 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=SMEM %s
|
||||
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-smem=0 -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VMEM %s
|
||||
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VGPR %s
|
||||
; RUN: llc -O0 -march=amdgcn -mcpu=fiji -amdgpu-spill-sgpr-to-vgpr=0 -verify-machineinstrs < %s | FileCheck -check-prefix=ALL -check-prefix=VMEM %s
|
||||
|
||||
; ALL-LABEL: {{^}}spill_sgpr_x2:
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_store_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[8:11], m0 ; 8-byte Folded Spill
|
||||
; SMEM: s_cbranch_scc1
|
||||
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_load_dwordx2 s{{\[[0-9]+:[0-9]+\]}}, s[8:11], m0 ; 8-byte Folded Reload
|
||||
|
||||
; SMEM: s_dcache_wb
|
||||
; SMEM: s_endpgm
|
||||
|
||||
; FIXME: Should only need 4 bytes
|
||||
; SMEM: ScratchSize: 12
|
||||
|
||||
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
|
||||
@ -24,6 +10,7 @@
|
||||
; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
|
||||
; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
|
||||
|
||||
|
||||
; VMEM: buffer_store_dword
|
||||
; VMEM: buffer_store_dword
|
||||
; VMEM: s_cbranch_scc1
|
||||
@ -44,21 +31,6 @@ ret:
|
||||
}
|
||||
|
||||
; ALL-LABEL: {{^}}spill_sgpr_x3:
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_store_dword s
|
||||
; SMEM: s_buffer_store_dword s
|
||||
; SMEM: s_buffer_store_dword s
|
||||
; SMEM: s_cbranch_scc1
|
||||
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_load_dword s
|
||||
; SMEM: s_buffer_load_dword s
|
||||
; SMEM: s_buffer_load_dword s
|
||||
; SMEM: s_dcache_wb
|
||||
; SMEM: s_endpgm
|
||||
|
||||
; FIXME: Should only need 4 bytes
|
||||
; SMEM: ScratchSize: 16
|
||||
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
|
||||
@ -92,17 +64,6 @@ ret:
|
||||
}
|
||||
|
||||
; ALL-LABEL: {{^}}spill_sgpr_x4:
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS:[0-9]+:[0-9]+]]{{\]}}, m0 ; 16-byte Folded Spill
|
||||
; SMEM: s_cbranch_scc1
|
||||
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
|
||||
; SMEM: s_dcache_wb
|
||||
; SMEM: s_endpgm
|
||||
|
||||
; FIXME: Should only need 4 bytes
|
||||
; SMEM: ScratchSize: 20
|
||||
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
|
||||
@ -140,25 +101,6 @@ ret:
|
||||
}
|
||||
|
||||
; ALL-LABEL: {{^}}spill_sgpr_x5:
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_store_dword s
|
||||
; SMEM: s_buffer_store_dword s
|
||||
; SMEM: s_buffer_store_dword s
|
||||
; SMEM: s_buffer_store_dword s
|
||||
; SMEM: s_buffer_store_dword s
|
||||
; SMEM: s_cbranch_scc1
|
||||
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_load_dword s
|
||||
; SMEM: s_buffer_load_dword s
|
||||
; SMEM: s_buffer_load_dword s
|
||||
; SMEM: s_buffer_load_dword s
|
||||
; SMEM: s_buffer_load_dword s
|
||||
; SMEM: s_dcache_wb
|
||||
; SMEM: s_endpgm
|
||||
|
||||
; FIXME: Should only need 4 bytes
|
||||
; SMEM: ScratchSize: 24
|
||||
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
|
||||
@ -201,22 +143,6 @@ ret:
|
||||
|
||||
; ALL-LABEL: {{^}}spill_sgpr_x8:
|
||||
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS:[0-9]+:[0-9]+]]{{\]}}, m0 ; 16-byte Folded Spill
|
||||
; SMEM: s_add_u32 m0, s3, 0x110{{$}}
|
||||
; SMEM: s_buffer_store_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Spill
|
||||
; SMEM: s_cbranch_scc1
|
||||
|
||||
; SMEM: s_add_u32 m0, s3, 0x100{{$}}
|
||||
; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
|
||||
; SMEM: s_add_u32 m0, s3, 0x110{{$}}
|
||||
; SMEM: s_buffer_load_dwordx4 s{{\[[0-9]+:[0-9]+\]}}, s{{\[}}[[VALS]]{{\]}}, m0 ; 16-byte Folded Reload
|
||||
|
||||
; SMEM: s_dcache_wb
|
||||
; SMEM: s_endpgm
|
||||
|
||||
; SMEM: ScratchSize: 36
|
||||
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
|
||||
; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 2
|
||||
|
||||
Loading…
Reference in New Issue
Block a user