mirror of
https://github.com/RPCS3/llvm-mirror.git
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[ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs
This adds a number of missing Thumb1 opcodes so that the peephole optimiser can remove redundant CMP instructions. Reapplying this after the first attempt broke non-thumb1 code as the t2ADDri instruction can be used with frame indices. In thumb1 we use tADDframe. Differential Revision: https://reviews.llvm.org/D57833 llvm-svn: 354667
This commit is contained in:
David Green
parent
b059d0c690
commit
62ceaab06e
@ -2542,6 +2542,7 @@ bool ARMBaseInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
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return true;
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case ARM::CMPrr:
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case ARM::t2CMPrr:
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case ARM::tCMPr:
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SrcReg = MI.getOperand(0).getReg();
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SrcReg2 = MI.getOperand(1).getReg();
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CmpMask = ~0;
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@ -2618,28 +2619,62 @@ inline static ARMCC::CondCodes getCmpToAddCondition(ARMCC::CondCodes CC) {
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/// This function can be extended later on.
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inline static bool isRedundantFlagInstr(const MachineInstr *CmpI,
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unsigned SrcReg, unsigned SrcReg2,
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int ImmValue, const MachineInstr *OI) {
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int ImmValue, const MachineInstr *OI,
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bool &IsThumb1) {
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if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
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(OI->getOpcode() == ARM::SUBrr || OI->getOpcode() == ARM::t2SUBrr) &&
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((OI->getOperand(1).getReg() == SrcReg &&
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OI->getOperand(2).getReg() == SrcReg2) ||
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(OI->getOperand(1).getReg() == SrcReg2 &&
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OI->getOperand(2).getReg() == SrcReg)))
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OI->getOperand(2).getReg() == SrcReg))) {
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IsThumb1 = false;
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return true;
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}
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if (CmpI->getOpcode() == ARM::tCMPr && OI->getOpcode() == ARM::tSUBrr &&
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((OI->getOperand(2).getReg() == SrcReg &&
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OI->getOperand(3).getReg() == SrcReg2) ||
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(OI->getOperand(2).getReg() == SrcReg2 &&
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OI->getOperand(3).getReg() == SrcReg))) {
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IsThumb1 = true;
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return true;
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}
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if ((CmpI->getOpcode() == ARM::CMPri || CmpI->getOpcode() == ARM::t2CMPri) &&
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(OI->getOpcode() == ARM::SUBri || OI->getOpcode() == ARM::t2SUBri) &&
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OI->getOperand(1).getReg() == SrcReg &&
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OI->getOperand(2).getImm() == ImmValue)
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OI->getOperand(2).getImm() == ImmValue) {
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IsThumb1 = false;
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return true;
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}
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if (CmpI->getOpcode() == ARM::tCMPi8 &&
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(OI->getOpcode() == ARM::tSUBi8 || OI->getOpcode() == ARM::tSUBi3) &&
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OI->getOperand(2).getReg() == SrcReg &&
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OI->getOperand(3).getImm() == ImmValue) {
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IsThumb1 = true;
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return true;
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}
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if ((CmpI->getOpcode() == ARM::CMPrr || CmpI->getOpcode() == ARM::t2CMPrr) &&
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(OI->getOpcode() == ARM::ADDrr || OI->getOpcode() == ARM::t2ADDrr ||
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OI->getOpcode() == ARM::ADDri || OI->getOpcode() == ARM::t2ADDri) &&
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OI->getOperand(0).isReg() && OI->getOperand(1).isReg() &&
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OI->getOperand(0).getReg() == SrcReg &&
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OI->getOperand(1).getReg() == SrcReg2)
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OI->getOperand(1).getReg() == SrcReg2) {
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IsThumb1 = false;
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return true;
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}
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if (CmpI->getOpcode() == ARM::tCMPr &&
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(OI->getOpcode() == ARM::tADDi3 || OI->getOpcode() == ARM::tADDi8 ||
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OI->getOpcode() == ARM::tADDrr) &&
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OI->getOperand(0).getReg() == SrcReg &&
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OI->getOperand(2).getReg() == SrcReg2) {
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IsThumb1 = true;
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return true;
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}
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return false;
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}
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@ -2756,7 +2791,8 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
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// For CMPri w/ CmpValue != 0, a SubAdd may still be a candidate.
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// Thus we cannot return here.
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if (CmpInstr.getOpcode() == ARM::CMPri ||
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CmpInstr.getOpcode() == ARM::t2CMPri)
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CmpInstr.getOpcode() == ARM::t2CMPri ||
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CmpInstr.getOpcode() == ARM::tCMPi8)
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MI = nullptr;
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else
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return false;
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@ -2800,11 +2836,13 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
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// Check that CPSR isn't set between the comparison instruction and the one we
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// want to change. At the same time, search for SubAdd.
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const TargetRegisterInfo *TRI = &getRegisterInfo();
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bool SubAddIsThumb1 = false;
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do {
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const MachineInstr &Instr = *--I;
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// Check whether CmpInstr can be made redundant by the current instruction.
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if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &Instr)) {
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if (isRedundantFlagInstr(&CmpInstr, SrcReg, SrcReg2, CmpValue, &Instr,
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SubAddIsThumb1)) {
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SubAdd = &*I;
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break;
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}
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@ -2828,7 +2866,7 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
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// If we found a SubAdd, use it as it will be closer to the CMP
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if (SubAdd) {
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MI = SubAdd;
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IsThumb1 = false;
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IsThumb1 = SubAddIsThumb1;
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}
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// We can't use a predicated instruction - it doesn't always write the flags.
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@ -2897,9 +2935,13 @@ bool ARMBaseInstrInfo::optimizeCompareInstr(
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// operands will be modified.
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unsigned Opc = SubAdd->getOpcode();
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bool IsSub = Opc == ARM::SUBrr || Opc == ARM::t2SUBrr ||
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Opc == ARM::SUBri || Opc == ARM::t2SUBri;
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if (!IsSub || (SrcReg2 != 0 && SubAdd->getOperand(1).getReg() == SrcReg2 &&
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SubAdd->getOperand(2).getReg() == SrcReg)) {
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Opc == ARM::SUBri || Opc == ARM::t2SUBri ||
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Opc == ARM::tSUBrr || Opc == ARM::tSUBi3 ||
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Opc == ARM::tSUBi8;
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unsigned OpI = Opc != ARM::tSUBrr ? 1 : 2;
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if (!IsSub ||
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(SrcReg2 != 0 && SubAdd->getOperand(OpI).getReg() == SrcReg2 &&
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SubAdd->getOperand(OpI + 1).getReg() == SrcReg)) {
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// VSel doesn't support condition code update.
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if (IsInstrVSel)
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return false;
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@ -2977,9 +3019,10 @@ bool ARMBaseInstrInfo::shouldSink(const MachineInstr &MI) const {
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++Next;
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unsigned SrcReg, SrcReg2;
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int CmpMask, CmpValue;
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bool IsThumb1;
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if (Next != MI.getParent()->end() &&
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analyzeCompare(*Next, SrcReg, SrcReg2, CmpMask, CmpValue) &&
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isRedundantFlagInstr(&*Next, SrcReg, SrcReg2, CmpValue, &MI))
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isRedundantFlagInstr(&*Next, SrcReg, SrcReg2, CmpValue, &MI, IsThumb1))
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return false;
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return true;
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}
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@ -38,8 +38,7 @@ define i32 @sadd_overflow(i32 %a, i32 %b) #0 {
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; ARM: movvc r[[R0]], #0
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; ARM: mov pc, lr
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; THUMBV6: adds r1, r0, r1
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; THUMBV6: cmp r1, r0
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; THUMBV6: adds r0, r0, r1
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; THUMBV6: bvc .LBB1_2
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; THUMBV7: adds r[[R2:[0-9]+]], r[[R0]], r[[R1:[0-9]+]]
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226
test/CodeGen/Thumb/peephole-cmp.mir
Normal file
226
test/CodeGen/Thumb/peephole-cmp.mir
Normal file
@ -0,0 +1,226 @@
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# RUN: llc -mtriple thumbv8m.base-none-eabi -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
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--- |
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "thumbv8m.base-none-none-eabi"
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define i32 @test_subrr(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_subrr_c(i32 %a, i32 %b) { ret i32 %a }
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define i32 @test_subri3(i32 %a) { ret i32 %a }
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define i32 @test_subri8(i32 %a) { ret i32 %a }
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define i32 @test_addrr(i32 %a) { ret i32 %a }
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define i32 @test_addri3(i32 %a) { ret i32 %a }
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define i32 @test_addri8(i32 %a) { ret i32 %a }
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...
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---
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name: test_subrr
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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- { reg: '$r1', virtual-reg: '%2' }
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body: |
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%2:tgpr = COPY $r1
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tSUBrr %2, %1, 14, $noreg
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tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %3
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: test_subrr
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# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1
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# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
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# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY1]], [[COPY0]], 14, $noreg
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# CHECK-NEXT: tBcc %bb.2, 8, $cpsr
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...
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---
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name: test_subrr_c
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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- { reg: '$r1', virtual-reg: '%2' }
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body: |
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%2:tgpr = COPY $r1
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tSUBrr %1, %2, 14, $noreg
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tCMPr %1, %2, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %3
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: test_subrr_c
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# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1
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# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
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# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBrr [[COPY0]], [[COPY1]], 14, $noreg
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# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
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...
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---
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name: test_subri3
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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body: |
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tSUBi3 %1, 1, 14, $noreg
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tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: test_subri3
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# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi3 [[COPY]], 1, 14, $noreg
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# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
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...
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---
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name: test_subri8
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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body: |
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tSUBi8 %1, 1, 14, $noreg
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tCMPi8 %1, 1, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: test_subri8
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# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tSUBi8 [[COPY]], 1, 14, $noreg
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# CHECK-NEXT: tBcc %bb.2, 3, $cpsr
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...
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---
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name: test_addrr
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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- { reg: '$r1', virtual-reg: '%2' }
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body: |
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0, $r1
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%2:tgpr = COPY $r1
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%1:tgpr = COPY $r0
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%0:tgpr, $cpsr = tADDrr %2, %1, 14, $noreg
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tCMPr %0, %2, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%3:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %3
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: test_addrr
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# CHECK: [[COPY1:%[0-9]+]]:tgpr = COPY $r1
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# CHECK-NEXT: [[COPY0:%[0-9]+]]:tgpr = COPY $r0
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# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDrr [[COPY1]], [[COPY0]], 14, $noreg
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# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
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...
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---
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name: test_addri3
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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body: |
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0
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%0:tgpr = COPY $r0
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%1:tgpr, $cpsr = tADDi3 %0, 1, 14, $noreg
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tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: test_addri3
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# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi3 [[COPY]], 1, 14, $noreg
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# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
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...
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---
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name: test_addri8
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liveins:
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- { reg: '$r0', virtual-reg: '%1' }
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body: |
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bb.0:
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successors: %bb.2(0x40000000), %bb.1(0x40000000)
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liveins: $r0
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%0:tgpr = COPY $r0
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%1:tgpr, $cpsr = tADDi8 %0, 10, 14, $noreg
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tCMPr %1, %0, 14, $noreg, implicit-def $cpsr
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tBcc %bb.2, 3, $cpsr
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tB %bb.1, 14, $noreg
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bb.1:
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$r0 = COPY %0
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tBX_RET 14, $noreg, implicit $r0
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bb.2:
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%2:tgpr, dead $cpsr = tMOVi8 0, 14, $noreg
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$r0 = COPY %2
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tBX_RET 14, $noreg, implicit $r0
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# CHECK-LABEL: name: test_addri8
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# CHECK: [[COPY:%[0-9]+]]:tgpr = COPY $r0
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# CHECK-NEXT: [[ADD:%[0-9]+]]:tgpr, $cpsr = tADDi8 [[COPY]], 10, 14, $noreg
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# CHECK-NEXT: tBcc %bb.2, 2, $cpsr
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...
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43
test/CodeGen/Thumb2/peephole-cmp.mir
Normal file
43
test/CodeGen/Thumb2/peephole-cmp.mir
Normal file
@ -0,0 +1,43 @@
|
||||
# RUN: llc -run-pass=peephole-opt -verify-machineinstrs -o - %s | FileCheck %s
|
||||
--- |
|
||||
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
|
||||
target triple = "thumbv7m-none-none-eabi"
|
||||
|
||||
define i32 @test_addir_frameindex(i32 %a) {
|
||||
%f = alloca i32
|
||||
ret i32 %a
|
||||
}
|
||||
...
|
||||
---
|
||||
name: test_addir_frameindex
|
||||
liveins:
|
||||
- { reg: '$r0', virtual-reg: '%0' }
|
||||
stack:
|
||||
- { id: 0, name: f, type: default, offset: 0, size: 1, alignment: 4,
|
||||
stack-id: 0, callee-saved-register: '', callee-saved-restored: true,
|
||||
local-offset: -4, debug-info-variable: '', debug-info-expression: '',
|
||||
debug-info-location: '' }
|
||||
body: |
|
||||
bb.0:
|
||||
successors: %bb.2(0x40000000), %bb.1(0x40000000)
|
||||
liveins: $r0
|
||||
|
||||
%0:rgpr = COPY $r0
|
||||
%1:gprnopc = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
|
||||
t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr
|
||||
t2Bcc %bb.2, 3, $cpsr
|
||||
t2B %bb.1, 14, $noreg
|
||||
|
||||
bb.1:
|
||||
$r0 = COPY %1
|
||||
tBX_RET 14, $noreg
|
||||
|
||||
bb.2:
|
||||
$r0 = COPY %0
|
||||
tBX_RET 14, $noreg
|
||||
|
||||
# CHECK-LABEL: name: test_addir_frameindex
|
||||
# CHECK: %1:gprnopc = t2ADDri %stack.0.f, 0, 14, $noreg, $noreg
|
||||
# CHECK-NEXT: t2CMPrr %1, %0, 14, $noreg, implicit-def $cpsr
|
||||
# CHECK-NEXT: t2Bcc %bb.2, 3, $cpsr
|
||||
...
|
||||
Loading…
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Reference in New Issue
Block a user