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Add missing zmovl AVX patterns which were causing crashes.

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Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689
This commit is contained in:
Chad Rosier 2011-12-15 22:11:31 +00:00
parent 65849ee22a
commit 62ebee9859
2 changed files with 14 additions and 0 deletions
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6
lib/Target/X86/X86InstrSSE.td
View File

@ -618,6 +618,9 @@ let Predicates = [HasAVX] in {
(SUBREG_TO_REG (i64 0), (SUBREG_TO_REG (i64 0),
(v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)), (v2f64 (VMOVSDrr (v2f64 (V_SET0)), FR64:$src)),
sub_xmm)>; sub_xmm)>;
def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
(v2i64 (scalar_to_vector (loadi64 addr:$src))), (i32 0)))),
(SUBREG_TO_REG (i64 0), (VMOVSDrm addr:$src), sub_sd)>;
// Move low f64 and clear high bits. // Move low f64 and clear high bits.
def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))), def : Pat<(v4f64 (X86vzmovl (v4f64 VR256:$src))),
@ -800,6 +803,9 @@ let Predicates = [HasAVX] in {
def : Pat<(v8i32 (X86vzmovl def : Pat<(v8i32 (X86vzmovl
(insert_subvector undef, (v4i32 VR128:$src), (i32 0)))), (insert_subvector undef, (v4i32 VR128:$src), (i32 0)))),
(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>; (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
def : Pat<(v4i64 (X86vzmovl
(insert_subvector undef, (v2i64 VR128:$src), (i32 0)))),
(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;
def : Pat<(v8f32 (X86vzmovl def : Pat<(v8f32 (X86vzmovl
(insert_subvector undef, (v4f32 VR128:$src), (i32 0)))), (insert_subvector undef, (v4f32 VR128:$src), (i32 0)))),
(SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>; (SUBREG_TO_REG (i32 0), (VMOVAPSrr VR128:$src), sub_xmm)>;

8
test/CodeGen/X86/2011-12-08-AVXISelBugs.ll
View File

@ -61,3 +61,11 @@ t2.exit: ; preds = %0, %loop
return: ; preds = %loop.cond return: ; preds = %loop.cond
ret void ret void
} }
define <3 x i64> @t4() nounwind {
entry:
%0 = load <2 x i64> addrspace(1)* undef, align 16
%1 = extractelement <2 x i64> %0, i32 0
%2 = insertelement <3 x i64> <i64 undef, i64 0, i64 0>, i64 %1, i32 0
ret <3 x i64> %2
}