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Add support for marking each operand as a %hh, %hm, %lm or %lo.
Represent previous bools and these ones with flags in a single byte per operand. llvm-svn: 2860
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@ -49,9 +49,10 @@ MachineInstr::SetMachineOperandVal(unsigned int i,
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{
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assert(i < operands.size());
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operands[i].Initialize(opType, _val);
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operands[i].isDef = isdef ||
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TargetInstrDescriptors[opCode].resultPos == (int) i;
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operands[i].isDefAndUse = isDefAndUse;
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if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
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operands[i].markDef();
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if (isDefAndUse)
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operands[i].markDefAndUse();
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}
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void
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@ -63,8 +64,6 @@ MachineInstr::SetMachineOperandConst(unsigned int i,
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assert(TargetInstrDescriptors[opCode].resultPos != (int) i &&
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"immed. constant cannot be defined");
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operands[i].InitializeConst(operandType, intValue);
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operands[i].isDef = false;
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operands[i].isDefAndUse = false;
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}
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void
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@ -76,9 +75,10 @@ MachineInstr::SetMachineOperandReg(unsigned int i,
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{
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assert(i < operands.size());
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operands[i].InitializeReg(regNum, isCCReg);
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operands[i].isDef = isdef ||
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TargetInstrDescriptors[opCode].resultPos == (int) i;
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operands[i].isDefAndUse = isDefAndUse;
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if (isdef || TargetInstrDescriptors[opCode].resultPos == (int) i)
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operands[i].markDef();
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if (isDefAndUse)
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operands[i].markDefAndUse();
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regsUsed.insert(regNum);
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}
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@ -101,10 +101,9 @@ static inline std::ostream &OutputValue(std::ostream &os,
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{
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os << "(val ";
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if (val && val->hasName())
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return os << val->getName();
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return os << val->getName() << ")";
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else
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return os << (void*) val; // print address only
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os << ")";
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return os << (void*) val << ")"; // print address only
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}
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std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
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@ -134,38 +133,37 @@ std::ostream &operator<<(std::ostream& os, const MachineInstr& minstr)
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return os << "\n";
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}
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static inline std::ostream &OutputOperand(std::ostream &os,
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const MachineOperand &mop)
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{
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Value* val;
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switch (mop.getOperandType())
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{
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case MachineOperand::MO_CCRegister:
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case MachineOperand::MO_VirtualRegister:
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return OutputValue(os, mop.getVRegValue());
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case MachineOperand::MO_MachineRegister:
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return os << "(" << mop.getMachineRegNum() << ")";
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default:
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assert(0 && "Unknown operand type");
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return os;
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}
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}
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std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
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{
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if (mop.opHiBits32())
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os << "%lm(";
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else if (mop.opLoBits32())
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os << "%lo(";
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else if (mop.opHiBits64())
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os << "%hh(";
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else if (mop.opLoBits64())
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os << "%hm(";
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switch(mop.opType)
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{
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case MachineOperand::MO_VirtualRegister:
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case MachineOperand::MO_MachineRegister:
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os << "%reg";
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return OutputOperand(os, mop);
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OutputValue(os, mop.getVRegValue());
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break;
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case MachineOperand::MO_CCRegister:
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os << "%ccreg";
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return OutputOperand(os, mop);
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OutputValue(os, mop.getVRegValue());
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break;
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case MachineOperand::MO_MachineRegister:
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os << "%reg";
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os << "(" << mop.getMachineRegNum() << ")";
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break;
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case MachineOperand::MO_SignExtendedImmed:
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return os << (long)mop.immedVal;
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os << (long)mop.immedVal;
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break;
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case MachineOperand::MO_UnextendedImmed:
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return os << (long)mop.immedVal;
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os << (long)mop.immedVal;
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break;
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case MachineOperand::MO_PCRelativeDisp:
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{
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const Value* opVal = mop.getVRegValue();
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@ -175,12 +173,18 @@ std::ostream &operator<<(std::ostream &os, const MachineOperand &mop)
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os << opVal->getName();
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else
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os << (const void*) opVal;
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return os << ")";
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os << ")";
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break;
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}
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default:
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assert(0 && "Unrecognized operand type");
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break;
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}
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if (mop.flags &
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(MachineOperand::HIFLAG32 | MachineOperand::LOFLAG32 |
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MachineOperand::HIFLAG64 | MachineOperand::LOFLAG64))
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os << ")";
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return os;
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}
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