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[AArch64][Falkor] Refine loads/stores that require an extra LD pipe.

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llvm-svn: 300976
This commit is contained in:
Chad Rosier 2017-04-21 13:55:41 +00:00
parent 6aaa4fd30c
commit 633c2c7f8f
2 changed files with 21 additions and 5 deletions
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8
lib/Target/AArch64/AArch64SchedFalkorDetails.td
View File

@ -509,10 +509,10 @@ def : InstRW<[WriteVST], (instrs STNPDi, STNPSi)>;
def : InstRW<[WriteSTP], (instrs STNPWi, STNPXi)>;
def : InstRW<[FalkorWr_2LD_1Z_3cyc], (instrs ERET)>;
def : InstRW<[WriteST], (instregex "^LDC.*$")>;
def : InstRW<[WriteST], (instregex "^STLR(B|H|W|X)$")>;
def : InstRW<[WriteST], (instregex "^STXP(W|X)$")>;
def : InstRW<[WriteST], (instregex "^STXR(B|H|W|X)$")>;
def : InstRW<[FalkorWr_1ST_1SD_1LD_3cyc], (instregex "^LDC.*$")>;
def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc], (instregex "^STLR(B|H|W|X)$")>;
def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc], (instregex "^STXP(W|X)$")>;
def : InstRW<[FalkorWr_1ST_1SD_1LD_0cyc], (instregex "^STXR(B|H|W|X)$")>;
def : InstRW<[WriteSTX], (instregex "^STLXP(W|X)$")>;
def : InstRW<[WriteSTX], (instregex "^STLXR(B|H|W|X)$")>;

18
lib/Target/AArch64/AArch64SchedFalkorWriteRes.td
View File

@ -28,7 +28,6 @@
//===----------------------------------------------------------------------===//
// Define 1 micro-op types
def FalkorWr_1X_2cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 2; }
def FalkorWr_1X_4cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 4; }
def FalkorWr_1X_5cyc : SchedWriteRes<[FalkorUnitX]> { let Latency = 5; }
@ -175,18 +174,33 @@ def FalkorWr_1SD_1ST_0cyc: SchedWriteRes<[FalkorUnitSD, FalkorUnitST]> {
//===----------------------------------------------------------------------===//
// Define 3 micro-op types
def FalkorWr_1ST_1SD_1LD_0cyc : SchedWriteRes<[FalkorUnitST, FalkorUnitSD,
FalkorUnitLD]> {
let Latency = 0;
let NumMicroOps = 3;
}
def FalkorWr_1ST_1SD_1LD_3cyc : SchedWriteRes<[FalkorUnitST, FalkorUnitSD,
FalkorUnitLD]> {
let Latency = 3;
let NumMicroOps = 3;
}
def FalkorWr_3VXVY_3cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
let Latency = 3;
let NumMicroOps = 3;
}
def FalkorWr_3VXVY_4cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
let Latency = 4;
let NumMicroOps = 3;
}
def FalkorWr_3VXVY_5cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
let Latency = 5;
let NumMicroOps = 3;
}
def FalkorWr_3VXVY_6cyc : SchedWriteRes<[FalkorUnitVXVY, FalkorUnitVXVY]> {
let Latency = 6;
let NumMicroOps = 3;
@ -196,10 +210,12 @@ def FalkorWr_1LD_2VXVY_4cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitVXVY]> {
let Latency = 4;
let NumMicroOps = 3;
}
def FalkorWr_2LD_1none_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD]> {
let Latency = 3;
let NumMicroOps = 3;
}
def FalkorWr_3LD_3cyc : SchedWriteRes<[FalkorUnitLD, FalkorUnitLD,
FalkorUnitLD]> {
let Latency = 3;